This leverages commit ("s390: Simplify (dis)assembly of insn operands
with const bits") to relax the operand constraints of the immediate
operand that contains the constant Z- or T-bit of the following extended
mnemonics:
risbgz, risbgnz, risbhgz, risblgz, rnsbgt, rosbgt, rxsbgt
Previously those instructions were the only ones where the assembler
on s390 restricted the specification of the subject I3/I4 operand values
exactly according to their specification to an unsigned 6- or 5-bit
unsigned integer. For any other instructions the assembler allows to
specify any operand value allowed by the instruction format, regardless
of whether the instruction specification is more restrictive.
Allow to specify the subject I3/I4 operand as unsigned 8-bit integer
with the constant operand bits being ORed during assembly.
Relax the instructions subject significant operand bit masks to only
consider the Z/T-bit as significant, so that the instructions get
disassembled as their *z or *t flavor regardless of whether any reserved
bits are set in addition to the Z/T-bit.
Adapt the rnsbg, rosbg, and rxsbg test cases not to inadvertently set
the T-bit in operand I3, as they otherwise get disassembled as their
rnsbgt, rosbgt, and rxsbgt counterpart.
This aligns GNU Assembler to LLVM Assembler.
opcodes/
* s390-opc.c (U6_18, U5_27, U6_26): Remove.
(INSTR_RIE_RRUUU2, INSTR_RIE_RRUUU3, INSTR_RIE_RRUUU4): Define
as INSTR_RIE_RRUUU while retaining insn fmt mask.
(MASK_RIE_RRUUU2, MASK_RIE_RRUUU3, MASK_RIE_RRUUU4): Treat only
Z/T-bit of I3/I4 operand as significant.
gas/testsuite/
* gas/s390/zarch-z10.s (rnsbg, rosbg, rxsbg): Do not set T-bit.
Reported-by: Dominik Steenken <dost@de.ibm.com>
Suggested-by: Ulrich Weigand <ulrich.weigand@de.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
(cherry picked from commit b8b60e2d0cb0ab1f235f082dbb8a4e8bc43aadf6)
Simplify assembly and disassembly of extended mnemonics with operands
with constant ORed bits:
Their instruction template already contains the respective constant
operand bits, as they are significant to distinguish the extended from
their base mnemonic. Operands are ORed into the instruction template.
Therefore it is not necessary to OR the constant bits into the operand
value during assembly in s390_insert_operand.
Additionally the constant operand bits from the instruction template
can be used to mask them from the operand value during disassembly in
s390_print_insn_with_opcode. For now do so for non-length unsigned
integer operands only.
The separate instruction formats need to be retained, as their masks
differ, which is relevant during disassembly to distinguish the base
and extended mnemonics from each other.
This affects the following extended mnemonics:
- vfaebs, vfaehs, vfaefs
- vfaezb, vfaezh, vfaezf
- vfaezbs, vfaezhs, vfaezfs
- vstrcbs, vstrchs, vstrcfs
- vstrczb, vstrczh, vstrczf
- vstrczbs, vstrczhs, vstrczfs
- wcefb, wcdgb
- wcelfb, wcdlgb
- wcfeb, wcgdb
- wclfeb, wclgdb
- wfisb, wfidb, wfixb
- wledb, wflrd, wflrx
include/
* opcode/s390.h (S390_OPERAND_OR1, S390_OPERAND_OR2,
S390_OPERAND_OR8): Remove.
opcodes/
* s390-opc.c (U4_OR1_24, U4_OR2_24, U4_OR8_28): Remove.
(INSTR_VRR_VVV0U1, INSTR_VRR_VVV0U2, INSTR_VRR_VVV0U3): Define
as INSTR_VRR_VVV0U0 while retaining respective insn fmt mask.
(INSTR_VRR_VV0UU8): Define as INSTR_VRR_VV0UU while retaining
respective insn fmt mask.
(INSTR_VRR_VVVU0VB1, INSTR_VRR_VVVU0VB2, INSTR_VRR_VVVU0VB3):
Define as INSTR_VRR_VVVU0VB while retaining respective insn fmt
mask.
* s390-dis.c (s390_print_insn_with_opcode): Mask constant
operand bits set in insn template of non-length unsigned
integer operands.
gas/
* config/tc-s390.c (s390_insert_operand): Do not OR constant
operand value bits.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
(cherry picked from commit a3f1e7c56a60573562e8578ae8b675ec1f4448e7)
Support for these extensions is broken and incomplete in the 2.42
branch, with a number of syntax and opcode bugs. This patch removes the
flags and documentation, to avoid any further suggestion that this
extension is fully and correctly supported.
Display -msse-check= default as none for "as --help" since its default
is none, not warning.
PR gas/31389
* config/tc-i386.c (md_show_usage): Change -msse-check= default
to none.
(cherry picked from commit 7a6a03c499ad899c1d1dd93beccbb62795feb1db)
When a symbol is referred with %le_{hi20,lo12,add}_r, it's definitely a
TLS symbol and we should set its type to TLS in the symtab. Otherwise
when building Perl with gcc-14 -flto, we get:
/usr/bin/ld: PL_current_context: TLS definition in
./miniperl.ltrans0.ltrans.o section .tbss mismatches non-TLS reference
in ./miniperl.ltrans1.ltrans.o
A minimal reproducer:
$ cat t1.s
.section .tbss
.globl x
x: .word 0
$ cat t2.s
f:
lu12i.w $a0, %le_hi20_r(x)
add.d $a0, $a0, $tp, %le_add_r(x)
li.w $a1, 1
st.w $a1, $a0, %le_lo12_r(x)
$ gas/as-new t1.s -o t1.o
$ gas/as-new t2.s -o t2.o
$ ld/ld-new t1.o t2.o
ld/ld-new: x: TLS definition in t1.o section .tbss mismatches
non-TLS reference in t2.o
Unfortunately this was undetected before Binutils-2.42 release because
GCC < 14 does not use %le_*_r, and without LTO it's very rare to have a
TLS LE definition and its reference in two different translation units.
So this fix should be backported to Binutils-2.42 branch too.
Signed-off-by: Xi Ruoyao <xry111@xry111.site>
(cherry picked from commit 029e52bac7f3a6dd8b39f7f3d298b73174da806b)
Previous commit a58dc5427f0 intended to bring the following two commits
from master branch:
91cdbed4d7b gas: scfi: untraceable control flow should be a hard error
16cbeae1b27 x86: testsuite: scfi: adjust COFI testcase
But missed adding the testcase files. Fix the failure by adding the
missing files.
gas/testsuite/
* gas/scfi/x86_64/ginsn-cofi-1.l: New test.
* gas/scfi/x86_64/ginsn-cofi-1.s: Likewise.
Restructure the architecture extensions table, add a new table for architecture
version dependencies, add missing architecture extensions, and improve some
extension descriptions.
For R_LARCH_TLS_{LE_HI20_R,LE_ADD_R,LD_PC_HI20,GD_PC_HI20, DESC_PC_HI20}
relocations, start a new frag to get correct eh_frame Call Frame Information
FDE DW_CFA_advance_loc info.
Gcc may generate "\t.align\t%d,54525952,4\n" before commit
b20c7ee066cb7d952fa193972e8bc6362c6e4063. To write 54525952 (NOP) to object
file, we call s_align_ptwo (-4). It result in alignment padding must be a
multiple of 4 if .align has second parameter.
Use default s_align_ptwo for .align.
Commit f530d5f1bab6 ("Update x86/APX: VROUND{P,S}{S,D} can generally be
encoded") took care of only half of the remaining issue. Add #pass here
as well.
Append "#pass" to APX tests for targets which pad text sections with NOPs.
* testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: Append
"#pass".
* testsuite/gas/i386/x86-64-apx-evex-promoted.d: Likewise.
(cherry picked from commit f530d5f1bab6eb5adc65f422ef811fb278a21a4b)
VRNDSCALE{P,S}{S,D} is the AVX512 generalization of these AVX insns. As
long as the immediate has the top 4 bits clear, they are equivalent to
the earlier VEX-encoded insns, and hence can be used to permit use of
eGPR-s in the memory operand. Since this is the normal way of using
these insns, also alter the resulting diagnostic to complain about the
immediate, not the eGPR use.
When there's a suitably disambiguating register operand, suffixes are
generally omitted (unless in suffix-always mode). All NDD insns have a
suitable register operand, so they shouldn't have suffixes by default.
Since SCFI isn't supported on x32:
Fatal error: SCFI is not supported for this ABI
skip SCFI tests for x32 targets.
PR gas/31245
* testsuite/gas/scfi/x86_64/scfi-x86-64.exp: Skip for x32
targets.
(cherry picked from commit 7bd344dd0e0469a93cbbf50f797155278cb76a0b)
Along with the relevant unit-tests, this adds the following rcpc3
instructions:
STL1 { <Vt>.D }[<index>], [<Xn|SP>]
LDAP1 { <Vt>.D }[<index>], [<Xn|SP>]
LDAPUR <Bt>, [<Xn|SP>{, #<simm>}]
LDAPUR <Ht>, [<Xn|SP>{, #<simm>}]
LDAPUR <St>, [<Xn|SP>{, #<simm>}]
LDAPUR <Dt>, [<Xn|SP>{, #<simm>}]
LDAPUR <Qt>, [<Xn|SP>{, #<simm>}]
STLUR <Bt>, [<Xn|SP>{, #<simm>}]
STLUR <Ht>, [<Xn|SP>{, #<simm>}]
STLUR <St>, [<Xn|SP>{, #<simm>}]
STLUR <Dt>, [<Xn|SP>{, #<simm>}]
STLUR <Qt>, [<Xn|SP>{, #<simm>}]
with `#<simm>' taking on a signed 8-bit integer value in the range
[-256,255] and `index' the values 0 or 1.
Co-authored-by: Srinath Parvathaneni <srinath.parvathaneni@arm.com>
The particular choices of address indexing, along with their encoding
for RCPC3 instructions lead to the requirement of a new set of operand
descriptions, along with the relevant inserter/extractor set.
That is, for the integer load/stores, there is only a single valid
indexing offset quantity and offset mode is allowed - The value is
always equivalent to the amount of data read/stored by the
operation and the offset is post-indexed for Load-Acquire RCpc, and
pre-indexed with writeback for Store-Release insns.
This indexing quantity/mode pair is selected by the setting of a
single bit in the instruction. To represent these insns, we add the
following operand types:
- AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND
- AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB
In the case of loads and stores involving SIMD/FP registers, the
optional offset is encoded as an 8-bit signed immediate, but neither
post-indexing or pre-indexing with writeback is available. This
created the need for an operand type similar to
AARCH64_OPND_ADDR_OFFSET, with the difference that FLD_index should
not be checked.
We thus introduce the AARCH64_OPND_RCPC3_ADDR_OFFSET operand, a
variant of AARCH64_OPND_ADDR_OFFSET, w/o the FLD_index bitfield.
Indicating the presence of the Armv8.2-a feature adding further
support for the Release Consistency Model, the `+rcpc3' architectural
extension flag is added to the list of possible `-march' options in
Binutils, together with the necessary macro for encoding rcpc3
instructions.
There are some tlbi operations that don't have a corresponding tlbip operation,
but we were incorrectly using the same list for both. Add the missing tlbi
*nxs operations, and use the F_REG_128 flag to filter tlbi operations that
don't have a tlbip analogue. For increased clarity, I have also used a macro
to reduce duplication between the 'nxs' and non-'nxs' variants, and added a
test to verify that no invalid combinations are accepted.
Additionally, fix two missing checks for AARCH64_OPND_SYSREG_TLBIP that were
preventing disassembly of tlbip instructions.
Hi,
This patch add support for SVE2.1 instructions ld1q,
ld2q, ld3q and ld4q, st1q, st2q, st3q and st4q.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
Hi,
This patch add support for SVE2.1 instruction faddqv,
fmaxnmqv, fmaxqv, fminnmqv and fminqv.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
Hi,
This patch add support for SVE2.1 instruction dupq, eorqv and extq.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
Hi,
This patch add support for FEAT_SVE2p1 (SVE2.1 Extension) feature
along with +sve2p1 optional flag to enabe this feature.
Also support for following SVE2p1 instructions is added
addqv, andqv, smaxqv, sminqv, umaxqv, uminqv and uminqv.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
Hi,
This patch add support for FEAT_SME2p1 and "movaz" instructions
along with the optional flag +sme2p1.
Following "movaz" instructions are add:
Move and zero two ZA tile slices to vector registers.
Move and zero four ZA tile slices to vector registers.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
Hi,
This patch add support for SVE2.1 and SME2.1 non-widening BFloat16
(FEAT_B16B16) instructions.
Following instructions predicated, unpredicated and indexed
variants are added in this patch.
bfadd, bfclamp, bfmax bfmaxnm, bfmin,bfminnm,
bfmla,bfmls,bfmul and bfsub.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
The testsuite for SCFI contains target-specific tests.
When a test is executed with --scfi=experimental command line option,
the CFI annotations in the test .s files are skipped altogether by the
GAS for processing. The CFI directives in the input assembly files are,
however, validated by running the assembler one more time without
--scfi=experimental.
Some testcases are used to highlight those asm constructs that the SCFI
machinery in GAS currently does not support:
- Only System V AMD64 ABI is supported for now. Using either --32 or
--x32 with SCFI results in hard error.
See scfi-unsupported-1.s.
- Untraceable stack-pointer manipulation in function epilougue and prologue.
See scfi-unsupported-2.s.
- Using Dynamically Realigned Arguement Pointer (DRAP) register to
realign the stack. For SCFI, the CFA must be only REG_SP or REG_FP
based. See scfi-unsupported-drap-1.s
Some testcases are used to highlight some diagnostics that the SCFI
machinery in GAS currently issues, with an intent to help user correct
inadvertent errors in their hand-written asm. An error is issued when
GAS finds that input asm is not amenable to correct CFI synthesis.
- (#1) "Warning: SCFI: Asymetrical register restore"
- (#2) "Error: SCFI: usage of REG_FP as scratch not supported"
- (#3) "Error: SCFI: unsupported stack manipulation pattern"
In case of (#2) and (#3), SCFI generation is skipped for the respective
function. Above is a subset of the warnings/errors implemented in the
code.
gas/testsuite/:
* gas/scfi/README: New test.
* gas/scfi/x86_64/ginsn-add-1.l: New test.
* gas/scfi/x86_64/ginsn-add-1.s: New test.
* gas/scfi/x86_64/ginsn-dw2-regnum-1.l: New test.
* gas/scfi/x86_64/ginsn-dw2-regnum-1.s: New test.
* gas/scfi/x86_64/ginsn-pop-1.l: New test.
* gas/scfi/x86_64/ginsn-pop-1.s: New test.
* gas/scfi/x86_64/ginsn-push-1.l: New test.
* gas/scfi/x86_64/ginsn-push-1.s: New test.
* gas/scfi/x86_64/scfi-add-1.d: New test.
* gas/scfi/x86_64/scfi-add-1.l: New test.
* gas/scfi/x86_64/scfi-add-1.s: New test.
* gas/scfi/x86_64/scfi-add-2.d: New test.
* gas/scfi/x86_64/scfi-add-2.l: New test.
* gas/scfi/x86_64/scfi-add-2.s: New test.
* gas/scfi/x86_64/scfi-asm-marker-1.d: New test.
* gas/scfi/x86_64/scfi-asm-marker-1.l: New test.
* gas/scfi/x86_64/scfi-asm-marker-1.s: New test.
* gas/scfi/x86_64/scfi-asm-marker-2.d: New test.
* gas/scfi/x86_64/scfi-asm-marker-2.l: New test.
* gas/scfi/x86_64/scfi-asm-marker-2.s: New test.
* gas/scfi/x86_64/scfi-asm-marker-3.d: New test.
* gas/scfi/x86_64/scfi-asm-marker-3.l: New test.
* gas/scfi/x86_64/scfi-asm-marker-3.s: New test.
* gas/scfi/x86_64/scfi-bp-sp-1.d: New test.
* gas/scfi/x86_64/scfi-bp-sp-1.l: New test.
* gas/scfi/x86_64/scfi-bp-sp-1.s: New test.
* gas/scfi/x86_64/scfi-bp-sp-2.d: New test.
* gas/scfi/x86_64/scfi-bp-sp-2.l: New test.
* gas/scfi/x86_64/scfi-bp-sp-2.s: New test.
* gas/scfi/x86_64/scfi-callee-saved-1.d: New test.
* gas/scfi/x86_64/scfi-callee-saved-1.l: New test.
* gas/scfi/x86_64/scfi-callee-saved-1.s: New test.
* gas/scfi/x86_64/scfi-callee-saved-2.d: New test.
* gas/scfi/x86_64/scfi-callee-saved-2.l: New test.
* gas/scfi/x86_64/scfi-callee-saved-2.s: New test.
* gas/scfi/x86_64/scfi-callee-saved-3.d: New test.
* gas/scfi/x86_64/scfi-callee-saved-3.l: New test.
* gas/scfi/x86_64/scfi-callee-saved-3.s: New test.
* gas/scfi/x86_64/scfi-callee-saved-4.d: New test.
* gas/scfi/x86_64/scfi-callee-saved-4.l: New test.
* gas/scfi/x86_64/scfi-callee-saved-4.s: New test.
* gas/scfi/x86_64/scfi-cfg-1.d: New test.
* gas/scfi/x86_64/scfi-cfg-1.l: New test.
* gas/scfi/x86_64/scfi-cfg-1.s: New test.
* gas/scfi/x86_64/scfi-cfg-2.d: New test.
* gas/scfi/x86_64/scfi-cfg-2.l: New test.
* gas/scfi/x86_64/scfi-cfg-2.s: New test.
* gas/scfi/x86_64/scfi-cfi-label-1.d: New test.
* gas/scfi/x86_64/scfi-cfi-label-1.l: New test.
* gas/scfi/x86_64/scfi-cfi-label-1.s: New test.
* gas/scfi/x86_64/scfi-cfi-sections-1.d: New test.
* gas/scfi/x86_64/scfi-cfi-sections-1.l: New test.
* gas/scfi/x86_64/scfi-cfi-sections-1.s: New test.
* gas/scfi/x86_64/scfi-cofi-1.d: New test.
* gas/scfi/x86_64/scfi-cofi-1.l: New test.
* gas/scfi/x86_64/scfi-cofi-1.s: New test.
* gas/scfi/x86_64/scfi-diag-1.l: New test.
* gas/scfi/x86_64/scfi-diag-1.s: New test.
* gas/scfi/x86_64/scfi-diag-2.l: New test.
* gas/scfi/x86_64/scfi-diag-2.s: New test.
* gas/scfi/x86_64/scfi-dyn-stack-1.d: New test.
* gas/scfi/x86_64/scfi-dyn-stack-1.l: New test.
* gas/scfi/x86_64/scfi-dyn-stack-1.s: New test.
* gas/scfi/x86_64/scfi-enter-1.d: New test.
* gas/scfi/x86_64/scfi-enter-1.l: New test.
* gas/scfi/x86_64/scfi-enter-1.s: New test.
* gas/scfi/x86_64/scfi-fp-diag-2.l: New test.
* gas/scfi/x86_64/scfi-fp-diag-2.s: New test.
* gas/scfi/x86_64/scfi-indirect-mov-1.d: New test.
* gas/scfi/x86_64/scfi-indirect-mov-1.l: New test.
* gas/scfi/x86_64/scfi-indirect-mov-1.s: New test.
* gas/scfi/x86_64/scfi-indirect-mov-2.d: New test.
* gas/scfi/x86_64/scfi-indirect-mov-2.l: New test.
* gas/scfi/x86_64/scfi-indirect-mov-2.s: New test.
* gas/scfi/x86_64/scfi-indirect-mov-3.d: New test.
* gas/scfi/x86_64/scfi-indirect-mov-3.l: New test.
* gas/scfi/x86_64/scfi-indirect-mov-3.s: New test.
* gas/scfi/x86_64/scfi-indirect-mov-4.d: New test.
* gas/scfi/x86_64/scfi-indirect-mov-4.l: New test.
* gas/scfi/x86_64/scfi-indirect-mov-4.s: New test.
* gas/scfi/x86_64/scfi-indirect-mov-5.s: New test.
* gas/scfi/x86_64/scfi-lea-1.d: New test.
* gas/scfi/x86_64/scfi-lea-1.l: New test.
* gas/scfi/x86_64/scfi-lea-1.s: New test.
* gas/scfi/x86_64/scfi-leave-1.d: New test.
* gas/scfi/x86_64/scfi-leave-1.l: New test.
* gas/scfi/x86_64/scfi-leave-1.s: New test.
* gas/scfi/x86_64/scfi-pushq-1.d: New test.
* gas/scfi/x86_64/scfi-pushq-1.l: New test.
* gas/scfi/x86_64/scfi-pushq-1.s: New test.
* gas/scfi/x86_64/scfi-pushsection-1.d: New test.
* gas/scfi/x86_64/scfi-pushsection-1.l: New test.
* gas/scfi/x86_64/scfi-pushsection-1.s: New test.
* gas/scfi/x86_64/scfi-pushsection-2.d: New test.
* gas/scfi/x86_64/scfi-pushsection-2.l: New test.
* gas/scfi/x86_64/scfi-pushsection-2.s: New test.
* gas/scfi/x86_64/scfi-selfalign-func-1.d: New test.
* gas/scfi/x86_64/scfi-selfalign-func-1.l: New test.
* gas/scfi/x86_64/scfi-selfalign-func-1.s: New test.
* gas/scfi/x86_64/scfi-simple-1.d: New test.
* gas/scfi/x86_64/scfi-simple-1.l: New test.
* gas/scfi/x86_64/scfi-simple-1.s: New test.
* gas/scfi/x86_64/scfi-simple-2.d: New test.
* gas/scfi/x86_64/scfi-simple-2.l: New test.
* gas/scfi/x86_64/scfi-simple-2.s: New test.
* gas/scfi/x86_64/scfi-sub-1.d: New test.
* gas/scfi/x86_64/scfi-sub-1.l: New test.
* gas/scfi/x86_64/scfi-sub-1.s: New test.
* gas/scfi/x86_64/scfi-sub-2.d: New test.
* gas/scfi/x86_64/scfi-sub-2.l: New test.
* gas/scfi/x86_64/scfi-sub-2.s: New test.
* gas/scfi/x86_64/scfi-unsupported-1.l: New test.
* gas/scfi/x86_64/scfi-unsupported-1.s: New test.
* gas/scfi/x86_64/scfi-unsupported-2.l: New test.
* gas/scfi/x86_64/scfi-unsupported-2.s: New test.
* gas/scfi/x86_64/scfi-unsupported-3.l: New test.
* gas/scfi/x86_64/scfi-unsupported-3.s: New test.
* gas/scfi/x86_64/scfi-unsupported-4.l: New test.
* gas/scfi/x86_64/scfi-unsupported-4.s: New test.
* gas/scfi/x86_64/scfi-unsupported-cfg-1.l: New test.
* gas/scfi/x86_64/scfi-unsupported-cfg-1.s: New test.
* gas/scfi/x86_64/scfi-unsupported-cfg-2.l: New test.
* gas/scfi/x86_64/scfi-unsupported-cfg-2.s: New test.
* gas/scfi/x86_64/scfi-unsupported-drap-1.l: New test.
* gas/scfi/x86_64/scfi-unsupported-drap-1.s: New test.
* gas/scfi/x86_64/scfi-unsupported-insn-1.l: New test.
* gas/scfi/x86_64/scfi-unsupported-insn-1.s: New test.
* gas/scfi/x86_64/scfi-x86-64.exp: New file.
Add a new listing option, -i, to emit ginsn in the listing output. We
may also emit other SCFI information if necessary in the future.
ginsn are most useful when seen alongside the assembly instructions.
Hence, they are emitted when the user includes the assembly instructions
in the listing output, i.e., "-ali=FILE".
gas/doc/:
* as.texi: Add documentation for the new listing option, -i.
