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RISC-V: Make XVentanaCondOps RV64 only

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Although XVentanaCondOps instructions are XLEN-agonistic, Ventana's manual
only defines them only for RV64 (because all Ventana's processors implement
RV64).

This commit limits XVentanaCondOps instructions RV64-only to match the
behavior of the manual and LLVM.

Note that this commit alone will not make XVentanaCondOps extension with
RV32 invalid (it just makes XVentanaCondOps on RV32 empty).

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Restrict "vt.maskc" and "vt.maskcn"
	to XLEN=64.

gas/ChangeLog:

	* testsuite/gas/riscv/x-ventana-condops-32.d: New failure test.
	* testsuite/gas/riscv/x-ventana-condops-32.l: Likewise.
This commit is contained in:
Tsukasa OI 2023-08-30 01:04:42 +00:00
parent aa1e22eb8d
commit fe0f44a0ca
3 changed files with 8 additions and 2 deletions
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3
gas/testsuite/gas/riscv/x-ventana-condops-32.d Normal file
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@ -0,0 +1,3 @@
#as: -march=rv32i_xventanacondops
#source: x-ventana-condops.s
#error_output: x-ventana-condops-32.l

3
gas/testsuite/gas/riscv/x-ventana-condops-32.l Normal file
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@ -0,0 +1,3 @@
.*Assembler messages:
.*Error: unrecognized opcode `vt.maskc a0,a1,a2'
.*Error: unrecognized opcode `vt.maskcn a0,a3,a4'

4
opcodes/riscv-opc.c
View File

@ -2174,8 +2174,8 @@ const struct riscv_opcode riscv_opcodes[] =
{"th.sync.s", 0, INSN_CLASS_XTHEADSYNC, "", MATCH_TH_SYNC_S, MASK_TH_SYNC_S, match_opcode, 0},
/* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
{"vt.maskc", 0, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },
{"vt.maskcn", 0, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKCN, MASK_VT_MASKCN, match_opcode, 0 },
{"vt.maskc", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },
{"vt.maskcn", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKCN, MASK_VT_MASKCN, match_opcode, 0 },
/* Terminate the list. */
{0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}