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aarch64: Add missing FEAT_MEC dc encodings and gate sysregs
FEAT_MEC support was introduced in [1]. However, the dc instruction was missing these encodings: - DC CIPAE - DC CIGDPAE Furthermore, the Arm ARM states that FEAT_MEC is an optional extension, introduced for v9.2-a. Therefore, these sysregs: - MECIDR_EL2 - MECID_P0_EL2 - MECID_A0_EL2 - MECID_P1_EL2 - MECID_A1_EL2 - VMECID_P_EL2 - VMECID_A_EL2 - MECID_RL_A_EL3 which were introduced in that commit now require -march=armv9.2-a at the very least to be enabled, as well as the dc encodings. opcodes/ChangeLog: * aarch64-opc.c (aarch64_sys_regs_dc): Add "cipae" and "cigdpae". * aarch64-sys-regs.def: Add V8_7A as a requirement for the above system registers. gas/testsuite/gas/ChangeLog * aarch64/mec-invalid.s: Add .arch directive. * aarch64/mec.d: Add .arch directive and check for cipae, cigdpae. * aarch64/mec.s: Add MEC data cache operations test. * aarch64/mec-arch-bad.d: New test to check for bad arch version. * aarch64/mec-arch-bad.l: Above. [1]: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=31f2faf5cf112931cfb8c0564a2b78477c907fe3 Regression tested on aarch64-none-elf
This commit is contained in:
Ezra Sitorus
Richard Earnshaw
parent
89e59ca6dc
commit
f977d551da
4
gas/testsuite/gas/aarch64/mec-arch-bad.d
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4
gas/testsuite/gas/aarch64/mec-arch-bad.d
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@ -0,0 +1,4 @@
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#name: MEC unavailable for architecture below armv9.2-a
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#as: -march=armv9.1-a
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#source: mec.s
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#error_output: mec-arch-bad.l
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18
gas/testsuite/gas/aarch64/mec-arch-bad.l
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18
gas/testsuite/gas/aarch64/mec-arch-bad.l
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@ -0,0 +1,18 @@
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.*: Assembler messages:
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.*: Error: selected processor does not support system register name 'mecidr_el2'
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.*: Error: selected processor does not support system register name 'mecid_p0_el2'
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.*: Error: selected processor does not support system register name 'mecid_a0_el2'
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.*: Error: selected processor does not support system register name 'mecid_p1_el2'
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.*: Error: selected processor does not support system register name 'mecid_a1_el2'
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.*: Error: selected processor does not support system register name 'vmecid_p_el2'
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.*: Error: selected processor does not support system register name 'vmecid_a_el2'
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.*: Error: selected processor does not support system register name 'mecid_rl_a_el3'
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.*: Error: selected processor does not support system register name 'mecid_p0_el2'
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.*: Error: selected processor does not support system register name 'mecid_a0_el2'
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.*: Error: selected processor does not support system register name 'mecid_p1_el2'
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.*: Error: selected processor does not support system register name 'mecid_a1_el2'
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.*: Error: selected processor does not support system register name 'vmecid_p_el2'
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.*: Error: selected processor does not support system register name 'vmecid_a_el2'
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.*: Error: selected processor does not support system register name 'mecid_rl_a_el3'
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.*: Error: selected processor does not support system register name 'cipae'
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.*: Error: selected processor does not support system register name 'cigdpae'
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@ -1,4 +1,6 @@
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// Memory Encryption Contexts, an extension of RME.
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.arch armv9.2-a
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// Illegal write to MEC system registers.
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msr mecidr_el2, x0
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@ -1,4 +1,5 @@
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#name: MEC System registers
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#as: -march=armv9.2-a
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#objdump: -dr
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.*: file format .*
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@ -22,3 +23,5 @@ Disassembly of section .text:
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[^:]*: d51ca900 msr vmecid_p_el2, x0
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[^:]*: d51ca920 msr vmecid_a_el2, x0
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[^:]*: d51eaa20 msr mecid_rl_a_el3, x0
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[^:]*: d50c7e00 dc cipae, x0
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[^:]*: d50c7ee0 dc cigdpae, x0
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@ -18,3 +18,7 @@ msr mecid_a1_el2, x0
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msr vmecid_p_el2, x0
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msr vmecid_a_el2, x0
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msr mecid_rl_a_el3, x0
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// MEC data cache operations.
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dc cipae, x0
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dc cigdpae, x0
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@ -5222,6 +5222,8 @@ const aarch64_sys_ins_reg aarch64_sys_regs_dc[] =
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{ "cisw", CPENS (0, C7, C14, 2), F_HASXT, AARCH64_NO_FEATURES },
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{ "cigsw", CPENS (0, C7, C14, 4), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (MEMTAG) },
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{ "cigdsw", CPENS (0, C7, C14, 6), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (MEMTAG) },
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{ "cipae", CPENS (4, C7, C14, 0), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_7A) },
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{ "cigdpae", CPENS (4, C7, C14, 7), F_HASXT | F_ARCHEXT, AARCH64_FEATURE (V8_7A) },
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{ "cipapa", CPENS (6, C7, C14, 1), F_HASXT, AARCH64_NO_FEATURES },
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{ "cigdpapa", CPENS (6, C7, C14, 5), F_HASXT, AARCH64_NO_FEATURES },
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{ 0, CPENS(0,0,0,0), 0, AARCH64_NO_FEATURES }
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@ -575,12 +575,12 @@
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SYSREG ("mdscr_el1", CPENC (2,0,0,2,2), 0, AARCH64_NO_FEATURES)
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SYSREG ("mdselr_el1", CPENC (2,0,0,4,2), F_ARCHEXT, AARCH64_FEATURE (DEBUGv8p9))
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SYSREG ("mdstepop_el1", CPENC (2,0,0,5,2), F_ARCHEXT, AARCH64_FEATURE (STEP2))
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SYSREG ("mecid_a0_el2", CPENC (3,4,10,8,1), 0, AARCH64_NO_FEATURES)
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SYSREG ("mecid_a1_el2", CPENC (3,4,10,8,3), 0, AARCH64_NO_FEATURES)
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SYSREG ("mecid_p0_el2", CPENC (3,4,10,8,0), 0, AARCH64_NO_FEATURES)
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SYSREG ("mecid_p1_el2", CPENC (3,4,10,8,2), 0, AARCH64_NO_FEATURES)
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SYSREG ("mecid_rl_a_el3", CPENC (3,6,10,10,1), 0, AARCH64_NO_FEATURES)
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SYSREG ("mecidr_el2", CPENC (3,4,10,8,7), F_REG_READ, AARCH64_NO_FEATURES)
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SYSREG ("mecid_a0_el2", CPENC (3,4,10,8,1), F_ARCHEXT, AARCH64_FEATURE (V8_7A))
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SYSREG ("mecid_a1_el2", CPENC (3,4,10,8,3), F_ARCHEXT, AARCH64_FEATURE (V8_7A))
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SYSREG ("mecid_p0_el2", CPENC (3,4,10,8,0), F_ARCHEXT, AARCH64_FEATURE (V8_7A))
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SYSREG ("mecid_p1_el2", CPENC (3,4,10,8,2), F_ARCHEXT, AARCH64_FEATURE (V8_7A))
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SYSREG ("mecid_rl_a_el3", CPENC (3,6,10,10,1), F_ARCHEXT, AARCH64_FEATURE (V8_7A))
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SYSREG ("mecidr_el2", CPENC (3,4,10,8,7), F_REG_READ|F_ARCHEXT, AARCH64_FEATURE (V8_7A))
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SYSREG ("mfar_el3", CPENC (3,6,6,0,5), 0, AARCH64_NO_FEATURES)
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SYSREG ("midr_el1", CPENC (3,0,0,0,0), F_REG_READ, AARCH64_NO_FEATURES)
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SYSREG ("mpam0_el1", CPENC (3,0,10,5,1), 0, AARCH64_NO_FEATURES)
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@ -1233,8 +1233,8 @@
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SYSREG ("vbar_el3", CPENC (3,6,12,0,0), 0, AARCH64_NO_FEATURES)
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SYSREG ("vdisr_el2", CPENC (3,4,12,1,1), F_ARCHEXT, AARCH64_FEATURE (RAS))
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SYSREG ("vdisr_el3", CPENC (3,6,12,1,1), F_ARCHEXT, AARCH64_FEATURE (E3DSE))
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SYSREG ("vmecid_a_el2", CPENC (3,4,10,9,1), 0, AARCH64_NO_FEATURES)
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SYSREG ("vmecid_p_el2", CPENC (3,4,10,9,0), 0, AARCH64_NO_FEATURES)
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SYSREG ("vmecid_a_el2", CPENC (3,4,10,9,1), F_ARCHEXT, AARCH64_FEATURE (V8_7A))
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SYSREG ("vmecid_p_el2", CPENC (3,4,10,9,0), F_ARCHEXT, AARCH64_FEATURE (V8_7A))
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SYSREG ("vmpidr_el2", CPENC (3,4,0,0,5), 0, AARCH64_NO_FEATURES)
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SYSREG ("vncr_el2", CPENC (3,4,2,2,0), F_ARCHEXT, AARCH64_FEATURE (V8_4A))
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SYSREG ("vpidr_el2", CPENC (3,4,0,0,0), 0, AARCH64_NO_FEATURES)
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