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s390: Optionally print instruction description in disassembly
Print instruction description as comment in disassembly with s390 architecture specific option "insndesc": - For objdump it can be enabled with option "-M insndesc" - In gdb it can be enabled with "set disassembler-options insndesc" Since comments are not column aligned the output can enhanced for readability by postprocessing using a filter such as "expand": ... | expand -t 8,16,24,32,40,80 Or when using in combination with objdump option --visualize-jumps: ... | expand | sed -e 's/ *#/\t#/' | expand -t 1,80 Note that the instruction descriptions add about 128 KB to s390-opc.o: s390-opc.o without instruction descriptions: 216368 bytes s390-opc.o with instruction descriptions : 348432 bytes binutils/ * NEWS: Mention new s390-specific disassembler option "insndesc". include/ * opcode/s390.h (struct s390_opcode): Add field to hold instruction description. opcodes/ * s390-mkopc.c: Copy instruction description from s390-opc.txt into generated operation code table s390-opc.tab. * s390-opc.c (s390_opformats): Provide NULL as description in .insn pseudo-mnemonics opcode table. * s390-dis.c: Add s390-specific disassembler option "insndesc" and optionally print the instruction description as comment in the disassembly when it is specified. gas/ * testsuite/gas/s390/s390.exp: Add new test disassembly test case "zarch-insndesc". * testsuite/gas/s390/zarch-insndesc.s: New test case for s390- specific disassembler option "insndesc". * testsuite/gas/s390/zarch-insndesc.d: Likewise. Signed-off-by: Jens Remus <jremus@linux.ibm.com> Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
This commit is contained in:
Jens Remus
Andreas Krebbel
parent
a3fa108623
commit
f96fe7f454
@ -19,6 +19,11 @@
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* objdump --visualize-jumps is now supported on s390 architecture.
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* The s390 disassembly now optionally includes the instruction description as
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comment with the s390-specific disassembler option "insndesc":
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- For objdump it can be enabled with "objdump -M insndesc ...".
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- In gdb it can be enabled with "set disassembler-options insndesc".
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Changes in 2.41:
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* The MIPS port now supports the Sony Interactive Entertainment Allegrex
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@ -37,6 +37,7 @@ if [expr [istarget "s390-*-*"] || [istarget "s390x-*-*"]] then {
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run_dump_test "zarch-operands" "{as -m64} {as -march=z9-109}"
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run_dump_test "zarch-machine" "{as -m64} {as -march=z900}"
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run_dump_test "zarch-optargs" "{as -m64} {as -march=arch12}"
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run_dump_test "zarch-insndesc" "{as -m64}"
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run_list_test "machine-parsing-1" ""
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run_list_test "machine-parsing-2" ""
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run_list_test "machine-parsing-3" ""
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17
gas/testsuite/gas/s390/zarch-insndesc.d
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17
gas/testsuite/gas/s390/zarch-insndesc.d
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@ -0,0 +1,17 @@
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#name: s390x insndesc
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#objdump: -dr -M insndesc
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.*: +file format .*
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Disassembly of section .text:
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.* <foo>:
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.*: b3 95 00 69 [ ]*cdfbr %f6,%r9 # convert from fixed 32 to long bfp
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*([\da-f]+): 84 69 00 00 [ ]*brxh %r6,%r9,\1 <foo\+0x\1> # branch relative on index high
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.*: b2 99 5f ff [ ]*srnm 4095\(%r5\) # set rounding mode
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.*: b9 11 00 96 [ ]*lngfr %r9,%r6 # load negative 64<32
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.*: ec 67 92 1c 26 54 [ ]*rnsbgt %r6,%r7,18,28,38 # rotate then and selected bits and test results
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.*: ec 67 0c 8d 0e 5d [ ]*risbhgz %r6,%r7,12,13,14 # rotate then insert selected bits high and zero remaining bits
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.*: b3 96 37 59 [ ]*cxfbra %f5,3,%r9,7 # convert from 32 bit fixed to extended bfp with rounding mode
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.*: ec 67 0c 94 0e 59 [ ]*risbgnz %r6,%r7,12,20,14 # rotate then insert selected bits and zero remaining bits nocc
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.*: 07 07 [ ]*nopr %r7 # no operation
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10
gas/testsuite/gas/s390/zarch-insndesc.s
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10
gas/testsuite/gas/s390/zarch-insndesc.s
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@ -0,0 +1,10 @@
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.text
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foo:
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cdfbr %f6,%r9
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brxh %r6,%r9,.
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srnm 4095(%r5)
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lngfr %r9,%r6
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rnsbgt %r6,%r7,18,28,38
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risbhgz %r6,%r7,12,13,14
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cxfbra %f5,3,%r9,7
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risbgnz %r6,%r7,12,20,14
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@ -81,7 +81,7 @@ enum s390_opcode_cpu_val
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struct s390_opcode
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{
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/* The opcode name. */
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/* The opcode name (mnemonic). */
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const char * name;
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/* The opcode itself. Those bits which will be filled in with
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@ -110,6 +110,9 @@ struct s390_opcode
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/* Instruction specific flags. */
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unsigned int flags;
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/* Instruction description. */
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const char * description;
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};
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/* The table itself is sorted by major opcode number, and is otherwise
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@ -31,6 +31,7 @@
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static int opc_index[256];
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static int current_arch_mask = 0;
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static int option_use_insn_len_bits_p = 0;
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static int option_print_insn_desc = 0;
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typedef struct
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{
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@ -43,7 +44,8 @@ static const s390_options_t options[] =
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{ "esa" , N_("Disassemble in ESA architecture mode") },
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{ "zarch", N_("Disassemble in z/Architecture mode") },
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{ "insnlength", N_("Print unknown instructions according to "
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"length from first two bits") }
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"length from first two bits") },
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{ "insndesc", N_("Print instruction description as comment") },
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};
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/* Set up index table for first opcode byte. */
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@ -63,6 +65,7 @@ disassemble_init_s390 (struct disassemble_info *info)
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current_arch_mask = 1 << S390_OPCODE_ZARCH;
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option_use_insn_len_bits_p = 0;
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option_print_insn_desc = 0;
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for (p = info->disassembler_options; p != NULL; )
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{
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@ -72,6 +75,8 @@ disassemble_init_s390 (struct disassemble_info *info)
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current_arch_mask = 1 << S390_OPCODE_ZARCH;
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else if (startswith (p, "insnlength"))
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option_use_insn_len_bits_p = 1;
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else if (startswith (p, "insndesc"))
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option_print_insn_desc = 1;
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else
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/* xgettext:c-format */
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opcodes_error_handler (_("unknown S/390 disassembler option: %s"), p);
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@ -311,6 +316,12 @@ s390_print_insn_with_opcode (bfd_vma memaddr,
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else
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separator = ',';
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}
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/* Optional: instruction name. */
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if (option_print_insn_desc && opcode->description
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&& opcode->description[0] != '\0')
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info->fprintf_styled_func (info->stream, dis_style_comment_start, "\t# %s",
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opcode->description);
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}
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/* Check whether opcode A's mask is more specific than that of B. */
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@ -63,6 +63,7 @@ struct op_struct
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int mode_bits;
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int min_cpu;
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int flags;
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char description[MAX_DESCRIPTION_LEN + 1];
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unsigned long long sort_value;
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int no_nibbles;
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@ -84,7 +85,7 @@ createTable (void)
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static void
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insertOpcode (char *opcode, char *mnemonic, char *format,
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int min_cpu, int mode_bits, int flags)
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int min_cpu, int mode_bits, int flags, char* description)
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{
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char *str;
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unsigned long long sort_value;
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@ -132,6 +133,8 @@ insertOpcode (char *opcode, char *mnemonic, char *format,
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op_array[ix].min_cpu = min_cpu;
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op_array[ix].mode_bits = mode_bits;
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op_array[ix].flags = flags;
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strncpy (op_array[ix].description, description, MAX_DESCRIPTION_LEN);
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op_array[ix].description[MAX_DESCRIPTION_LEN] = '\0';
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no_ops++;
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}
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@ -193,7 +196,7 @@ const struct s390_cond_ext_format s390_crb_extensions[NUM_CRB_EXTENSIONS] =
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static void
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insertExpandedMnemonic (char *opcode, char *mnemonic, char *format,
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int min_cpu, int mode_bits, int flags)
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int min_cpu, int mode_bits, int flags, char *description)
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{
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char *tag;
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char prefix[MAX_MNEMONIC_LEN + 1];
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@ -206,7 +209,7 @@ insertExpandedMnemonic (char *opcode, char *mnemonic, char *format,
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if (!(tag = strpbrk (mnemonic, "*$")))
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{
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insertOpcode (opcode, mnemonic, format, min_cpu, mode_bits, flags);
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insertOpcode (opcode, mnemonic, format, min_cpu, mode_bits, flags, description);
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return;
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}
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@ -290,7 +293,7 @@ insertExpandedMnemonic (char *opcode, char *mnemonic, char *format,
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return;
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}
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insertOpcode (opcode, new_mnemonic, format, min_cpu, mode_bits, flags);
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insertOpcode (opcode, new_mnemonic, format, min_cpu, mode_bits, flags, description);
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}
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return;
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@ -311,7 +314,8 @@ static const char file_header[] =
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" instruction which matches.\n"
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" MODE_BITS - zarch or esa\n"
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" MIN_CPU - number of the min cpu level required\n"
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" FLAGS - instruction flags. */\n\n"
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" FLAGS - instruction flags.\n"
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" DESCRIPTION - description of the instruction. */\n\n"
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"const struct s390_opcode s390_opcodes[] =\n {\n";
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/* `dumpTable': write opcode table. */
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@ -337,7 +341,8 @@ dumpTable (void)
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op_array[ix].format, op_array[ix].format);
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printf ("%i, ", op_array[ix].mode_bits);
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printf ("%i, ", op_array[ix].min_cpu);
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printf ("%i}", op_array[ix].flags);
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printf ("%i, ", op_array[ix].flags);
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printf ("\"%s\" }", op_array[ix].description);
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if (ix < no_ops-1)
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printf (",\n");
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else
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@ -497,7 +502,7 @@ main (void)
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str++;
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} while (*str != 0);
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}
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insertExpandedMnemonic (opcode, mnemonic, format, min_cpu, mode_bits, flag_bits);
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insertExpandedMnemonic (opcode, mnemonic, format, min_cpu, mode_bits, flag_bits, description);
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continue_loop:
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;
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@ -774,37 +774,37 @@ unused_s390_operands_static_asserts (void)
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const struct s390_opcode s390_opformats[] =
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{
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{ "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0 ,0 },
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{ "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0 ,0 },
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{ "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0 ,0 },
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{ "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0 ,0 },
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{ "rilu", OP8(0x00LL), MASK_RIL_RU, INSTR_RIL_RU, 3, 0 ,0 },
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{ "ris", OP8(0x00LL), MASK_RIS_RURDI, INSTR_RIS_RURDI, 3, 6 ,0 },
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{ "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0 ,0 },
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{ "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0 ,0 },
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{ "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0 ,0 },
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{ "rrs", OP8(0x00LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU, 3, 6 ,0 },
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{ "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0 ,0 },
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{ "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0 ,0 },
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{ "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0 ,0 },
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{ "rsy", OP8(0x00LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3 ,0 },
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{ "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0 ,0 },
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{ "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0 ,0 },
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{ "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR, 3, 0 ,0 },
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{ "rxy", OP8(0x00LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3 ,0 },
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{ "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0 ,0 },
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{ "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0 ,0 },
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{ "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3 ,0 },
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{ "sil", OP8(0x00LL), MASK_SIL_RDI, INSTR_SIL_RDI, 3, 6 ,0 },
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{ "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0 ,0 },
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{ "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0 ,0 },
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{ "ssf", OP8(0x00LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 3, 0 ,0 },
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{ "vrv", OP8(0x00LL), MASK_VRV_VVXRDU, INSTR_VRV_VVXRDU, 3, 9 ,0 },
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{ "vri", OP8(0x00LL), MASK_VRI_VVUUU, INSTR_VRI_VVUUU, 3, 9 ,0 },
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{ "vrx", OP8(0x00LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 3, 9 ,0 },
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{ "vrs", OP8(0x00LL), MASK_VRS_RVRDU, INSTR_VRS_RVRDU, 3, 9 ,0 },
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{ "vrr", OP8(0x00LL), MASK_VRR_VVV0UUU, INSTR_VRR_VVV0UUU, 3, 9 ,0 },
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{ "vsi", OP8(0x00LL), MASK_VSI_URDV, INSTR_VSI_URDV, 3, 10 ,0 },
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{ "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0, 0, NULL },
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{ "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0, 0, NULL },
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{ "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0, 0, NULL },
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{ "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0, 0, NULL },
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{ "rilu", OP8(0x00LL), MASK_RIL_RU, INSTR_RIL_RU, 3, 0, 0, NULL },
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{ "ris", OP8(0x00LL), MASK_RIS_RURDI, INSTR_RIS_RURDI, 3, 6, 0, NULL },
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{ "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0, NULL },
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{ "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0, NULL },
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{ "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0, 0, NULL },
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{ "rrs", OP8(0x00LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU, 3, 6, 0, NULL },
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{ "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0, 0, NULL },
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{ "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0, 0, NULL },
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{ "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0, 0, NULL },
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{ "rsy", OP8(0x00LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3, 0, NULL },
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{ "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0, NULL },
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{ "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0, 0, NULL },
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{ "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR, 3, 0, 0, NULL },
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{ "rxy", OP8(0x00LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3, 0, NULL },
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{ "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0, NULL },
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{ "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0, 0, NULL },
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{ "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3, 0, NULL },
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{ "sil", OP8(0x00LL), MASK_SIL_RDI, INSTR_SIL_RDI, 3, 6, 0, NULL },
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{ "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0, 0, NULL },
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{ "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0, 0, NULL },
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{ "ssf", OP8(0x00LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 3, 0, 0, NULL },
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{ "vrv", OP8(0x00LL), MASK_VRV_VVXRDU, INSTR_VRV_VVXRDU, 3, 9, 0, NULL },
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{ "vri", OP8(0x00LL), MASK_VRI_VVUUU, INSTR_VRI_VVUUU, 3, 9, 0, NULL },
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{ "vrx", OP8(0x00LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 3, 9, 0, NULL },
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{ "vrs", OP8(0x00LL), MASK_VRS_RVRDU, INSTR_VRS_RVRDU, 3, 9, 0, NULL },
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{ "vrr", OP8(0x00LL), MASK_VRR_VVV0UUU, INSTR_VRR_VVV0UUU, 3, 9, 0, NULL },
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{ "vsi", OP8(0x00LL), MASK_VSI_URDV, INSTR_VSI_URDV, 3, 10, 0, NULL },
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};
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const int s390_num_opformats =
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