mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2025-03-19 13:51:44 +08:00
* alldeps.mak, configure.in, i860-break.h, i860-opcode.h,
i860-pinsn.c, i860-tdep.c, config/i860/*: Remove incomplete i860 support that can't be integrated anyway due to lack of clear authorship.
This commit is contained in:
Fred Fish
parent
ccf1e898d7
commit
f747d2596a
@ -241,6 +241,10 @@ xcoffsolib.c
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xcoffsolib.h
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z8k-tdep.c
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# Things which are explicitly *not* kept, for now.
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# state.c - Not used at the moment, keep for reference (fnf)
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# state.h - Not used at the moment, keep for reference (fnf)
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Do-last:
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echo Thawing away the \"chill\"...
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@ -36,8 +36,6 @@ i386mach-nat.c\
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i386v-nat.c\
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i386v4-nat.c\
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i387-tdep.c\
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i860-pinsn.c\
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i860-tdep.c\
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i960-pinsn.c\
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i960-tdep.c\
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infptrace.c\
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@ -139,8 +137,6 @@ ALLPARAM=\
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./config/i386/xm-linux.h\
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./config/i386/xm-sun386.h\
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./config/i386/xm-symmetry.h\
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./config/i860/tm-stratus.h\
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./config/i860/xm-stratus.h\
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./config/i960/tm-nindy960.h\
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./config/i960/tm-vx960.h\
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./config/m68k/nm-apollo68b.h\
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@ -266,8 +262,6 @@ ALLCONFIG=\
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./config/i386/sun386.mt\
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./config/i386/symmetry.mh\
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./config/i386/symmetry.mt\
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./config/i860/stratus.mh\
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./config/i860/stratus.mt\
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./config/i960/nindy960.mt\
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./config/i960/vxworks960.mt\
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./config/m68k/3b1.mh\
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@ -47,8 +47,6 @@ i[34]86-*-sysv32) gdb_host=i386v32 ;;
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i[34]86-*-sysv4*) gdb_host=i386v4 ;;
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i[34]86-*-sysv*) gdb_host=i386v ;;
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i860-*-*) gdb_host=stratus ;;
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m680[01]0-sun-sunos3*) gdb_host=sun2os3 ;;
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m680[01]0-sun-sunos4*) gdb_host=sun2os4 ;;
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m68030-sony-*) gdb_host=news1000 ;;
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@ -169,8 +167,6 @@ i[34]86-*-sco*) gdb_target=i386v ;;
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i[34]86-*-sysv*) gdb_target=i386v ;;
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i[34]86-*-linux) gdb_target=linux ;;
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i860-*-*) gdb_target=stratus ;;
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i960-*-bout) gdb_target=vxworks960 ;;
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i960-*-coff) gdb_target=nindy960 ;;
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i960-*-elf) gdb_target=nindy960 ;;
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@ -1,83 +0,0 @@
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/* I860 -specific breakpoint stuff.
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Copyright (C) 1986, 1987 Free Software Foundation, Inc.
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GDB is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY. No author or distributor accepts responsibility to anyone
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||||
for the consequences of using it or for whether it serves any
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particular purpose or works at all, unless he says so in writing.
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Refer to the GDB General Public License for full details.
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Everyone is granted permission to copy, modify and redistribute GDB,
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but only under the conditions described in the GDB General Public
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||||
License. A copy of this license is supposed to have been given to you
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along with GDB so you can know your rights and responsibilities. It
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||||
should be in a file named COPYING. Among other things, the copyright
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||||
notice and this notice must be preserved on all copies.
|
||||
|
||||
In other words, go ahead and share GDB, but don't try to stop
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anyone else from sharing it farther. Help stamp out software hoarding!
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*/
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/* #define BREAKPOINT_DEBUG 1 */
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#include "tm.h"
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#ifdef i860
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void i860_insert_breakpoints();
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void i860_dbrk_breakpoints();
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#define BREAKPOINT_HERE(b,pc) ((b->act_addr[0] == pc) || (b->act_addr[1] == pc) ||(b->act_addr[2] == pc) || (b->act_addr[2] == pc))
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/* This is the sequence of bytes we insert for a breakpoint. */
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static char break_insn[] = BREAKPOINT;
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static char float_insn[] = BREAKFLOAT;
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#endif
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#define FOPMSK 0x4C000000
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#define DOPMSK 0x4C000200
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#define FOP860 0x48000000
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#define DOP860 0x48000200
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#define ALN32(a) ((( (int)(a) & 0x0007) == 0x04) )
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#define ALN64(a) ((( (int)(a) & 0x0007) == 0x00) )
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/*
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#define ISFOP(a) ((((adj_read_memory_integer(a)) & FOPMSK)==FOP860 ))
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#define ISCOR(a) ((!(((adj_read_memory_integer(a)) & FOPMSK)==FOP860 )))
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#define ISDOP(a) ((((adj_read_memory_integer(a)) & DOPMSK)==DOP860 ))
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*/
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#define ISFOP(a) ((((adj_read_memory_integer(a)) & FOPMSK)==FOP860 ))
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#define ISCOR(a) ((!(((adj_read_memory_integer(a)) & FOPMSK)==FOP860 )))
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#define ISDOP(a) ((((adj_read_memory_integer(a)) & DOPMSK)==DOP860 ))
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#define ISDIM(a) (\
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( ISDOP(a) && ALN64(a) && ISCOR(a+4)) || \
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((ISFOP(a) && ALN64(a) && ISCOR(a+4)) && (ISDOP(a-8) || ISDOP(a-0x10))) || \
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( ISCOR(a) && ALN32(a) && ISDOP(a-4)) || \
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((ISCOR(a) && ALN32(a) && ISFOP(a+4)) && (ISDOP(a-4) || ISDOP(a-0x0C))) \
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)
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/*
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#define ISDIM(a) (\
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( ISDOP(a) && ALN64(a) && ISCOR(a+4)) || \
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((ISFOP(a) && ALN64(a) && ISCOR(a+4)) && (ISDOP(a-8) || ISDOP(a-16))) || \
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( ISCOR(a) && ALN32(a) && ISDOP(a-4)) || \
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((ISCOR(a) && ALN32(a) && ISFOP(a+4)) && (ISDOP(a-4) || ISDOP(a-12))) \
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)
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*/
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#define FOPADR(a) ( ((int)(a) & 0xFFFFFFF8) )
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#define CORADR(a) ((((int)(a) & 0xFFFFFFFC ) | 0x04) )
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#define DMNEXT(a) ( ISDIM(a)?(ISDIM(a+1)?(a+2):(a+1)):(a+1) )
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#define STDIM (((*(int *)&(registers[REGISTER_BYTE(PS_REGNUM)])) & 0x6000) == 0x2000 )
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#define INDIM (((*(int *)&(registers[REGISTER_BYTE(PS_REGNUM)])) & 0x6000) == 0x4000 )
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#define ENDIM (((*(int *)&(registers[REGISTER_BYTE(PS_REGNUM)])) & 0x6000) == 0x6000 )
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#define DIM 8
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#define RIM 0x8004
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#define SIM 4
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#define ADDR_INC(a) (((int)(a) & 0x0FFF))
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#define SINGLE_STEP_MODE 1
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#define BREAK_MODE 0
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@ -1,134 +0,0 @@
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/* Intel I860 opcde list for GDB, the GNU debugger.
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Copyright (C) 1986, 1987 Free Software Foundation, Inc.
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GDB is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY. No author or distributor accepts responsibility to anyone
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||||
for the consequences of using it or for whether it serves any
|
||||
particular purpose or works at all, unless he says so in writing.
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||||
Refer to the GDB General Public License for full details.
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||||
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Everyone is granted permission to copy, modify and redistribute GDB,
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||||
but only under the conditions described in the GDB General Public
|
||||
License. A copy of this license is supposed to have been given to you
|
||||
along with GDB so you can know your rights and responsibilities. It
|
||||
should be in a file named COPYING. Among other things, the copyright
|
||||
notice and this notice must be preserved on all copies.
|
||||
|
||||
In other words, go ahead and share GDB, but don't try to stop
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||||
anyone else from sharing it farther. Help stamp out software hoarding!
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||||
*/
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#ifdef BIG_ENDIAN
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struct gen_fmt
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{
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unsigned op1 : 6;
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unsigned src2 : 5;
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unsigned dest : 5;
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unsigned src1 : 5;
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unsigned offset : 11;
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};
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struct geni_fmt
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{
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unsigned op1 : 6;
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unsigned src2 : 5;
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unsigned dest : 5;
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unsigned offset : 16;
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};
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struct esc_fmt
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{
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unsigned op1 : 6;
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unsigned res1 : 10;
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unsigned src1 : 5;
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unsigned res2 : 6;
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unsigned op2 : 5;
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};
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struct ctrl_fmt
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{
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unsigned op1 : 6;
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unsigned int offset : 26;
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};
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struct fp_fmt
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{
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unsigned op1 : 6;
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unsigned src2 : 5;
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unsigned dest : 5;
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unsigned src1 : 5;
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unsigned p : 1;
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unsigned d : 1;
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unsigned s : 1;
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unsigned r : 1;
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unsigned op2 : 7;
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};
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union insn_fmt
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{
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struct gen_fmt gen;
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struct geni_fmt geni;
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struct esc_fmt esc;
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struct ctrl_fmt ctrl;
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struct fp_fmt fp;
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long int_val;
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};
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#else
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struct gen_fmt
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{
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unsigned offset : 11;
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unsigned src1 : 5;
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unsigned dest : 5;
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unsigned src2 : 5;
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unsigned op1 : 6;
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};
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struct geni_fmt
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{
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unsigned offset : 16;
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unsigned dest : 5;
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unsigned src2 : 5;
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unsigned op1 : 6;
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};
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struct esc_fmt
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{
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unsigned op2 : 5;
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unsigned res2 : 6;
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unsigned src1 : 5;
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unsigned res1 : 10;
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unsigned op1 : 6;
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};
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struct ctrl_fmt
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{
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unsigned int offset : 26;
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unsigned op1 : 6;
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};
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struct fp_fmt
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{
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unsigned op2 : 7;
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unsigned r : 1;
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unsigned s : 1;
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unsigned d : 1;
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unsigned p : 1;
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unsigned src1 : 5;
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unsigned dest : 5;
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unsigned src2 : 5;
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unsigned op1 : 6;
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};
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union insn_fmt
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{
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struct gen_fmt gen;
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struct geni_fmt geni;
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struct esc_fmt esc;
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struct ctrl_fmt ctrl;
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struct fp_fmt fp;
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long int_val;
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};
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#endif
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typedef enum
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{
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Error, not_branch, uncond, uncond_d, cond, cond_d
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} branch_type;
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658
gdb/i860-pinsn.c
658
gdb/i860-pinsn.c
@ -1,658 +0,0 @@
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/* Print i860 instructions for GDB, the GNU debugger.
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Copyright (C) 1986, 1987 Free Software Foundation, Inc.
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Contributed by Michael Tiemann (tiemann@mcc.com)
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GDB is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY. No author or distributor accepts responsibility to anyone
|
||||
for the consequences of using it or for whether it serves any
|
||||
particular purpose or works at all, unless he says so in writing.
|
||||
Refer to the GDB General Public License for full details.
|
||||
|
||||
Everyone is granted permission to copy, modify and redistribute GDB,
|
||||
but only under the conditions described in the GDB General Public
|
||||
License. A copy of this license is supposed to have been given to you
|
||||
along with GDB so you can know your rights and responsibilities. It
|
||||
should be in a file named COPYING. Among other things, the copyright
|
||||
notice and this notice must be preserved on all copies.
|
||||
|
||||
In other words, go ahead and share GDB, but don't try to stop
|
||||
anyone else from sharing it farther. Help stamp out software hoarding!
|
||||
*/
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#include <stdio.h>
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#include "defs.h"
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#include "i860/tm-i860.h"
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#include "i860-opcode.h"
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/* i860 instructions are never longer than this many bytes. */
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#define MAXLEN 4
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static int fp_instr();
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static void fld_offset();
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static void gen_rrr();
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static void gen_irr();
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static void ctrl_a();
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/*
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* integer registers names
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*/
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static char *ireg[32] =
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{
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"r0", "r1", "sp", "fp", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
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"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
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"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
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};
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/*
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* Control registers of the ld.c and st.c instructions
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*/
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static char *ctlreg[32] =
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{
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||||
"fir", "psr", "dirbase", "db", "fsr", "?", "?", "?",
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||||
"?", "?", "?", "?", "?", "?", "?", "?",
|
||||
"?", "?", "?", "?", "?", "?", "?", "?",
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||||
"?", "?", "?", "?", "?", "?", "?", "?"
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||||
};
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||||
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/***********************************************************************
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||||
* Print the i860 instruction at address MEMADDR in debugged memory,
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* on STREAM. Returns length of the instruction, in bytes, which
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* is always 4.
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*/
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||||
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int
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print_insn (memaddr, stream)
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CORE_ADDR memaddr; /* address of the instruction */
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||||
FILE *stream; /* stream on which to write result */
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||||
{
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||||
union insn_fmt insn; /* the instruction we're decoding */
|
||||
long offset; /* the (decoded) offset from the instruction */
|
||||
long split_offset; /* the value of a ld/st-style split offset */
|
||||
int ai; /* autoincrement flag */
|
||||
char suffix; /* length suffix */
|
||||
|
||||
adj_read_memory (memaddr, &insn, MAXLEN);
|
||||
|
||||
/* These offsets used in ld, st, bte, etc. instructions and are formed by
|
||||
* combining 2 separate fields within the instruction and sign-extending
|
||||
* the result
|
||||
*/
|
||||
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split_offset = (insn.gen.dest << 11) | insn.gen.offset;
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||||
split_offset = SIGN_EXT(16, split_offset);
|
||||
|
||||
|
||||
switch (insn.gen.op1)
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||||
{
|
||||
case 000:
|
||||
fprintf (stream, "ld.b %s(%s),%s", ireg[insn.gen.src1],
|
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ireg[insn.gen.src2], ireg[insn.gen.dest]);
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break;
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||||
case 001:
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offset = SIGN_EXT(16, insn.geni.offset);
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fprintf (stream, "ld.b 0x%x(%s),%s", offset,
|
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ireg[insn.geni.src2], ireg[insn.geni.dest]);
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break;
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||||
case 002:
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||||
fprintf (stream, "ixfr %s,f%d", ireg[insn.gen.src1], insn.gen.dest);
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||||
break;
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||||
case 003:
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||||
fprintf (stream, "st.b %s,0x%x(%s)", ireg[insn.gen.src1], split_offset,
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||||
ireg[insn.geni.src2]);
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break;
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||||
case 004:
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||||
fprintf (stream, "ld.%c %s(%s),%s", (insn.gen.offset & 1) ? 'l' : 's',
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||||
ireg[insn.gen.src1], ireg[insn.gen.src2], ireg[insn.gen.dest]);
|
||||
break;
|
||||
case 005:
|
||||
offset = SIGN_EXT(16, insn.geni.offset);
|
||||
fprintf (stream, "ld.%c 0x%x(%s),%s", (insn.geni.offset & 1) ? 'l' : 's',
|
||||
(offset & ~1), ireg[insn.geni.src2], ireg[insn.geni.dest]);
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||||
break;
|
||||
|
||||
case 007:
|
||||
fprintf (stream, "st.%c %s,0x%x(%s)", (insn.geni.offset & 1) ? 'l' : 's',
|
||||
ireg[insn.gen.src1], (split_offset & ~1), ireg[insn.geni.src2]);
|
||||
break;
|
||||
|
||||
case 010:
|
||||
offset = insn.gen.offset;
|
||||
fld_offset(&offset, &suffix, &ai);
|
||||
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||||
fprintf (stream, "fld.%c %s(%s)%s,f%d", suffix,
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||||
ireg[insn.gen.src1], ireg[insn.gen.src2], ai ? "++" : "",
|
||||
insn.gen.dest);
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||||
break;
|
||||
case 011:
|
||||
offset = SIGN_EXT(16, insn.geni.offset);
|
||||
fld_offset(&offset, &suffix, &ai);
|
||||
|
||||
fprintf (stream, "fld.%c 0x%x(%s)%s,f%d", suffix,
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||||
offset, ireg[insn.gen.src2], ai ? "++" : "", insn.gen.dest);
|
||||
break;
|
||||
case 012:
|
||||
offset = insn.gen.offset;
|
||||
fld_offset(&offset, &suffix, &ai);
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||||
|
||||
fprintf (stream, "fst.%c f%d,%s(%s)%s", suffix,
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insn.gen.dest, ireg[insn.gen.src1], ireg[insn.gen.src2],
|
||||
ai ? "++" : "");
|
||||
break;
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||||
case 013:
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||||
offset = SIGN_EXT(16, insn.geni.offset);
|
||||
fld_offset(&offset, &suffix, &ai);
|
||||
|
||||
fprintf (stream, "fst.%c f%d,0x%x(%s)%s", suffix,
|
||||
insn.gen.dest, offset, ireg[insn.gen.src2], ai ? "++" : "");
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||||
break;
|
||||
case 014:
|
||||
fprintf (stream, "ld.c %s,%s", ctlreg[insn.gen.src2],
|
||||
ireg[insn.gen.dest]);
|
||||
break;
|
||||
case 015:
|
||||
offset = SIGN_EXT(16, insn.geni.offset);
|
||||
fld_offset(&offset, &suffix, &ai);
|
||||
|
||||
fprintf (stream, "flush 0x%x(%s)%s", offset, ireg[insn.gen.src2],
|
||||
ai ? "++" : "");
|
||||
break;
|
||||
case 016:
|
||||
fprintf (stream, "st.c %s,%s", ireg[insn.gen.src1],
|
||||
ctlreg[insn.gen.src2]);
|
||||
break;
|
||||
case 017:
|
||||
offset = SIGN_EXT(16, insn.geni.offset);
|
||||
fld_offset(&offset, &suffix, &ai);
|
||||
|
||||
fprintf (stream, "pst.d f%d,0x%x(%s)%s", insn.gen.dest,
|
||||
offset, ireg[insn.gen.src2], ai ? "++" : "");
|
||||
break;
|
||||
|
||||
case 020:
|
||||
fprintf (stream, "bri %s", ireg[insn.gen.src1]);
|
||||
break;
|
||||
case 021:
|
||||
gen_rrr("trap", insn, stream);
|
||||
break;
|
||||
case 022:
|
||||
/*
|
||||
* Floating-point Opcodes
|
||||
*/
|
||||
if (!fp_instr(insn.fp, stream))
|
||||
fprintf (stream, "0x%08x (invalid instruction)", insn.int_val);
|
||||
break;
|
||||
case 023:
|
||||
/*
|
||||
* Core Escape Opcodes
|
||||
*/
|
||||
switch (insn.esc.op2)
|
||||
{
|
||||
case 1:
|
||||
fprintf (stream, "lock");
|
||||
break;
|
||||
case 2:
|
||||
fprintf (stream, "calli %s", ireg[insn.esc.src1]);
|
||||
break;
|
||||
case 4:
|
||||
fprintf (stream, "intovr");
|
||||
break;
|
||||
case 7:
|
||||
fprintf (stream, "unlock");
|
||||
break;
|
||||
default:
|
||||
fprintf (stream, "0x%08x (invalid instruction)", insn.int_val);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case 024:
|
||||
fprintf (stream, "btne %s,%s,", ireg[insn.gen.src1],
|
||||
ireg[insn.gen.src2]);
|
||||
offset = split_offset << 2;
|
||||
print_address ((CORE_ADDR) (memaddr + 4 + offset), stream);
|
||||
break;
|
||||
case 025:
|
||||
fprintf (stream, "btne 0x%x,%s,", insn.gen.src1, ireg[insn.gen.src2]);
|
||||
offset = split_offset << 2;
|
||||
print_address ((CORE_ADDR) (memaddr + 4 + offset), stream);
|
||||
break;
|
||||
case 026:
|
||||
fprintf (stream, "bte %s,%s,", ireg[insn.gen.src1],
|
||||
ireg[insn.gen.src2]);
|
||||
offset = split_offset << 2;
|
||||
print_address ((CORE_ADDR) (memaddr + 4 + offset), stream);
|
||||
break;
|
||||
case 027:
|
||||
fprintf (stream, "bte 0x%x,%s,", insn.gen.src1, ireg[insn.gen.src2]);
|
||||
offset = split_offset << 2;
|
||||
print_address ((CORE_ADDR) (memaddr + 4 + offset), stream);
|
||||
break;
|
||||
|
||||
case 030:
|
||||
offset = insn.gen.offset;
|
||||
fld_offset(&offset, &suffix, &ai);
|
||||
|
||||
fprintf (stream, "pfld.%c %s(%s)%s,f%d", suffix,
|
||||
ireg[insn.gen.src1], ireg[insn.gen.src2], ai ? "++" : "",
|
||||
insn.gen.dest);
|
||||
break;
|
||||
case 031:
|
||||
offset = SIGN_EXT(16, insn.geni.offset);
|
||||
fld_offset(&offset, &suffix, &ai);
|
||||
|
||||
fprintf (stream, "pfld.%c 0x%x(%s)%s,f%d", suffix,
|
||||
offset, ireg[insn.gen.src2], ai ? "++" : "", insn.gen.dest);
|
||||
break;
|
||||
case 032:
|
||||
ctrl_a("br", insn, memaddr, stream);
|
||||
break;
|
||||
case 033:
|
||||
ctrl_a("call", insn, memaddr, stream);
|
||||
break;
|
||||
case 034:
|
||||
ctrl_a("bc", insn, memaddr, stream);
|
||||
break;
|
||||
case 035:
|
||||
ctrl_a("bc.t", insn, memaddr, stream);
|
||||
break;
|
||||
case 036:
|
||||
ctrl_a("bnc", insn, memaddr, stream);
|
||||
break;
|
||||
case 037:
|
||||
ctrl_a("bnc.t", insn, memaddr, stream);
|
||||
break;
|
||||
|
||||
case 040:
|
||||
gen_rrr("addu", insn, stream);
|
||||
break;
|
||||
case 041:
|
||||
gen_irr("addu", insn, SIGN_EXT(16, insn.geni.offset), stream);
|
||||
break;
|
||||
case 042:
|
||||
gen_rrr("subu", insn, stream);
|
||||
break;
|
||||
case 043:
|
||||
gen_irr("subu", insn, SIGN_EXT(16, insn.geni.offset), stream);
|
||||
break;
|
||||
case 044:
|
||||
gen_rrr("adds", insn, stream);
|
||||
break;
|
||||
case 045:
|
||||
gen_irr("adds", insn, SIGN_EXT(16, insn.geni.offset), stream);
|
||||
break;
|
||||
case 046:
|
||||
gen_rrr("subs", insn, stream);
|
||||
break;
|
||||
case 047:
|
||||
gen_irr("subs", insn, SIGN_EXT(16, insn.geni.offset), stream);
|
||||
break;
|
||||
|
||||
case 050:
|
||||
if (insn.gen.src1 == 0)
|
||||
{
|
||||
if (insn.gen.src2 == 0 && insn.gen.dest == 0)
|
||||
fprintf (stream, "nop");
|
||||
else
|
||||
fprintf (stream, "mov %s,%s", ireg[insn.gen.src2],
|
||||
ireg[insn.gen.dest]);
|
||||
}
|
||||
else
|
||||
gen_rrr("shl", insn, stream);
|
||||
break;
|
||||
case 051:
|
||||
gen_irr("shl", insn, insn.geni.offset, stream);
|
||||
break;
|
||||
case 052:
|
||||
gen_rrr("shr", insn, stream);
|
||||
break;
|
||||
case 053:
|
||||
gen_irr("shr", insn, insn.geni.offset, stream);
|
||||
break;
|
||||
case 054:
|
||||
if (insn.gen.src1 == 0 && insn.gen.src2 == 0 && insn.gen.dest == 0)
|
||||
{
|
||||
if ((insn.int_val & (1 << 9)) != 0)
|
||||
fprintf (stream, "d.");
|
||||
fprintf (stream, "fnop");
|
||||
}
|
||||
else
|
||||
gen_rrr("shrd", insn, stream);
|
||||
break;
|
||||
case 055:
|
||||
fprintf (stream, "bla %s,%s,", ireg[insn.gen.src1],
|
||||
ireg[insn.gen.src2]);
|
||||
offset = split_offset << 2;
|
||||
print_address ((CORE_ADDR) (memaddr + 4 + offset), stream);
|
||||
break;
|
||||
case 056:
|
||||
gen_rrr("shra", insn, stream);
|
||||
break;
|
||||
case 057:
|
||||
gen_irr("shra", insn, insn.geni.offset, stream);
|
||||
break;
|
||||
|
||||
case 060:
|
||||
gen_rrr("and", insn, stream);
|
||||
break;
|
||||
case 061:
|
||||
gen_irr("and", insn, insn.geni.offset, stream);
|
||||
break;
|
||||
|
||||
case 063:
|
||||
gen_irr("andh", insn, insn.geni.offset, stream);
|
||||
break;
|
||||
case 064:
|
||||
gen_rrr("andnot", insn, stream);
|
||||
break;
|
||||
case 065:
|
||||
gen_irr("andnot", insn, insn.geni.offset, stream);
|
||||
break;
|
||||
|
||||
case 067:
|
||||
gen_irr("andnoth", insn, insn.geni.offset, stream);
|
||||
break;
|
||||
|
||||
case 070:
|
||||
gen_rrr("or", insn, stream);
|
||||
break;
|
||||
case 071:
|
||||
gen_irr("or", insn, insn.geni.offset, stream);
|
||||
break;
|
||||
|
||||
case 073:
|
||||
gen_irr("orh", insn, insn.geni.offset, stream);
|
||||
break;
|
||||
case 074:
|
||||
gen_rrr("xor", insn, stream);
|
||||
break;
|
||||
case 075:
|
||||
gen_irr("xor", insn, insn.geni.offset, stream);
|
||||
break;
|
||||
|
||||
case 077:
|
||||
gen_irr("xorh", insn, insn.geni.offset, stream);
|
||||
break;
|
||||
|
||||
default:
|
||||
fprintf (stream, "0x%08x (invalid instruction)", insn.int_val);
|
||||
break;
|
||||
}
|
||||
|
||||
return(4);
|
||||
}
|
||||
|
||||
/* A full list of floating point opcodes - if the entry is NULL, there is
|
||||
* no corresponding instruction
|
||||
*/
|
||||
|
||||
static char *fp_ops[] =
|
||||
{
|
||||
"r2p1", "r2pt", "r2ap1", "r2apt",
|
||||
"i2p1", "i2pt", "i2ap1", "i2apt",
|
||||
"rat1p2", "m12apm", "ra1p2", "m12ttpa",
|
||||
"iat1p2", "m12tpm", "ia1p2", "m12tpa",
|
||||
|
||||
"r2s1", "r2st", "r2as1", "r2ast",
|
||||
"i2s1", "i2st", "i2as1", "i2ast",
|
||||
"rat1s2", "m12asm", "ra1s2", "m12ttsa",
|
||||
"iat1s2", "m12tsm", "ia1s2", "m12tsa",
|
||||
|
||||
"fmul", "fmlow", "frcp", "frsqr",
|
||||
"fmul3", NULL, NULL, NULL,
|
||||
NULL, NULL, NULL, NULL,
|
||||
NULL, NULL, NULL, NULL,
|
||||
|
||||
"fadd", "fsub", "fix", "famov",
|
||||
"fgt", "feq", NULL, NULL,
|
||||
NULL, NULL, "ftrunc", NULL,
|
||||
NULL, NULL, NULL, NULL,
|
||||
|
||||
"fxfr", NULL, NULL, NULL,
|
||||
NULL, NULL, NULL, NULL,
|
||||
NULL, "fiadd", NULL, NULL,
|
||||
NULL, "fisub", NULL, NULL,
|
||||
|
||||
"faddp", "faddz", NULL, NULL,
|
||||
NULL, NULL, NULL, "fzchkl",
|
||||
NULL, NULL, "form", NULL,
|
||||
NULL, NULL, NULL, "fzchks",
|
||||
};
|
||||
|
||||
/* Alternate list of floating point opcodes for PFMAM/PFMSM instructions
|
||||
*/
|
||||
|
||||
static char *alt_fp_ops[] =
|
||||
{
|
||||
"mr2p1", "mr2pt", "mr2mp1", "mr2mpt",
|
||||
"mi2p1", "mi2pt", "mi2mp1", "mi2mpt",
|
||||
"mrmt1p2", "mm12mpm", "mrm1p2", "mm12ttpm",
|
||||
"mimt1p2", "mm12tpm", "mim1p2", "mm12tpm",
|
||||
|
||||
"mr2s1", "mr2st", "mr2ms1", "mr2mst",
|
||||
"mi2s1", "mi2st", "mi2ms1", "mi2mst",
|
||||
"mrmt1s2", "mm12msm", "mrm1s2", "mm12ttsm",
|
||||
"mimt1s2", "mm12tsm", "mim1s2", "mm12tsm",
|
||||
};
|
||||
|
||||
|
||||
/* Floating point precision suffix values - indexed by s and r bits of
|
||||
* instructions.
|
||||
*/
|
||||
|
||||
static char precision[2] =
|
||||
{
|
||||
's', 'd',
|
||||
};
|
||||
|
||||
/***********************************************************************
|
||||
* Print floating-point instruction 'insn' on the indicated stream
|
||||
* Returns 1 if successful, 0 on failure (invalid instruction)
|
||||
*/
|
||||
|
||||
static int
|
||||
fp_instr(insn, stream)
|
||||
struct fp_fmt insn; /* instruction to decode */
|
||||
FILE *stream; /* stream to print on */
|
||||
{
|
||||
char *name; /* the opcode name */
|
||||
|
||||
name = fp_ops[insn.op2];
|
||||
if (name && insn.d)
|
||||
fprintf(stream, "d.");
|
||||
|
||||
|
||||
if (insn.op2 < 0x20)
|
||||
{
|
||||
/*
|
||||
* DPC Ops
|
||||
*/
|
||||
if (insn.p == 0) /* use PFMAM/PFMSM ops if p=0 */
|
||||
name = alt_fp_ops[insn.op2];
|
||||
|
||||
fprintf (stream, "%s.%c%c f%d,f%d,f%d", name,
|
||||
precision[insn.s], precision[insn.r],
|
||||
insn.src1, insn.src2, insn.dest);
|
||||
}
|
||||
else
|
||||
{
|
||||
switch (insn.op2)
|
||||
{
|
||||
case 0x21: /* fmlow (no pipeline allowed) */
|
||||
fprintf (stream, "%s.%c%c f%d,f%d,f%d", name,
|
||||
precision[insn.s], precision[insn.r],
|
||||
insn.src1, insn.src2, insn.dest);
|
||||
break;
|
||||
|
||||
case 0x22: /* frcp */
|
||||
case 0x23: /* fsqrt */
|
||||
fprintf (stream, "%s.%c%c f%d,f%d", name,
|
||||
precision[insn.s], precision[insn.r],
|
||||
insn.src2, insn.dest);
|
||||
break;
|
||||
|
||||
case 0x24: /* pfmul3 */
|
||||
fprintf (stream, "pfmul3.dd f%d,f%d,f%d",
|
||||
insn.src1, insn.src2, insn.dest);
|
||||
break;
|
||||
|
||||
case 0x30: /* fadd */
|
||||
case 0x49: /* fiadd */
|
||||
if (insn.src2 == 0)
|
||||
{
|
||||
/*
|
||||
* Really fmov
|
||||
*/
|
||||
fprintf (stream, "%sfmov.%c%c f%d,f%d", insn.p ? "p" : "",
|
||||
precision[insn.s], precision[insn.r],
|
||||
insn.src1, insn.dest);
|
||||
}
|
||||
else
|
||||
{
|
||||
fprintf (stream, "%s%s.%c%c f%d,f%d,f%d", insn.p ? "p" : "", name,
|
||||
precision[insn.s], precision[insn.r],
|
||||
insn.src1, insn.src2, insn.dest);
|
||||
}
|
||||
break;
|
||||
|
||||
case 0x32: /* fix */
|
||||
case 0x3A: /* ftrunc */
|
||||
fprintf (stream, "%s%s.%c%c f%d,f%d", insn.p ? "p" : "", name,
|
||||
precision[insn.s], precision[insn.r],
|
||||
insn.src1, insn.dest);
|
||||
break;
|
||||
|
||||
case 0x34: /* pfgt/pfle */
|
||||
if (insn.r)
|
||||
name = "fle";
|
||||
fprintf (stream, "p%s.%c%c f%d,f%d,f%d", name,
|
||||
precision[insn.s], precision[insn.s],
|
||||
insn.src1, insn.src2, insn.dest);
|
||||
break;
|
||||
|
||||
case 0x35: /* pfeq */
|
||||
fprintf (stream, "pfeq.%c%c f%d,f%d,f%d",
|
||||
precision[insn.s], precision[insn.r],
|
||||
insn.src1, insn.src2, insn.dest);
|
||||
break;
|
||||
|
||||
case 0x40: /* fxfr */
|
||||
fprintf (stream, "fxfr f%d,%s", insn.src1, ireg[insn.dest]);
|
||||
break;
|
||||
|
||||
case 0x50: /* faddp */
|
||||
case 0x51: /* faddz */
|
||||
case 0x57: /* fzchkl */
|
||||
case 0x5F: /* fzchks */
|
||||
/*
|
||||
* Graphics ops with no precision
|
||||
*/
|
||||
fprintf (stream, "%s%s f%d,f%d,f%d", insn.p ? "p" : "", name,
|
||||
insn.src1, insn.src2, insn.dest);
|
||||
break;
|
||||
|
||||
case 0x5A: /* form */
|
||||
fprintf (stream, "%sform f%d,f%d", insn.p ? "p" : "",
|
||||
insn.src1, insn.dest);
|
||||
break;
|
||||
|
||||
default:
|
||||
/*
|
||||
* All the rest are uniform 3-address, optionally pipelined, etc
|
||||
*/
|
||||
if (name)
|
||||
fprintf (stream, "%s%s.%c%c f%d,f%d,f%d", insn.p ? "p" : "", name,
|
||||
precision[insn.s], precision[insn.r],
|
||||
insn.src1, insn.src2, insn.dest);
|
||||
else
|
||||
return (0);
|
||||
break;
|
||||
}
|
||||
}
|
||||
return (1);
|
||||
}
|
||||
|
||||
/***********************************************************************
|
||||
* Decode fld/fst-style offset encodings into actual offset, precision suffix,
|
||||
* and autoincrement flag
|
||||
*/
|
||||
|
||||
static void
|
||||
fld_offset(offset, suffix, autoincrement)
|
||||
long *offset; /* original and returned offset */
|
||||
char *suffix; /* returned suffix character */
|
||||
int *autoincrement; /* autoincrement flag (1 if ai) */
|
||||
{
|
||||
long off = *offset; /* working copy of *offset */
|
||||
|
||||
*autoincrement = ((off & 1) != 0);
|
||||
|
||||
if (off & 2)
|
||||
{
|
||||
*suffix = 'l';
|
||||
*offset = (off & ~3);
|
||||
}
|
||||
else if (off & 4)
|
||||
{
|
||||
*suffix = 'q';
|
||||
*offset = (off & ~7);
|
||||
}
|
||||
else
|
||||
{
|
||||
*suffix = 'd';
|
||||
*offset = (off & ~7);
|
||||
}
|
||||
}
|
||||
|
||||
/***********************************************************************
|
||||
* Print a general format instruction of the three register form:
|
||||
* op rx,ry,rz
|
||||
*/
|
||||
|
||||
static void
|
||||
gen_rrr(name, insn, stream)
|
||||
char *name;
|
||||
union insn_fmt insn;
|
||||
FILE *stream;
|
||||
{
|
||||
fprintf (stream, "%s %s,%s,%s", name, ireg[insn.gen.src1],
|
||||
ireg[insn.gen.src2], ireg[insn.gen.dest]);
|
||||
}
|
||||
|
||||
/***********************************************************************
|
||||
* Print a general format instruction of the immed + two register form:
|
||||
* op i,ry,rz
|
||||
*/
|
||||
|
||||
static void
|
||||
gen_irr(name, insn, immed, stream)
|
||||
char *name;
|
||||
union insn_fmt insn;
|
||||
long immed;
|
||||
FILE *stream;
|
||||
{
|
||||
fprintf (stream, "%s 0x%x,%s,%s", name, immed,
|
||||
ireg[insn.gen.src2], ireg[insn.gen.dest]);
|
||||
}
|
||||
|
||||
/***********************************************************************
|
||||
* Print a ctrl format instruction with a 26-bit displacement:
|
||||
* op addr
|
||||
*/
|
||||
|
||||
static void
|
||||
ctrl_a(name, insn, memaddr, stream)
|
||||
char *name;
|
||||
union insn_fmt insn;
|
||||
CORE_ADDR memaddr;
|
||||
FILE *stream;
|
||||
{
|
||||
long offset;
|
||||
|
||||
fprintf (stream, "%s ", name);
|
||||
offset = SIGN_EXT(28, insn.ctrl.offset << 2);
|
||||
|
||||
print_address ((CORE_ADDR) (memaddr + 4 + offset), stream);
|
||||
}
|
||||
2224
gdb/i860-tdep.c
2224
gdb/i860-tdep.c
File diff suppressed because it is too large
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Reference in New Issue
Block a user