mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2025-01-30 12:44:10 +08:00
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
This commit is contained in:
Chris Demetriou
parent
06880219d1
commit
f701dad2ba
@ -1,4 +1,14 @@
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2002-02-10 Chris Demetriou cgd@sibyte.com
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2002-02-10 Chris Demetriou <cgd@broadcom.com>
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* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
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DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
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JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
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SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
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ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
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fields (i.e., add and move commas) so that they more closely
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match the MIPS ISA documentation opcode partitioning.
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2002-02-10 Chris Demetriou <cgd@broadcom.com>
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* mips.igen (ADDI): Print immediate value.
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(BREAK): Print code.
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@ -807,7 +807,7 @@
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TRACE_ALU_RESULT2 (HI, LO);
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}
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000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
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000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
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"ddiv r<RS>, r<RT>"
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*mipsIII:
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*mipsIV:
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@ -882,7 +882,7 @@
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TRACE_ALU_RESULT2 (HI, LO);
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}
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000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
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000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
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"div r<RS>, r<RT>"
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*mipsI,mipsII,mipsIII,mipsIV:
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*vr4100:
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@ -915,7 +915,7 @@
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TRACE_ALU_RESULT2 (HI, LO);
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}
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000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
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000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
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"divu r<RS>, r<RT>"
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*mipsI,mipsII,mipsIII,mipsIV:
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*vr4100:
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@ -992,7 +992,7 @@
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do_dmultx (SD_, rs, rt, rd, 1);
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}
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000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
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000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
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"dmult r<RS>, r<RT>"
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*mipsIII,mipsIV:
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*vr4100:
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@ -1000,7 +1000,7 @@
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do_dmult (SD_, RS, RT, 0);
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}
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000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
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000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
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"dmult r<RS>, r<RT>":RD == 0
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"dmult r<RD>, r<RS>, r<RT>"
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*vr5000:
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@ -1015,7 +1015,7 @@
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do_dmultx (SD_, rs, rt, rd, 0);
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}
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000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
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000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
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"dmultu r<RS>, r<RT>"
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*mipsIII,mipsIV:
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*vr4100:
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@ -1023,7 +1023,7 @@
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do_dmultu (SD_, RS, RT, 0);
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}
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000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
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000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
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"dmultu r<RD>, r<RS>, r<RT>":RD == 0
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"dmultu r<RS>, r<RT>"
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*vr5000:
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@ -1043,7 +1043,7 @@
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}
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00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
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000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
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"dsll r<RD>, r<RT>, <SHIFT>"
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*mipsIII:
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*mipsIV:
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@ -1054,7 +1054,7 @@
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}
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00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
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000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
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"dsll32 r<RD>, r<RT>, <SHIFT>"
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*mipsIII:
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*mipsIV:
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@ -1065,7 +1065,7 @@
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GPR[RD] = GPR[RT] << s;
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}
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000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
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000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
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"dsllv r<RD>, r<RT>, r<RS>"
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*mipsIII:
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*mipsIV:
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@ -1081,7 +1081,7 @@
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}
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00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
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000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
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"dsra r<RD>, r<RT>, <SHIFT>"
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*mipsIII:
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*mipsIV:
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@ -1092,7 +1092,7 @@
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}
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00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
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000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
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"dsra32 r<RT>, r<RD>, <SHIFT>"
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*mipsIII:
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*mipsIV:
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@ -1112,7 +1112,7 @@
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TRACE_ALU_RESULT (GPR[rd]);
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}
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000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
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000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
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"dsrav r<RT>, r<RD>, r<RS>"
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*mipsIII:
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*mipsIV:
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@ -1128,7 +1128,7 @@
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}
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00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
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000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
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"dsrl r<RD>, r<RT>, <SHIFT>"
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*mipsIII:
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*mipsIV:
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@ -1139,7 +1139,7 @@
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}
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00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
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000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
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"dsrl32 r<RD>, r<RT>, <SHIFT>"
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*mipsIII:
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*mipsIV:
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@ -1159,7 +1159,7 @@
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000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
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000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
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"dsrlv r<RD>, r<RT>, r<RS>"
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*mipsIII:
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*mipsIV:
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@ -1170,7 +1170,7 @@
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}
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000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
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000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
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"dsub r<RD>, r<RS>, r<RT>"
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*mipsIII:
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*mipsIV:
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@ -1194,7 +1194,7 @@
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TRACE_ALU_RESULT (GPR[rd]);
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}
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000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
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000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
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"dsubu r<RD>, r<RS>, r<RT>"
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*mipsIII:
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*mipsIV:
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@ -1233,7 +1233,7 @@
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DELAY_SLOT (region | (INSTR_INDEX << 2));
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}
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000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
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000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
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"jalr r<RS>":RD == 31
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"jalr r<RD>, r<RS>"
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*mipsI,mipsII,mipsIII,mipsIV:
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@ -1247,7 +1247,7 @@
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}
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000000,5.RS,000000000000000001000:SPECIAL:32::JR
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000000,5.RS,000000000000000,001000:SPECIAL:32::JR
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"jr r<RS>"
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*mipsI,mipsII,mipsIII,mipsIV:
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*vr4100:
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@ -1646,7 +1646,7 @@
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000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
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000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
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"movn r<RD>, r<RS>, r<RT>"
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*mipsIV:
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*vr5000:
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@ -1657,7 +1657,7 @@
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000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
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000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
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"movz r<RD>, r<RS>, r<RT>"
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*mipsIV:
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*vr5000:
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@ -1681,7 +1681,7 @@
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000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
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000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
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"mtlo r<RS>"
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*mipsI,mipsII,mipsIII,mipsIV:
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*vr4100:
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@ -1708,7 +1708,7 @@
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TRACE_ALU_RESULT2 (HI, LO);
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}
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000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
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000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
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"mult r<RS>, r<RT>"
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*mipsI,mipsII,mipsIII,mipsIV:
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*vr4100:
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@ -1717,7 +1717,7 @@
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}
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000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
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000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
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"mult r<RS>, r<RT>":RD == 0
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"mult r<RD>, r<RS>, r<RT>"
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*vr5000:
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@ -1741,7 +1741,7 @@
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TRACE_ALU_RESULT2 (HI, LO);
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}
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000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
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000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
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"multu r<RS>, r<RT>"
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*mipsI,mipsII,mipsIII,mipsIV:
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*vr4100:
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@ -1749,7 +1749,7 @@
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do_multu (SD_, RS, RT, 0);
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}
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000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
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000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
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"multu r<RS>, r<RT>":RD == 0
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"multu r<RD>, r<RS>, r<RT>"
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*vr5000:
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@ -2011,7 +2011,7 @@
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TRACE_ALU_RESULT (GPR[rd]);
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}
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00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
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000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
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"nop":RD == 0 && RT == 0 && SHIFT == 0
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"sll r<RD>, r<RT>, <SHIFT>"
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*mipsI,mipsII,mipsIII,mipsIV:
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@ -2035,7 +2035,7 @@
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TRACE_ALU_RESULT (GPR[rd]);
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}
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000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
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000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
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"sllv r<RD>, r<RT>, r<RS>"
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*mipsI,mipsII,mipsIII,mipsIV:
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*vr4100:
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@ -2053,7 +2053,7 @@
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TRACE_ALU_RESULT (GPR[rd]);
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}
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000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
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000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
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"slt r<RD>, r<RS>, r<RT>"
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*mipsI,mipsII,mipsIII,mipsIV:
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*vr4100:
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@ -2108,7 +2108,7 @@
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TRACE_ALU_RESULT (GPR[rd]);
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}
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000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
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000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
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"sltu r<RD>, r<RS>, r<RT>"
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*mipsI,mipsII,mipsIII,mipsIV:
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*vr4100:
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@ -2148,7 +2148,7 @@
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TRACE_ALU_RESULT (GPR[rd]);
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}
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000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
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000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
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"srav r<RD>, r<RT>, r<RS>"
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*mipsI,mipsII,mipsIII,mipsIV:
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*vr4100:
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@ -2188,7 +2188,7 @@
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TRACE_ALU_RESULT (GPR[rd]);
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}
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000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
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000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
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"srlv r<RD>, r<RT>, r<RS>"
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*mipsI,mipsII,mipsIII,mipsIV:
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*vr4100:
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@ -2199,7 +2199,7 @@
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}
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000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
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000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
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"sub r<RD>, r<RS>, r<RT>"
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*mipsI,mipsII,mipsIII,mipsIV:
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*vr4100:
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@ -2223,7 +2223,7 @@
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TRACE_ALU_RESULT (GPR[rd]);
|
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}
|
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|
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000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
|
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000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
|
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"subu r<RD>, r<RS>, r<RT>"
|
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*mipsI,mipsII,mipsIII,mipsIV:
|
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*vr4100:
|
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@ -2346,7 +2346,7 @@
|
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}
|
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|
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|
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000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
|
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000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
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"sync":STYPE == 0
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"sync <STYPE>"
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*mipsII:
|
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@ -2534,7 +2534,7 @@
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TRACE_ALU_RESULT (GPR[rd]);
|
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}
|
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|
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000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
|
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000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
|
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"xor r<RD>, r<RS>, r<RT>"
|
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*mipsI,mipsII,mipsIII,mipsIV:
|
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*vr4100:
|
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@ -3258,7 +3258,7 @@
|
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|
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// MOVF
|
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// MOVT
|
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000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
|
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000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32::MOVtf
|
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"mov%s<TF> r<RD>, r<RS>, <CC>"
|
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*mipsIV:
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*vr5000:
|
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@ -3809,14 +3809,14 @@
|
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}
|
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|
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|
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010000,10000,000000000000000,111001:COP0:32::DI
|
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010000,1,0000000000000000000,111001:COP0:32::DI
|
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"di"
|
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*mipsI,mipsII,mipsIII,mipsIV:
|
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*vr4100:
|
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*vr5000:
|
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|
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|
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010000,00001,5.RT,5.RD,000,0000,0000:COP0:64::DMFC0
|
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010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
|
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"dmfc0 r<RT>, r<RD>"
|
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*mipsIII,mipsIV:
|
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{
|
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@ -3824,7 +3824,7 @@
|
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}
|
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|
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|
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010000,00101,5.RT,5.RD,000,0000,0000:COP0:64::DMTC0
|
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010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
|
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"dmtc0 r<RT>, r<RD>"
|
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*mipsIII,mipsIV:
|
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{
|
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@ -3832,14 +3832,14 @@
|
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}
|
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|
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|
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010000,10000,000000000000000,111000:COP0:32::EI
|
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010000,1,0000000000000000000,111000:COP0:32::EI
|
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"ei"
|
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*mipsI,mipsII,mipsIII,mipsIV:
|
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*vr4100:
|
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*vr5000:
|
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|
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|
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010000,10000,000000000000000,011000:COP0:32::ERET
|
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010000,1,0000000000000000000,011000:COP0:32::ERET
|
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"eret"
|
||||
*mipsIII:
|
||||
*mipsIV:
|
||||
@ -3884,7 +3884,7 @@
|
||||
}
|
||||
|
||||
|
||||
010000,10000,000000000000000,010000:COP0:32::RFE
|
||||
010000,1,0000000000000000000,010000:COP0:32::RFE
|
||||
"rfe"
|
||||
*mipsI,mipsII,mipsIII,mipsIV:
|
||||
*r3900:
|
||||
@ -3906,28 +3906,28 @@
|
||||
|
||||
|
||||
|
||||
010000,10000,000000000000000,001000:COP0:32::TLBP
|
||||
010000,1,0000000000000000000,001000:COP0:32::TLBP
|
||||
"tlbp"
|
||||
*mipsI,mipsII,mipsIII,mipsIV:
|
||||
*vr4100:
|
||||
*vr5000:
|
||||
|
||||
|
||||
010000,10000,000000000000000,000001:COP0:32::TLBR
|
||||
010000,1,0000000000000000000,000001:COP0:32::TLBR
|
||||
"tlbr"
|
||||
*mipsI,mipsII,mipsIII,mipsIV:
|
||||
*vr4100:
|
||||
*vr5000:
|
||||
|
||||
|
||||
010000,10000,000000000000000,000010:COP0:32::TLBWI
|
||||
010000,1,0000000000000000000,000010:COP0:32::TLBWI
|
||||
"tlbwi"
|
||||
*mipsI,mipsII,mipsIII,mipsIV:
|
||||
*vr4100:
|
||||
*vr5000:
|
||||
|
||||
|
||||
010000,10000,000000000000000,000110:COP0:32::TLBWR
|
||||
010000,1,0000000000000000000,000110:COP0:32::TLBWR
|
||||
"tlbwr"
|
||||
*mipsI,mipsII,mipsIII,mipsIV:
|
||||
*vr4100:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user