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S/390: z13: Accept vector alignment hints
Accept vector alignment hints on z13 although they are ignored there. The advantage is that any binary compiled for architecture level z13 may run on z14 or later and benefit from vector alignment hints. gas/ChangeLog: 2020-05-18 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com> * testsuite/gas/s390/zarch-z13.d: Add regexp checks for vector load/store instruction variants with alignment hints. * testsuite/gas/s390/zarch-z13.s: Emit new vector load/store instruction variants with alignment hints. opcodes/ChangeLog: 2020-05-18 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com> * s390-opc.txt: Relocate vector load/store instructions with additional alignment parameter and change architecture level constraint from z14 to z13.
This commit is contained in:
Stefan Schulze Frielinghaus
parent
8bbc5da5ee
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f687f5f563
@ -17,7 +17,6 @@ Disassembly of section .text:
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.*: e7 f0 fd fc 10 46 [ ]*vgmh %v15,253,252
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.*: e7 f0 fd fc 20 46 [ ]*vgmf %v15,253,252
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.*: e7 f0 fd fc 30 46 [ ]*vgmg %v15,253,252
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.*: e7 f6 9f a0 00 06 [ ]*vl %v15,4000\(%r6,%r9\)
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.*: e7 f1 00 00 04 56 [ ]*vlr %v15,%v17
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.*: e7 f6 9f a0 d0 05 [ ]*vlrep %v15,4000\(%r6,%r9\),13
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.*: e7 f6 9f a0 00 05 [ ]*vlrepb %v15,4000\(%r6,%r9\)
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@ -42,7 +41,6 @@ Disassembly of section .text:
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.*: e7 f6 9f a0 10 04 [ ]*vllezh %v15,4000\(%r6,%r9\)
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.*: e7 f6 9f a0 20 04 [ ]*vllezf %v15,4000\(%r6,%r9\)
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.*: e7 f6 9f a0 30 04 [ ]*vllezg %v15,4000\(%r6,%r9\)
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.*: e7 f1 6f a0 04 36 [ ]*vlm %v15,%v17,4000\(%r6\)
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.*: e7 f6 9f a0 d0 07 [ ]*vlbb %v15,4000\(%r6,%r9\),13
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.*: e7 f6 9f a0 d0 22 [ ]*vlvg %v15,%r6,4000\(%r9\),13
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.*: e7 f6 9f a0 00 22 [ ]*vlvgb %v15,%r6,4000\(%r9\)
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@ -98,12 +96,10 @@ Disassembly of section .text:
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.*: e7 f1 00 00 04 5f [ ]*vsegb %v15,%v17
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.*: e7 f1 00 00 14 5f [ ]*vsegh %v15,%v17
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.*: e7 f1 00 00 24 5f [ ]*vsegf %v15,%v17
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.*: e7 f6 9f a0 00 0e [ ]*vst %v15,4000\(%r6,%r9\)
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.*: e7 f6 9f a0 d0 08 [ ]*vsteb %v15,4000\(%r6,%r9\),13
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.*: e7 f6 9f a0 d0 09 [ ]*vsteh %v15,4000\(%r6,%r9\),13
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.*: e7 f6 9f a0 d0 0b [ ]*vstef %v15,4000\(%r6,%r9\),13
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.*: e7 f6 9f a0 d0 0a [ ]*vsteg %v15,4000\(%r6,%r9\),13
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.*: e7 f1 6f a0 04 3e [ ]*vstm %v15,%v17,4000\(%r6\)
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.*: e7 f6 9f a0 00 3f [ ]*vstl %v15,%r6,4000\(%r9\)
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.*: e7 f1 00 00 d4 d7 [ ]*vuph %v15,%v17,13
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.*: e7 f1 00 00 04 d7 [ ]*vuphb %v15,%v17
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@ -680,3 +676,11 @@ Disassembly of section .text:
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.*: e3 69 b8 f0 fd 3b [ ]*lzrf %r6,-10000\(%r9,%r11\)
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.*: e3 69 b8 f0 fd 2a [ ]*lzrg %r6,-10000\(%r9,%r11\)
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.*: b9 3c 00 69 [ ]*prno %r6,%r9
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.*: e7 f6 9f a0 00 06 [ ]*vl %v15,4000\(%r6,%r9\)
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.*: e7 f6 9f a0 d0 06 [ ]*vl %v15,4000\(%r6,%r9\),13
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.*: e7 f1 6f a0 04 36 [ ]*vlm %v15,%v17,4000\(%r6\)
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.*: e7 f1 6f a0 d4 36 [ ]*vlm %v15,%v17,4000\(%r6\),13
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.*: e7 f6 9f a0 00 0e [ ]*vst %v15,4000\(%r6,%r9\)
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.*: e7 f6 9f a0 d0 0e [ ]*vst %v15,4000\(%r6,%r9\),13
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.*: e7 f1 6f a0 04 3e [ ]*vstm %v15,%v17,4000\(%r6\)
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.*: e7 f1 6f a0 d4 3e [ ]*vstm %v15,%v17,4000\(%r6\),13
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@ -11,7 +11,6 @@ foo:
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vgmh %v15,253,252
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vgmf %v15,253,252
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vgmg %v15,253,252
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vl %v15,4000(%r6,%r9)
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vlr %v15,%v17
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vlrep %v15,4000(%r6,%r9),13
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vlrepb %v15,4000(%r6,%r9)
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@ -36,7 +35,6 @@ foo:
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vllezh %v15,4000(%r6,%r9)
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vllezf %v15,4000(%r6,%r9)
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vllezg %v15,4000(%r6,%r9)
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vlm %v15,%v17,4000(%r6)
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vlbb %v15,4000(%r6,%r9),13
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vlvg %v15,%r6,4000(%r9),13
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vlvgb %v15,%r6,4000(%r9)
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@ -92,12 +90,10 @@ foo:
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vsegb %v15,%v17
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vsegh %v15,%v17
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vsegf %v15,%v17
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vst %v15,4000(%r6,%r9)
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vsteb %v15,4000(%r6,%r9),13
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vsteh %v15,4000(%r6,%r9),13
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vstef %v15,4000(%r6,%r9),13
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vsteg %v15,4000(%r6,%r9),13
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vstm %v15,%v17,4000(%r6)
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vstl %v15,%r6,4000(%r9)
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vuph %v15,%v17,13
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vuphb %v15,%v17
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@ -674,3 +670,11 @@ foo:
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lzrf %r6,-10000(%r9,%r11)
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lzrg %r6,-10000(%r9,%r11)
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ppno %r6,%r9
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vl %v15,4000(%r6,%r9)
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vl %v15,4000(%r6,%r9),13
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vlm %v15,%v17,4000(%r6)
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vlm %v15,%v17,4000(%r6),13
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vst %v15,4000(%r6,%r9)
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vst %v15,4000(%r6,%r9),13
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vstm %v15,%v17,4000(%r6)
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vstm %v15,%v17,4000(%r6),13
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@ -1159,7 +1159,6 @@ e70000000046 vgmb VRI_V0UU "vector generate mask byte" z13 zarch vx
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e70000001046 vgmh VRI_V0UU "vector generate mask halfword" z13 zarch vx
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e70000002046 vgmf VRI_V0UU "vector generate mask word" z13 zarch vx
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e70000003046 vgmg VRI_V0UU "vector generate mask double word" z13 zarch vx
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e70000000006 vl VRX_VRRD "vector memory load" z13 zarch vx
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e70000000056 vlr VRX_VV "vector register load" z13 zarch vx
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e70000000005 vlrep VRX_VRRDU "vector load and replicate" z13 zarch vx
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e70000000005 vlrepb VRX_VRRD "vector load and replicate byte elements" z13 zarch vx
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@ -1184,7 +1183,6 @@ e70000000004 vllezb VRX_VRRD "vector load logical byte element and zero" z13 zar
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e70000001004 vllezh VRX_VRRD "vector load logical halfword element and zero" z13 zarch vx
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e70000002004 vllezf VRX_VRRD "vector load logical word element and zero" z13 zarch vx
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e70000003004 vllezg VRX_VRRD "vector load logical double word element and zero" z13 zarch vx
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e70000000036 vlm VRS_VVRD "vector load multiple" z13 zarch vx
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e70000000007 vlbb VRX_VRRDU "vector load to block boundary" z13 zarch vx
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e70000000022 vlvg VRS_VRRDU "vector load VR element from GR" z13 zarch vx
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e70000000022 vlvgb VRS_VRRD "vector load VR byte element from GR" z13 zarch vx
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@ -1240,12 +1238,10 @@ e7000000005f vseg VRR_VV0U "vector sign extend to double word" z13 zarch vx
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e7000000005f vsegb VRR_VV "vector sign extend byte to double word" z13 zarch vx
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e7000000105f vsegh VRR_VV "vector sign extend halfword to double word" z13 zarch vx
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e7000000205f vsegf VRR_VV "vector sign extend word to double word" z13 zarch vx
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e7000000000e vst VRX_VRRD "vector store" z13 zarch vx
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e70000000008 vsteb VRX_VRRDU "vector store byte element" z13 zarch vx
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e70000000009 vsteh VRX_VRRDU "vector store halfword element" z13 zarch vx
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e7000000000b vstef VRX_VRRDU "vector store word element" z13 zarch vx
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e7000000000a vsteg VRX_VRRDU "vector store double word element" z13 zarch vx
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e7000000003e vstm VRS_VVRD "vector store multiple" z13 zarch vx
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e7000000003f vstl VRS_VRRD "vector store with length" z13 zarch vx
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e700000000d7 vuph VRR_VV0U "vector unpack high" z13 zarch vx
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e700000000d7 vuphb VRR_VV "vector unpack high byte" z13 zarch vx
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@ -1680,6 +1676,13 @@ e3000000003b lzrf RXY_RRRD "load and zero rightmost byte 32->32" z13 zarch
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e3000000002a lzrg RXY_RRRD "load and zero rightmost byte 64->64" z13 zarch
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b93c ppno RRE_RR "perform pseudorandom number operation" z13 zarch
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# Aligned vector store hints
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e70000000006 vl VRX_VRRDU "vector memory load" z13 zarch optparm,vx
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e70000000036 vlm VRS_VVRDU "vector load multiple" z13 zarch optparm,vx
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e7000000000e vst VRX_VRRDU "vector store" z13 zarch optparm,vx
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e7000000003e vstm VRS_VVRDU "vector store multiple" z13 zarch optparm,vx
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# arch12 instructions
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# Vector Enhancements Facility 1
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@ -1881,14 +1884,6 @@ b93c prno RRE_RR "perform pseudorandom number operation" arch12 zarch
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b9a1 tpei RRE_RR "test pending external interruption" arch12 zarch
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b9ac irbm RRE_RR "insert reference bits multiple" arch12 zarch
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# Aligned vector store hints
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e70000000006 vl VRX_VRRDU "vector memory load" arch12 zarch optparm
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e70000000036 vlm VRS_VVRDU "vector load multiple" arch12 zarch optparm
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e7000000000e vst VRX_VRRDU "vector store" arch12 zarch optparm
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e7000000003e vstm VRS_VVRDU "vector store multiple" arch12 zarch optparm
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# arch13 instructions
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