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Arm64: correct 64-bit element fmmla encoding

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There's just one bit of difference to the 32-bit element form, as
per the documentation.
This commit is contained in:
Jan Beulich 2020-01-03 10:12:49 +01:00
parent 4bb7a87e74
commit f4950f76fa
6 changed files with 65 additions and 54 deletions
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5
gas/ChangeLog
View File

@ -1,3 +1,8 @@
2020-01-03 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/aarch64/f64mm.d,
testsuite/gas/aarch64/sve-movprfx-mm.d: Adjust expectations.
2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
* config/tc-z80.c: Add new architectures: Z180 and eZ80. Add

4
gas/testsuite/gas/aarch64/f64mm.d
View File

@ -6,8 +6,8 @@
Disassembly of section \.text:
0+ <\.text>:
*[0-9a-f]+: 64dbe6b1 fmmla z17\.d, z21\.d, z27\.d
*[0-9a-f]+: 64c0e400 fmmla z0\.d, z0\.d, z0\.d
*[0-9a-f]+: 64fbe6b1 fmmla z17\.d, z21\.d, z27\.d
*[0-9a-f]+: 64e0e400 fmmla z0\.d, z0\.d, z0\.d
*[0-9a-f]+: a43b17f1 ld1rob {z17\.b}, p5/z, \[sp, x27\]
*[0-9a-f]+: a42003e0 ld1rob {z0\.b}, p0/z, \[sp, x0\]
*[0-9a-f]+: a4bb17f1 ld1roh {z17\.h}, p5/z, \[sp, x27\]

2
gas/testsuite/gas/aarch64/sve-movprfx-mm.d
View File

@ -21,4 +21,4 @@ Disassembly of section \.text:
*[0-9a-f]+: 0420bc11 movprfx z17, z0
*[0-9a-f]+: 64bbe6b1 fmmla z17\.s, z21\.s, z27\.s
*[0-9a-f]+: 0420bc11 movprfx z17, z0
*[0-9a-f]+: 64dbe6b1 fmmla z17\.d, z21\.d, z27\.d
*[0-9a-f]+: 64fbe6b1 fmmla z17\.d, z21\.d, z27\.d

6
opcodes/ChangeLog
View File

@ -1,3 +1,9 @@
2020-01-03 Jan Beulich <jbeulich@suse.com>
* opcodes/aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
FMMLA encoding.
* opcodes/aarch64-dis-2.c: Re-generate.
2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
* z80-dis.c: Add support for eZ80 and Z80 instructions.

100
opcodes/aarch64-dis-2.c
View File

@ -8839,9 +8839,9 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
if (((word >> 22) & 0x1) == 0)
if (((word >> 20) & 0x1) == 0)
{
if (((word >> 20) & 0x1) == 0)
if (((word >> 22) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
@ -8850,6 +8850,28 @@ aarch64_opcode_lookup_1 (uint32_t word)
return 1869;
}
else
{
if (((word >> 23) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
x11001x00100xxxx111xxxxxxxxxxxxx
st1b. */
return 1872;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
x11001x01100xxxx111xxxxxxxxxxxxx
st1h. */
return 1893;
}
}
}
else
{
if (((word >> 22) & 0x1) == 0)
{
if (((word >> 23) & 0x1) == 0)
{
@ -8868,20 +8890,9 @@ aarch64_opcode_lookup_1 (uint32_t word)
return 1937;
}
}
}
else
{
if (((word >> 23) & 0x1) == 0)
else
{
if (((word >> 20) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
x11001x00100xxxx111xxxxxxxxxxxxx
st1b. */
return 1872;
}
else
if (((word >> 23) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
@ -8889,35 +8900,13 @@ aarch64_opcode_lookup_1 (uint32_t word)
st3b. */
return 1917;
}
}
else
{
if (((word >> 31) & 0x1) == 0)
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
011001x0110xxxxx111xxxxxxxxxxxxx
fmmla. */
return 2398;
}
else
{
if (((word >> 20) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
111001x01100xxxx111xxxxxxxxxxxxx
st1h. */
return 1893;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
111001x01101xxxx111xxxxxxxxxxxxx
st3h. */
return 1921;
}
x11001x01101xxxx111xxxxxxxxxxxxx
st3h. */
return 1921;
}
}
}
@ -9780,21 +9769,32 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
if (((word >> 20) & 0x1) == 0)
if (((word >> 31) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
x11001x01110xxxx111xxxxxxxxxxxxx
st1h. */
return 1895;
011001x0111xxxxx111xxxxxxxxxxxxx
fmmla. */
return 2398;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
x11001x01111xxxx111xxxxxxxxxxxxx
st4h. */
return 1929;
if (((word >> 20) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
111001x01110xxxx111xxxxxxxxxxxxx
st1h. */
return 1895;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
111001x01111xxxx111xxxxxxxxxxxxx
st4h. */
return 1929;
}
}
}
}

2
opcodes/aarch64-tbl.h
View File

@ -5073,7 +5073,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
INT8MATMUL_SVE_INSNC ("usdot", 0x44a01800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0),
INT8MATMUL_SVE_INSNC ("sudot", 0x44a01c00, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0),
F32MATMUL_SVE_INSNC ("fmmla", 0x64a0e400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_S, 0, C_SCAN_MOVPRFX, 0),
F64MATMUL_SVE_INSNC ("fmmla", 0x64c0e400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_D, 0, C_SCAN_MOVPRFX, 0),
F64MATMUL_SVE_INSNC ("fmmla", 0x64e0e400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_D, 0, C_SCAN_MOVPRFX, 0),
F64MATMUL_SVE_INSN ("ld1rob", 0xa4200000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BZU, F_OD(1), 0),
F64MATMUL_SVE_INSN ("ld1roh", 0xa4a00000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_HZU, F_OD(1), 0),
F64MATMUL_SVE_INSN ("ld1row", 0xa5200000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_SZU, F_OD(1), 0),