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* interp.c (load_memory): Add missing "break"'s.

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This commit is contained in:
Gavin Romig-Koch 1998-02-19 15:24:10 +00:00
parent 1ece1d561b
commit f319bab251
2 changed files with 25 additions and 6 deletions
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13
sim/mips/ChangeLog
View File

@ -1,3 +1,16 @@
Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
* interp.c (load_memory): Add missing "break"'s.
Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
* interp.c (sim_store_register, sim_fetch_register): Pass in
length parameter. Return -1.
Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
* interp.c: Added hardware init hook, fixed warnings.
Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
* Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.

18
sim/mips/interp.c
View File

@ -586,11 +586,12 @@ sim_read (sd,addr,buffer,size)
return(index);
}
void
sim_store_register (sd,rn,memory)
int
sim_store_register (sd,rn,memory,length)
SIM_DESC sd;
int rn;
unsigned char *memory;
int length;
{
sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
/* NOTE: gdb (the client) stores registers in target byte order
@ -645,14 +646,15 @@ sim_store_register (sd,rn,memory)
else
cpu->registers[rn] = T2H_8 (*(unsigned64*)memory);
return;
return -1;
}
void
sim_fetch_register (sd,rn,memory)
int
sim_fetch_register (sd,rn,memory,length)
SIM_DESC sd;
int rn;
unsigned char *memory;
int length;
{
sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
/* NOTE: gdb (the client) stores registers in target byte order
@ -703,7 +705,7 @@ sim_fetch_register (sd,rn,memory)
else /* 64bit register */
*(unsigned64*)memory = H2T_8 ((unsigned64)(cpu->registers[rn]));
return;
return -1;
}
@ -1478,12 +1480,15 @@ load_memory (SIM_DESC sd,
case AccessLength_SEPTIBYTE :
value = sim_core_read_misaligned_7 (cpu, NULL_CIA,
sim_core_read_map, pAddr);
break;
case AccessLength_SEXTIBYTE :
value = sim_core_read_misaligned_6 (cpu, NULL_CIA,
sim_core_read_map, pAddr);
break;
case AccessLength_QUINTIBYTE :
value = sim_core_read_misaligned_5 (cpu, NULL_CIA,
sim_core_read_map, pAddr);
break;
case AccessLength_WORD :
value = sim_core_read_aligned_4 (cpu, NULL_CIA,
sim_core_read_map, pAddr);
@ -1491,6 +1496,7 @@ load_memory (SIM_DESC sd,
case AccessLength_TRIPLEBYTE :
value = sim_core_read_misaligned_3 (cpu, NULL_CIA,
sim_core_read_map, pAddr);
break;
case AccessLength_HALFWORD :
value = sim_core_read_aligned_2 (cpu, NULL_CIA,
sim_core_read_map, pAddr);