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[ARC] Fix case-sensitivity for extension instructions.

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In ARC assembler, we accept case insensitive mnemonics, but this was
not the case for extension instruction, fix it and add a test.

gas/
Claudiu Zissulescu <claziss@synopsys.com>

	* config/tc-arc.c (tokenize_extinsn): Convert to lower case the
	name of extension instructions.
	* testsuite/gas/arc/textinsn_case.d: New file.
	* testsuite/gas/arc/textinsn_case.s: Likewise.
This commit is contained in:
claziss 2018-07-23 11:09:43 +02:00 committed by Claudiu Zissulescu
parent 898ade12ee
commit f02806be1f
4 changed files with 26 additions and 0 deletions
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7
gas/ChangeLog
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@ -1,3 +1,10 @@
2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (tokenize_extinsn): Convert to lower case the
name of extension instructions.
* testsuite/gas/arc/textinsn_case.d: New file.
* testsuite/gas/arc/textinsn_case.s: Likewise.
2018-07-22 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (build_vex_prefix): Determine vector

4
gas/config/tc-arc.c
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@ -4369,6 +4369,10 @@ tokenize_extinsn (extInstruction_t *einsn)
insn_name = xstrdup (p);
restore_line_pointer (c);
/* Convert to lower case. */
for (p = insn_name; *p; ++p)
*p = TOLOWER (*p);
/* 2nd: get major opcode. */
if (*input_line_pointer != ',')
{

9
gas/testsuite/gas/arc/textinsn_case.d Normal file
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@ -0,0 +1,9 @@
#objdump: -d
.*: +file format .*arc.*
Disassembly of section .text:
[0-9a-f]+ <test>:
\s+[0-9a-f]+:\s+3a25 00c1\s+aes_qroundf\s+r1,r2,r3

6
gas/testsuite/gas/arc/textinsn_case.s Normal file
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@ -0,0 +1,6 @@
.cpu em
.extInstruction aes_qRoundF, 7, 0x25, SUFFIX_COND, SYNTAX_3OP
.text
test:
aes_qRoundF r1,r2,r3