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https://sourceware.org/git/binutils-gdb.git
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bfd/
* elf64-ppc.c (create_linkage_sections): Align .glink to 8 bytes. (ppc64_elf_build_stubs): Use new lazy linking stub. ld/testsuite/ * ld-powerpc/tlsexe.d: Update for lazy link stub change. * ld-powerpc/tlsexe.r: Likewise. * ld-powerpc/tlsexetoc.d: Likewise. * ld-powerpc/tlsexetoc.r: Likewise. * ld-powerpc/tlsso.d: Likewise. * ld-powerpc/tlstocso.d: Likewise.
This commit is contained in:
Alan Modra
parent
12c0f75707
commit
ee4bf8d232
@ -1,3 +1,8 @@
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2006-08-17 Alan Modra <amodra@bigpond.net.au>
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* elf64-ppc.c (create_linkage_sections): Align .glink to 8 bytes.
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(ppc64_elf_build_stubs): Use new lazy linking stub.
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2006-08-17 Alan Modra <amodra@bigpond.net.au>
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* elf64-ppc.c (ppc64_elf_size_stubs): Ignore non-code sections.
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@ -135,30 +135,29 @@ static bfd_vma opd_entry_value
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#define BCTR 0x4e800420 /* bctr */
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#define ADDIS_R12_R12 0x3d8c0000 /* addis %r12,%r12,off@ha */
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#define ADDIS_R2_R2 0x3c420000 /* addis %r2,%r2,off@ha */
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#define ADDI_R2_R2 0x38420000 /* addi %r2,%r2,off@l */
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#define LD_R2_40R1 0xe8410028 /* ld %r2,40(%r1) */
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/* glink call stub instructions. We enter with the index in R0, and the
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address of glink entry in CTR. From that, we can calculate PLT0. */
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/* glink call stub instructions. We enter with the index in R0. */
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#define GLINK_CALL_STUB_SIZE (16*4)
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#define MFCTR_R12 0x7d8902a6 /* mfctr %r12 */
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#define SLDI_R11_R0_3 0x780b1f24 /* sldi %r11,%r0,3 */
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#define ADDIC_R2_R0_32K 0x34408000 /* addic. %r2,%r0,-32768 */
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#define SUB_R12_R12_R11 0x7d8b6050 /* sub %r12,%r12,%r11 */
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#define SRADI_R2_R2_63 0x7c42fe76 /* sradi %r2,%r2,63 */
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#define SLDI_R11_R0_2 0x780b1764 /* sldi %r11,%r0,2 */
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#define AND_R2_R2_R11 0x7c425838 /* and %r2,%r2,%r11 */
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/* sub %r12,%r12,%r11 */
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#define ADD_R12_R12_R2 0x7d8c1214 /* add %r12,%r12,%r2 */
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#define ADDIS_R12_R12 0x3d8c0000 /* addis %r12,%r12,xxx@ha */
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/* ld %r11,xxx@l(%r12) */
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#define ADDI_R12_R12 0x398c0000 /* addi %r12,%r12,xxx@l */
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/* ld %r2,8(%r12) */
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/* mtctr %r11 */
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/* ld %r11,16(%r12) */
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/* bctr */
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/* 0: */
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/* .quad plt0-1f */
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/* __glink: */
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#define MFLR_R12 0x7d8802a6 /* mflr %12 */
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#define BCL_20_31 0x429f0005 /* bcl 20,31,1f */
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/* 1: */
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#define MFLR_R11 0x7d6802a6 /* mflr %11 */
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#define LD_R2_M16R11 0xe84bfff0 /* ld %2,(0b-1b)(%11) */
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#define MTLR_R12 0x7d8803a6 /* mtlr %12 */
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#define ADD_R12_R2_R11 0x7d825a14 /* add %12,%2,%11 */
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/* ld %11,0(%12) */
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/* ld %2,8(%12) */
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/* mtctr %11 */
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/* ld %11,16(%12) */
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/* bctr */
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/* Pad with this. */
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#define NOP 0x60000000
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@ -3728,7 +3727,7 @@ create_linkage_sections (bfd *dynobj, struct bfd_link_info *info)
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htab->glink = bfd_make_section_anyway_with_flags (dynobj, ".glink",
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flags);
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if (htab->glink == NULL
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|| ! bfd_set_section_alignment (dynobj, htab->glink, 2))
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|| ! bfd_set_section_alignment (dynobj, htab->glink, 3))
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return FALSE;
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/* Create branch lookup table for plt_branch stubs. */
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@ -9458,18 +9457,6 @@ ppc64_elf_build_stubs (bfd_boolean emit_stub_syms,
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bfd_vma plt0;
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/* Build the .glink plt call stub. */
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plt0 = (htab->plt->output_section->vma
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+ htab->plt->output_offset
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- (htab->glink->output_section->vma
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+ htab->glink->output_offset
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+ GLINK_CALL_STUB_SIZE));
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if (plt0 + 0x80008000 > 0xffffffff)
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{
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(*_bfd_error_handler) (_(".glink and .plt too far apart"));
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bfd_set_error (bfd_error_bad_value);
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return FALSE;
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}
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if (htab->emit_stub_syms)
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{
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struct elf_link_hash_entry *h;
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@ -9480,7 +9467,7 @@ ppc64_elf_build_stubs (bfd_boolean emit_stub_syms,
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{
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h->root.type = bfd_link_hash_defined;
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h->root.u.def.section = htab->glink;
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h->root.u.def.value = 0;
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h->root.u.def.value = 8;
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h->ref_regular = 1;
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h->def_regular = 1;
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h->ref_regular_nonweak = 1;
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@ -9489,29 +9476,26 @@ ppc64_elf_build_stubs (bfd_boolean emit_stub_syms,
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}
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}
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p = htab->glink->contents;
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bfd_put_32 (htab->glink->owner, MFCTR_R12, p);
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plt0 = (htab->plt->output_section->vma
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+ htab->plt->output_offset
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- (htab->glink->output_section->vma
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+ htab->glink->output_offset
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+ 16));
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bfd_put_64 (htab->glink->owner, plt0, p);
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p += 8;
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bfd_put_32 (htab->glink->owner, MFLR_R12, p);
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p += 4;
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bfd_put_32 (htab->glink->owner, SLDI_R11_R0_3, p);
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bfd_put_32 (htab->glink->owner, BCL_20_31, p);
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p += 4;
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bfd_put_32 (htab->glink->owner, ADDIC_R2_R0_32K, p);
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bfd_put_32 (htab->glink->owner, MFLR_R11, p);
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p += 4;
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bfd_put_32 (htab->glink->owner, SUB_R12_R12_R11, p);
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bfd_put_32 (htab->glink->owner, LD_R2_M16R11, p);
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p += 4;
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bfd_put_32 (htab->glink->owner, SRADI_R2_R2_63, p);
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bfd_put_32 (htab->glink->owner, MTLR_R12, p);
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p += 4;
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bfd_put_32 (htab->glink->owner, SLDI_R11_R0_2, p);
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bfd_put_32 (htab->glink->owner, ADD_R12_R2_R11, p);
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p += 4;
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bfd_put_32 (htab->glink->owner, AND_R2_R2_R11, p);
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p += 4;
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bfd_put_32 (htab->glink->owner, SUB_R12_R12_R11, p);
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p += 4;
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bfd_put_32 (htab->glink->owner, ADD_R12_R12_R2, p);
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p += 4;
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bfd_put_32 (htab->glink->owner, ADDIS_R12_R12 | PPC_HA (plt0), p);
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p += 4;
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bfd_put_32 (htab->glink->owner, LD_R11_0R12 | PPC_LO (plt0), p);
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p += 4;
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bfd_put_32 (htab->glink->owner, ADDI_R12_R12 | PPC_LO (plt0), p);
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bfd_put_32 (htab->glink->owner, LD_R11_0R12, p);
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p += 4;
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bfd_put_32 (htab->glink->owner, LD_R2_0R12 | 8, p);
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p += 4;
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@ -9521,6 +9505,11 @@ ppc64_elf_build_stubs (bfd_boolean emit_stub_syms,
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p += 4;
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bfd_put_32 (htab->glink->owner, BCTR, p);
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p += 4;
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while (p - htab->glink->contents < GLINK_CALL_STUB_SIZE)
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{
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bfd_put_32 (htab->glink->owner, NOP, p);
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p += 4;
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}
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/* Build the .glink lazy link call stubs. */
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indx = 0;
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@ -9539,7 +9528,7 @@ ppc64_elf_build_stubs (bfd_boolean emit_stub_syms,
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p += 4;
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}
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bfd_put_32 (htab->glink->owner,
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B_DOT | ((htab->glink->contents - p) & 0x3fffffc), p);
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B_DOT | ((htab->glink->contents - p + 8) & 0x3fffffc), p);
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indx++;
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p += 4;
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}
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@ -1,3 +1,12 @@
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2006-08-17 Alan Modra <amodra@bigpond.net.au>
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* ld-powerpc/tlsexe.d: Update for lazy link stub change.
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* ld-powerpc/tlsexe.r: Likewise.
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* ld-powerpc/tlsexetoc.d: Likewise.
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* ld-powerpc/tlsexetoc.r: Likewise.
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* ld-powerpc/tlsso.d: Likewise.
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* ld-powerpc/tlstocso.d: Likewise.
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2006-08-16 H.J. Lu <hongjiu.lu@intel.com>
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PR ld/3015
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@ -56,21 +56,22 @@ Disassembly of section \.text:
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.* e9 4d 90 2a lwa r10,-28632\(r13\)
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.* 3d 2d 00 00 addis r9,r13,0
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.* a9 49 90 30 lha r10,-28624\(r9\)
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.* 7d 89 02 a6 mfctr r12
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.* 78 0b 1f 24 rldicr r11,r0,3,60
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.* 34 40 80 00 addic\. r2,r0,-32768
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.* 7d 8b 60 50 subf r12,r11,r12
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.* 7c 42 fe 76 sradi r2,r2,63
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.* 78 0b 17 64 rldicr r11,r0,2,61
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.* 7c 42 58 38 and r2,r2,r11
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.* 7d 8b 60 50 subf r12,r11,r12
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.* 7d 8c 12 14 add r12,r12,r2
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.* 3d 8c 00 01 addis r12,r12,1
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.* e9 6c 01 c4 ld r11,452\(r12\)
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.* 39 8c 01 c4 addi r12,r12,452
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.* 60 00 00 00 nop
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.* 00 00 00 00 .*
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.* 00 01 01 f0 .*
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.* 7d 88 02 a6 mflr r12
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.* 42 9f 00 05 bcl- 20,4\*cr7\+so,.*
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.* 7d 68 02 a6 mflr r11
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.* e8 4b ff f0 ld r2,-16\(r11\)
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.* 7d 88 03 a6 mtlr r12
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.* 7d 82 5a 14 add r12,r2,r11
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.* e9 6c 00 00 ld r11,0\(r12\)
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.* e8 4c 00 08 ld r2,8\(r12\)
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.* 7d 69 03 a6 mtctr r11
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.* e9 6c 00 10 ld r11,16\(r12\)
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.* 4e 80 04 20 bctr
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.* 60 00 00 00 nop
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.* 60 00 00 00 nop
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.* 60 00 00 00 nop
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.* 38 00 00 00 li r0,0
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.* 4b ff ff bc b .*
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.* 4b ff ff c4 b .*
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@ -16,7 +16,7 @@ Section Headers:
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+\[ 4\] \.dynstr +.*
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+\[ 5\] \.rela\.dyn +.*
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+\[ 6\] \.rela\.plt +.*
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+\[ 7\] \.text +PROGBITS .* 0+fc 0+ +AX +0 +0 +4
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+\[ 7\] \.text +PROGBITS .* 0+100 0+ +AX +0 +0 +8
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+\[ 8\] \.rodata + PROGBITS .* 0+ 0+ +A +0 +0 +8
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+\[ 9\] \.tdata +PROGBITS .* 0+38 0+ WAT +0 +0 +8
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+\[10\] \.tbss +NOBITS .* 0+38 0+ WAT +0 +0 +8
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@ -40,21 +40,22 @@ Disassembly of section \.text:
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.* 89 4d 90 60 lbz r10,-28576\(r13\)
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.* 3d 2d 00 00 addis r9,r13,0
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.* 99 49 90 68 stb r10,-28568\(r9\)
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.* 7d 89 02 a6 mfctr r12
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.* 78 0b 1f 24 rldicr r11,r0,3,60
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.* 34 40 80 00 addic\. r2,r0,-32768
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.* 7d 8b 60 50 subf r12,r11,r12
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.* 7c 42 fe 76 sradi r2,r2,63
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.* 78 0b 17 64 rldicr r11,r0,2,61
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.* 7c 42 58 38 and r2,r2,r11
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.* 7d 8b 60 50 subf r12,r11,r12
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.* 7d 8c 12 14 add r12,r12,r2
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.* 3d 8c 00 01 addis r12,r12,1
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.* e9 6c 01 ec ld r11,492\(r12\)
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.* 39 8c 01 ec addi r12,r12,492
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.* 60 00 00 00 nop
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.* 00 00 00 00 .*
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.* 00 01 02 18 .*
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.* 7d 88 02 a6 mflr r12
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.* 42 9f 00 05 bcl- 20,4\*cr7\+so,.*
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.* 7d 68 02 a6 mflr r11
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.* e8 4b ff f0 ld r2,-16\(r11\)
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.* 7d 88 03 a6 mtlr r12
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.* 7d 82 5a 14 add r12,r2,r11
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.* e9 6c 00 00 ld r11,0\(r12\)
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.* e8 4c 00 08 ld r2,8\(r12\)
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.* 7d 69 03 a6 mtctr r11
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.* e9 6c 00 10 ld r11,16\(r12\)
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.* 4e 80 04 20 bctr
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.* 60 00 00 00 nop
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.* 60 00 00 00 nop
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.* 60 00 00 00 nop
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.* 38 00 00 00 li r0,0
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.* 4b ff ff bc b .*
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.* 4b ff ff c4 b .*
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@ -16,7 +16,7 @@ Section Headers:
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+\[ 4\] \.dynstr +.*
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+\[ 5\] \.rela\.dyn +.*
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+\[ 6\] \.rela\.plt +.*
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+\[ 7\] \.text +PROGBITS .* 0+bc 0+ +AX +0 +0 +4
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+\[ 7\] \.text +PROGBITS .* 0+c0 0+ +AX +0 +0 +8
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+\[ 8\] \.rodata +PROGBITS .* 0+ 0+ +A +0 +0 +8
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+\[ 9\] \.tdata +PROGBITS .* 0+38 0+ WAT +0 +0 +8
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+\[10\] \.tbss +NOBITS .* 0+38 0+ WAT +0 +0 +8
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@ -56,21 +56,22 @@ Disassembly of section \.text:
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.* e9 4d 00 02 lwa r10,0\(r13\)
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.* 3d 2d 00 00 addis r9,r13,0
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.* a9 49 00 00 lha r10,0\(r9\)
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.* 7d 89 02 a6 mfctr r12
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.* 78 0b 1f 24 rldicr r11,r0,3,60
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.* 34 40 80 00 addic\. r2,r0,-32768
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.* 7d 8b 60 50 subf r12,r11,r12
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.* 7c 42 fe 76 sradi r2,r2,63
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.* 78 0b 17 64 rldicr r11,r0,2,61
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.* 7c 42 58 38 and r2,r2,r11
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.* 7d 8b 60 50 subf r12,r11,r12
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.* 7d 8c 12 14 add r12,r12,r2
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.* 3d 8c 00 01 addis r12,r12,1
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.* e9 6c 01 f4 ld r11,500\(r12\)
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.* 39 8c 01 f4 addi r12,r12,500
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.* 60 00 00 00 nop
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.* 00 00 00 00 .*
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.* 00 01 02 20 .*
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.* 7d 88 02 a6 mflr r12
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.* 42 9f 00 05 bcl- 20,4\*cr7\+so,.*
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.* 7d 68 02 a6 mflr r11
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.* e8 4b ff f0 ld r2,-16\(r11\)
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.* 7d 88 03 a6 mtlr r12
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.* 7d 82 5a 14 add r12,r2,r11
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.* e9 6c 00 00 ld r11,0\(r12\)
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.* e8 4c 00 08 ld r2,8\(r12\)
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.* 7d 69 03 a6 mtctr r11
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.* e9 6c 00 10 ld r11,16\(r12\)
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.* 4e 80 04 20 bctr
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.* 60 00 00 00 nop
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.* 60 00 00 00 nop
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.* 60 00 00 00 nop
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.* 38 00 00 00 li r0,0
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.* 4b ff ff bc b .*
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.* 4b ff ff c4 b .*
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@ -40,21 +40,22 @@ Disassembly of section \.text:
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.* 89 4d 00 00 lbz r10,0\(r13\)
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.* 3d 2d 00 00 addis r9,r13,0
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.* 99 49 00 00 stb r10,0\(r9\)
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.* 7d 89 02 a6 mfctr r12
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.* 78 0b 1f 24 rldicr r11,r0,3,60
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.* 34 40 80 00 addic\. r2,r0,-32768
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.* 7d 8b 60 50 subf r12,r11,r12
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.* 7c 42 fe 76 sradi r2,r2,63
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.* 78 0b 17 64 rldicr r11,r0,2,61
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.* 7c 42 58 38 and r2,r2,r11
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.* 7d 8b 60 50 subf r12,r11,r12
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.* 7d 8c 12 14 add r12,r12,r2
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.* 3d 8c 00 01 addis r12,r12,1
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.* e9 6c 01 ec ld r11,492\(r12\)
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.* 39 8c 01 ec addi r12,r12,492
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.* 60 00 00 00 nop
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.* 00 00 00 00 .*
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.* 00 01 02 18 .*
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.* 7d 88 02 a6 mflr r12
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.* 42 9f 00 05 bcl- 20,4\*cr7\+so,.*
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.* 7d 68 02 a6 mflr r11
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.* e8 4b ff f0 ld r2,-16\(r11\)
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.* 7d 88 03 a6 mtlr r12
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.* 7d 82 5a 14 add r12,r2,r11
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.* e9 6c 00 00 ld r11,0\(r12\)
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.* e8 4c 00 08 ld r2,8\(r12\)
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.* 7d 69 03 a6 mtctr r11
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.* e9 6c 00 10 ld r11,16\(r12\)
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.* 4e 80 04 20 bctr
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.* 60 00 00 00 nop
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.* 60 00 00 00 nop
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.* 60 00 00 00 nop
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.* 38 00 00 00 li r0,0
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.* 4b ff ff bc b .*
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.* 4b ff ff c4 b .*
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