From ea1bd007428cb20df9a36a049d3a0ccd9ae74894 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christoph=20M=C3=BCllner?= Date: Thu, 23 Nov 2023 01:04:47 +0100 Subject: [PATCH] RISC-V: Zv*: Add support for Zvkb ISA extension MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Back then when the support for the RISC-V vector crypto extensions was merged, the specification was frozen, but not ratified. A frozen specification is allowed to change within tight bounds before ratification and this has happend with the vector crypto extensions. The following changes were applied: * A new extension Zvkb was defined, which is a strict subset of Zvbb. * Zvkn and Zvks include now Zvkb instead of Zvbb. This patch implements these changes between the frozen and the ratified specification. Note, that this technically an incompatible change of Zvkn and Zvks, but I am not aware of any project that depends on the currently implemented behaviour of Zvkn and Zvks. So this patch should be fine. Reported-By: Jerry Shih Reported-By: Eric Biggers Signed-off-by: Christoph Müllner --- bfd/elfxx-riscv.c | 10 ++++++++-- gas/testsuite/gas/riscv/zvkb.d | 28 ++++++++++++++++++++++++++++ gas/testsuite/gas/riscv/zvkb.s | 20 ++++++++++++++++++++ gas/testsuite/gas/riscv/zvkn.d | 15 --------------- gas/testsuite/gas/riscv/zvkn.s | 14 -------------- gas/testsuite/gas/riscv/zvks.d | 15 --------------- gas/testsuite/gas/riscv/zvks.s | 14 -------------- include/opcode/riscv-opc.h | 4 ++-- include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 20 ++++++++++---------- 10 files changed, 69 insertions(+), 72 deletions(-) create mode 100644 gas/testsuite/gas/riscv/zvkb.d create mode 100644 gas/testsuite/gas/riscv/zvkb.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 567631e7d96..58cc3a60c27 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1170,10 +1170,11 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"zks", "zbkx", check_implicit_always}, {"zks", "zksed", check_implicit_always}, {"zks", "zksh", check_implicit_always}, + {"zvbb", "zvkb", check_implicit_always}, {"zvkn", "zvkned", check_implicit_always}, {"zvkn", "zvknha", check_implicit_always}, {"zvkn", "zvknhb", check_implicit_always}, - {"zvkn", "zvbb", check_implicit_always}, + {"zvkn", "zvkb", check_implicit_always}, {"zvkn", "zvkt", check_implicit_always}, {"zvkng", "zvkn", check_implicit_always}, {"zvkng", "zvkg", check_implicit_always}, @@ -1181,7 +1182,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"zvknc", "zvbc", check_implicit_always}, {"zvks", "zvksed", check_implicit_always}, {"zvks", "zvksh", check_implicit_always}, - {"zvks", "zvbb", check_implicit_always}, + {"zvks", "zvkb", check_implicit_always}, {"zvks", "zvkt", check_implicit_always}, {"zvksg", "zvks", check_implicit_always}, {"zvksg", "zvkg", check_implicit_always}, @@ -1302,6 +1303,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvkg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvkn", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvkng", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2535,6 +2537,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "zvbb"); case INSN_CLASS_ZVBC: return riscv_subset_supports (rps, "zvbc"); + case INSN_CLASS_ZVKB: + return riscv_subset_supports (rps, "zvkb"); case INSN_CLASS_ZVKG: return riscv_subset_supports (rps, "zvkg"); case INSN_CLASS_ZVKNED: @@ -2787,6 +2791,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _("zvbb"); case INSN_CLASS_ZVBC: return _("zvbc"); + case INSN_CLASS_ZVKB: + return _("zvkb"); case INSN_CLASS_ZVKG: return _("zvkg"); case INSN_CLASS_ZVKNED: diff --git a/gas/testsuite/gas/riscv/zvkb.d b/gas/testsuite/gas/riscv/zvkb.d new file mode 100644 index 00000000000..181320f963b --- /dev/null +++ b/gas/testsuite/gas/riscv/zvkb.d @@ -0,0 +1,28 @@ +#as: -march=rv64gc_zvkb +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+06860257[ ]+vandn.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+04860257[ ]+vandn.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+0685c257[ ]+vandn.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+0485c257[ ]+vandn.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+4a842257[ ]+vbrev8.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+48842257[ ]+vbrev8.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+4a84a257[ ]+vrev8.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+4884a257[ ]+vrev8.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+4a84a257[ ]+vrev8.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+4884a257[ ]+vrev8.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+56860257[ ]+vrol.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+54860257[ ]+vrol.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+5685c257[ ]+vrol.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+5485c257[ ]+vrol.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+52860257[ ]+vror.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+50860257[ ]+vror.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+5285c257[ ]+vror.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+5085c257[ ]+vror.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+52803257[ ]+vror.vi[ ]+v4,v8,0 +[ ]+[0-9a-f]+:[ ]+548fb257[ ]+vror.vi[ ]+v4,v8,63,v0.t diff --git a/gas/testsuite/gas/riscv/zvkb.s b/gas/testsuite/gas/riscv/zvkb.s new file mode 100644 index 00000000000..13823dd2288 --- /dev/null +++ b/gas/testsuite/gas/riscv/zvkb.s @@ -0,0 +1,20 @@ + vandn.vv v4, v8, v12 + vandn.vv v4, v8, v12, v0.t + vandn.vx v4, v8, a1 + vandn.vx v4, v8, a1, v0.t + vbrev8.v v4, v8 + vbrev8.v v4, v8, v0.t + vrev8.v v4, v8 + vrev8.v v4, v8, v0.t + vrev8.v v4, v8 + vrev8.v v4, v8, v0.t + vrol.vv v4, v8, v12 + vrol.vv v4, v8, v12, v0.t + vrol.vx v4, v8, a1 + vrol.vx v4, v8, a1, v0.t + vror.vv v4, v8, v12 + vror.vv v4, v8, v12, v0.t + vror.vx v4, v8, a1 + vror.vx v4, v8, a1, v0.t + vror.vi v4, v8, 0 + vror.vi v4, v8, 63, v0.t diff --git a/gas/testsuite/gas/riscv/zvkn.d b/gas/testsuite/gas/riscv/zvkn.d index abb92b9f001..5766a99544a 100644 --- a/gas/testsuite/gas/riscv/zvkn.d +++ b/gas/testsuite/gas/riscv/zvkn.d @@ -12,20 +12,12 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+04860257[ ]+vandn.vv[ ]+v4,v8,v12,v0.t [ ]+[0-9a-f]+:[ ]+0685c257[ ]+vandn.vx[ ]+v4,v8,a1 [ ]+[0-9a-f]+:[ ]+0485c257[ ]+vandn.vx[ ]+v4,v8,a1,v0.t -[ ]+[0-9a-f]+:[ ]+4a852257[ ]+vbrev.v[ ]+v4,v8 -[ ]+[0-9a-f]+:[ ]+48852257[ ]+vbrev.v[ ]+v4,v8,v0.t [ ]+[0-9a-f]+:[ ]+4a842257[ ]+vbrev8.v[ ]+v4,v8 [ ]+[0-9a-f]+:[ ]+48842257[ ]+vbrev8.v[ ]+v4,v8,v0.t [ ]+[0-9a-f]+:[ ]+4a84a257[ ]+vrev8.v[ ]+v4,v8 [ ]+[0-9a-f]+:[ ]+4884a257[ ]+vrev8.v[ ]+v4,v8,v0.t [ ]+[0-9a-f]+:[ ]+4a84a257[ ]+vrev8.v[ ]+v4,v8 [ ]+[0-9a-f]+:[ ]+4884a257[ ]+vrev8.v[ ]+v4,v8,v0.t -[ ]+[0-9a-f]+:[ ]+4a862257[ ]+vclz.v[ ]+v4,v8 -[ ]+[0-9a-f]+:[ ]+48862257[ ]+vclz.v[ ]+v4,v8,v0.t -[ ]+[0-9a-f]+:[ ]+4a86a257[ ]+vctz.v[ ]+v4,v8 -[ ]+[0-9a-f]+:[ ]+4886a257[ ]+vctz.v[ ]+v4,v8,v0.t -[ ]+[0-9a-f]+:[ ]+4a872257[ ]+vcpop.v[ ]+v4,v8 -[ ]+[0-9a-f]+:[ ]+48872257[ ]+vcpop.v[ ]+v4,v8,v0.t [ ]+[0-9a-f]+:[ ]+56860257[ ]+vrol.vv[ ]+v4,v8,v12 [ ]+[0-9a-f]+:[ ]+54860257[ ]+vrol.vv[ ]+v4,v8,v12,v0.t [ ]+[0-9a-f]+:[ ]+5685c257[ ]+vrol.vx[ ]+v4,v8,a1 @@ -36,10 +28,3 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+5085c257[ ]+vror.vx[ ]+v4,v8,a1,v0.t [ ]+[0-9a-f]+:[ ]+52803257[ ]+vror.vi[ ]+v4,v8,0 [ ]+[0-9a-f]+:[ ]+548fb257[ ]+vror.vi[ ]+v4,v8,63,v0.t -[ ]+[0-9a-f]+:[ ]+d6860257[ ]+vwsll.vv[ ]+v4,v8,v12 -[ ]+[0-9a-f]+:[ ]+d4860257[ ]+vwsll.vv[ ]+v4,v8,v12,v0.t -[ ]+[0-9a-f]+:[ ]+d685c257[ ]+vwsll.vx[ ]+v4,v8,a1 -[ ]+[0-9a-f]+:[ ]+d485c257[ ]+vwsll.vx[ ]+v4,v8,a1,v0.t -[ ]+[0-9a-f]+:[ ]+d6803257[ ]+vwsll.vi[ ]+v4,v8,0 -[ ]+[0-9a-f]+:[ ]+d48fb257[ ]+vwsll.vi[ ]+v4,v8,31,v0.t - diff --git a/gas/testsuite/gas/riscv/zvkn.s b/gas/testsuite/gas/riscv/zvkn.s index 44e8f1769ce..6110903de20 100644 --- a/gas/testsuite/gas/riscv/zvkn.s +++ b/gas/testsuite/gas/riscv/zvkn.s @@ -4,20 +4,12 @@ vandn.vv v4, v8, v12, v0.t vandn.vx v4, v8, a1 vandn.vx v4, v8, a1, v0.t - vbrev.v v4, v8 - vbrev.v v4, v8, v0.t vbrev8.v v4, v8 vbrev8.v v4, v8, v0.t vrev8.v v4, v8 vrev8.v v4, v8, v0.t vrev8.v v4, v8 vrev8.v v4, v8, v0.t - vclz.v v4, v8 - vclz.v v4, v8, v0.t - vctz.v v4, v8 - vctz.v v4, v8, v0.t - vcpop.v v4, v8 - vcpop.v v4, v8, v0.t vrol.vv v4, v8, v12 vrol.vv v4, v8, v12, v0.t vrol.vx v4, v8, a1 @@ -28,9 +20,3 @@ vror.vx v4, v8, a1, v0.t vror.vi v4, v8, 0 vror.vi v4, v8, 63, v0.t - vwsll.vv v4, v8, v12 - vwsll.vv v4, v8, v12, v0.t - vwsll.vx v4, v8, a1 - vwsll.vx v4, v8, a1, v0.t - vwsll.vi v4, v8, 0 - vwsll.vi v4, v8, 31, v0.t diff --git a/gas/testsuite/gas/riscv/zvks.d b/gas/testsuite/gas/riscv/zvks.d index 2f55630f505..180ab98dd19 100644 --- a/gas/testsuite/gas/riscv/zvks.d +++ b/gas/testsuite/gas/riscv/zvks.d @@ -12,20 +12,12 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+04860257[ ]+vandn.vv[ ]+v4,v8,v12,v0.t [ ]+[0-9a-f]+:[ ]+0685c257[ ]+vandn.vx[ ]+v4,v8,a1 [ ]+[0-9a-f]+:[ ]+0485c257[ ]+vandn.vx[ ]+v4,v8,a1,v0.t -[ ]+[0-9a-f]+:[ ]+4a852257[ ]+vbrev.v[ ]+v4,v8 -[ ]+[0-9a-f]+:[ ]+48852257[ ]+vbrev.v[ ]+v4,v8,v0.t [ ]+[0-9a-f]+:[ ]+4a842257[ ]+vbrev8.v[ ]+v4,v8 [ ]+[0-9a-f]+:[ ]+48842257[ ]+vbrev8.v[ ]+v4,v8,v0.t [ ]+[0-9a-f]+:[ ]+4a84a257[ ]+vrev8.v[ ]+v4,v8 [ ]+[0-9a-f]+:[ ]+4884a257[ ]+vrev8.v[ ]+v4,v8,v0.t [ ]+[0-9a-f]+:[ ]+4a84a257[ ]+vrev8.v[ ]+v4,v8 [ ]+[0-9a-f]+:[ ]+4884a257[ ]+vrev8.v[ ]+v4,v8,v0.t -[ ]+[0-9a-f]+:[ ]+4a862257[ ]+vclz.v[ ]+v4,v8 -[ ]+[0-9a-f]+:[ ]+48862257[ ]+vclz.v[ ]+v4,v8,v0.t -[ ]+[0-9a-f]+:[ ]+4a86a257[ ]+vctz.v[ ]+v4,v8 -[ ]+[0-9a-f]+:[ ]+4886a257[ ]+vctz.v[ ]+v4,v8,v0.t -[ ]+[0-9a-f]+:[ ]+4a872257[ ]+vcpop.v[ ]+v4,v8 -[ ]+[0-9a-f]+:[ ]+48872257[ ]+vcpop.v[ ]+v4,v8,v0.t [ ]+[0-9a-f]+:[ ]+56860257[ ]+vrol.vv[ ]+v4,v8,v12 [ ]+[0-9a-f]+:[ ]+54860257[ ]+vrol.vv[ ]+v4,v8,v12,v0.t [ ]+[0-9a-f]+:[ ]+5685c257[ ]+vrol.vx[ ]+v4,v8,a1 @@ -36,10 +28,3 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+5085c257[ ]+vror.vx[ ]+v4,v8,a1,v0.t [ ]+[0-9a-f]+:[ ]+52803257[ ]+vror.vi[ ]+v4,v8,0 [ ]+[0-9a-f]+:[ ]+548fb257[ ]+vror.vi[ ]+v4,v8,63,v0.t -[ ]+[0-9a-f]+:[ ]+d6860257[ ]+vwsll.vv[ ]+v4,v8,v12 -[ ]+[0-9a-f]+:[ ]+d4860257[ ]+vwsll.vv[ ]+v4,v8,v12,v0.t -[ ]+[0-9a-f]+:[ ]+d685c257[ ]+vwsll.vx[ ]+v4,v8,a1 -[ ]+[0-9a-f]+:[ ]+d485c257[ ]+vwsll.vx[ ]+v4,v8,a1,v0.t -[ ]+[0-9a-f]+:[ ]+d6803257[ ]+vwsll.vi[ ]+v4,v8,0 -[ ]+[0-9a-f]+:[ ]+d48fb257[ ]+vwsll.vi[ ]+v4,v8,31,v0.t - diff --git a/gas/testsuite/gas/riscv/zvks.s b/gas/testsuite/gas/riscv/zvks.s index b0d3d824f3a..5e498208ba3 100644 --- a/gas/testsuite/gas/riscv/zvks.s +++ b/gas/testsuite/gas/riscv/zvks.s @@ -4,20 +4,12 @@ vandn.vv v4, v8, v12, v0.t vandn.vx v4, v8, a1 vandn.vx v4, v8, a1, v0.t - vbrev.v v4, v8 - vbrev.v v4, v8, v0.t vbrev8.v v4, v8 vbrev8.v v4, v8, v0.t vrev8.v v4, v8 vrev8.v v4, v8, v0.t vrev8.v v4, v8 vrev8.v v4, v8, v0.t - vclz.v v4, v8 - vclz.v v4, v8, v0.t - vctz.v v4, v8 - vctz.v v4, v8, v0.t - vcpop.v v4, v8 - vcpop.v v4, v8, v0.t vrol.vv v4, v8, v12 vrol.vv v4, v8, v12, v0.t vrol.vx v4, v8, a1 @@ -28,9 +20,3 @@ vror.vx v4, v8, a1, v0.t vror.vi v4, v8, 0 vror.vi v4, v8, 63, v0.t - vwsll.vv v4, v8, v12 - vwsll.vv v4, v8, v12, v0.t - vwsll.vx v4, v8, a1 - vwsll.vx v4, v8, a1, v0.t - vwsll.vi v4, v8, 0 - vwsll.vi v4, v8, 31, v0.t diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 1e417217b7d..1af8475befc 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2121,7 +2121,7 @@ #define MASK_VDOTUVV 0xfc00707f #define MATCH_VFDOTVV 0xe4001057 #define MASK_VFDOTVV 0xfc00707f -/* Zvbb instructions. */ +/* Zvbb/Zvkb instructions. */ #define MATCH_VANDN_VV 0x4000057 #define MASK_VANDN_VV 0xfc00707f #define MATCH_VANDN_VX 0x4004057 @@ -3798,7 +3798,7 @@ DECLARE_INSN(c_ntl_all, MATCH_C_NTL_ALL, MASK_C_NTL_ALL) /* Zawrs instructions. */ DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO) DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO) -/* Zvbb instructions. */ +/* Zvbb/Zvkb instructions. */ DECLARE_INSN(vandn_vv, MATCH_VANDN_VV, MASK_VANDN_VV) DECLARE_INSN(vandn_vx, MATCH_VANDN_VX, MASK_VANDN_VX) DECLARE_INSN(vbrev8_v, MATCH_VBREV8_V, MASK_VBREV8_V) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 25486869606..132d686b416 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -439,6 +439,7 @@ enum riscv_insn_class INSN_CLASS_ZVEF, INSN_CLASS_ZVBB, INSN_CLASS_ZVBC, + INSN_CLASS_ZVKB, INSN_CLASS_ZVKG, INSN_CLASS_ZVKNED, INSN_CLASS_ZVKNHA_OR_ZVKNHB, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index bf19978e025..011fd2e4f3f 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1911,20 +1911,20 @@ const struct riscv_opcode riscv_opcodes[] = {"vmv4r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV4RV, MASK_VMV4RV, match_opcode, 0}, {"vmv8r.v", 0, INSN_CLASS_V, "Vd,Vt", MATCH_VMV8RV, MASK_VMV8RV, match_opcode, 0}, -/* Zvbb instructions. */ -{"vandn.vv", 0, INSN_CLASS_ZVBB, "Vd,Vt,VsVm", MATCH_VANDN_VV, MASK_VANDN_VV, match_opcode, 0}, -{"vandn.vx", 0, INSN_CLASS_ZVBB, "Vd,Vt,sVm", MATCH_VANDN_VX, MASK_VANDN_VX, match_opcode, 0}, +/* Zvbb/Zvkb instructions. */ +{"vandn.vv", 0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VANDN_VV, MASK_VANDN_VV, match_opcode, 0}, +{"vandn.vx", 0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VANDN_VX, MASK_VANDN_VX, match_opcode, 0}, {"vbrev.v", 0, INSN_CLASS_ZVBB, "Vd,VtVm", MATCH_VBREV_V, MASK_VBREV_V, match_opcode, 0}, -{"vbrev8.v", 0, INSN_CLASS_ZVBB, "Vd,VtVm", MATCH_VBREV8_V, MASK_VBREV8_V, match_opcode, 0}, -{"vrev8.v", 0, INSN_CLASS_ZVBB, "Vd,VtVm", MATCH_VREV8_V, MASK_VREV8_V, match_opcode, 0}, +{"vbrev8.v", 0, INSN_CLASS_ZVKB, "Vd,VtVm", MATCH_VBREV8_V, MASK_VBREV8_V, match_opcode, 0}, +{"vrev8.v", 0, INSN_CLASS_ZVKB, "Vd,VtVm", MATCH_VREV8_V, MASK_VREV8_V, match_opcode, 0}, {"vclz.v", 0, INSN_CLASS_ZVBB, "Vd,VtVm", MATCH_VCLZ_V, MASK_VCLZ_V, match_opcode, 0}, {"vctz.v", 0, INSN_CLASS_ZVBB, "Vd,VtVm", MATCH_VCTZ_V, MASK_VCTZ_V, match_opcode, 0}, {"vcpop.v", 0, INSN_CLASS_ZVBB, "Vd,VtVm", MATCH_VCPOP_V, MASK_VCPOP_V, match_opcode, 0}, -{"vrol.vv", 0, INSN_CLASS_ZVBB, "Vd,Vt,VsVm", MATCH_VROL_VV, MASK_VROL_VV, match_opcode, 0}, -{"vrol.vx", 0, INSN_CLASS_ZVBB, "Vd,Vt,sVm", MATCH_VROL_VX, MASK_VROL_VX, match_opcode, 0}, -{"vror.vv", 0, INSN_CLASS_ZVBB, "Vd,Vt,VsVm", MATCH_VROR_VV, MASK_VROR_VV, match_opcode, 0}, -{"vror.vx", 0, INSN_CLASS_ZVBB, "Vd,Vt,sVm", MATCH_VROR_VX, MASK_VROR_VX, match_opcode, 0}, -{"vror.vi", 0, INSN_CLASS_ZVBB, "Vd,Vt,VlVm", MATCH_VROR_VI, MASK_VROR_VI, match_opcode, 0}, +{"vrol.vv", 0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VROL_VV, MASK_VROL_VV, match_opcode, 0}, +{"vrol.vx", 0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VROL_VX, MASK_VROL_VX, match_opcode, 0}, +{"vror.vv", 0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VROR_VV, MASK_VROR_VV, match_opcode, 0}, +{"vror.vx", 0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VROR_VX, MASK_VROR_VX, match_opcode, 0}, +{"vror.vi", 0, INSN_CLASS_ZVKB, "Vd,Vt,VlVm", MATCH_VROR_VI, MASK_VROR_VI, match_opcode, 0}, {"vwsll.vv", 0, INSN_CLASS_ZVBB, "Vd,Vt,VsVm", MATCH_VWSLL_VV, MASK_VWSLL_VV, match_opcode, 0}, {"vwsll.vx", 0, INSN_CLASS_ZVBB, "Vd,Vt,sVm", MATCH_VWSLL_VX, MASK_VWSLL_VX, match_opcode, 0}, {"vwsll.vi", 0, INSN_CLASS_ZVBB, "Vd,Vt,VjVm", MATCH_VWSLL_VI, MASK_VWSLL_VI, match_opcode, 0},