mirror of
https://sourceware.org/git/binutils-gdb.git
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include/opcode/
* mips.h: Remove "mi" documentation. Update "mh" documentation. (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI): Delete. (INSN2_WRITE_GPR_MHI): Rename to... (INSN2_WRITE_GPR_MH): ...this. opcodes/ * micromips-opc.c (WR_mhi): Rename to.. (WR_mh): ...this. (micromips_opcodes): Update "movep" entry accordingly. Replace "mh,mi" with "mh". * mips-dis.c (micromips_to_32_reg_h_map): Rename to... (micromips_to_32_reg_h_map1): ...this. (micromips_to_32_reg_i_map): Rename to... (micromips_to_32_reg_h_map2): ...this. (print_micromips_insn): Remove "mi" case. Print both registers in the pair for "mh". gas/ * config/tc-mips.c (mips32_to_micromips_reg_h_map): Delete. (micromips_to_32_reg_h_map): Rename to... (micromips_to_32_reg_h_map1): ...this. (micromips_to_32_reg_i_map): Rename to... (micromips_to_32_reg_h_map2): ...this. (mips_lookup_reg_pair): New function. (gpr_write_mask, macro): Adjust after above renaming. (validate_micromips_insn): Remove "mi" handling. (mips_ip): Likewise. Parse both registers in a pair for "mh".
This commit is contained in:
Richard Sandiford
parent
fa7616a4c7
commit
e76ff5abe3
@ -1,3 +1,15 @@
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2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
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* config/tc-mips.c (mips32_to_micromips_reg_h_map): Delete.
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(micromips_to_32_reg_h_map): Rename to...
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(micromips_to_32_reg_h_map1): ...this.
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(micromips_to_32_reg_i_map): Rename to...
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(micromips_to_32_reg_h_map2): ...this.
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(mips_lookup_reg_pair): New function.
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(gpr_write_mask, macro): Adjust after above renaming.
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(validate_micromips_insn): Remove "mi" handling.
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(mips_ip): Likewise. Parse both registers in a pair for "mh".
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2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
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* config/tc-mips.c (validate_mips_insn, validate_micromips_insn)
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@ -779,15 +779,6 @@ static const unsigned int mips16_to_32_reg_map[] =
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#define mips32_to_micromips_reg_l_map mips32_to_16_reg_map
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#define X ILLEGAL_REG
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/* reg type h: 4, 5, 6. */
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static const int mips32_to_micromips_reg_h_map[] =
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{
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X, X, X, X, 4, 5, 6, X,
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X, X, X, X, X, X, X, X,
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X, X, X, X, X, X, X, X,
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X, X, X, X, X, X, X, X
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};
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/* reg type m: 0, 17, 2, 3, 16, 18, 19, 20. */
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static const int mips32_to_micromips_reg_m_map[] =
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{
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@ -819,13 +810,11 @@ static const int mips32_to_micromips_reg_q_map[] =
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#define micromips_to_32_reg_g_map mips16_to_32_reg_map
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/* The microMIPS registers with type h. */
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static const unsigned int micromips_to_32_reg_h_map[] =
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static const unsigned int micromips_to_32_reg_h_map1[] =
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{
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5, 5, 6, 4, 4, 4, 4, 4
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};
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/* The microMIPS registers with type i. */
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static const unsigned int micromips_to_32_reg_i_map[] =
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static const unsigned int micromips_to_32_reg_h_map2[] =
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{
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6, 7, 7, 21, 22, 5, 6, 7
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};
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@ -2591,6 +2580,19 @@ reglist_lookup (char **s, unsigned int types, unsigned int *reglistp)
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return ok && reglist != 0;
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}
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static unsigned int
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mips_lookup_reg_pair (unsigned int regno1, unsigned int regno2,
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const unsigned int *map1, const unsigned int *map2,
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unsigned int count)
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{
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unsigned int i;
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for (i = 0; i < count; i++)
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if (map1[i] == regno1 && map2[i] == regno2)
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return i;
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return ILLEGAL_REG;
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}
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/* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
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and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
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@ -3503,10 +3505,10 @@ gpr_write_mask (const struct mips_cl_insn *ip)
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{
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if (pinfo2 & INSN2_WRITE_GPR_MB)
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mask |= 1 << micromips_to_32_reg_b_map[EXTRACT_OPERAND (1, MB, *ip)];
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if (pinfo2 & INSN2_WRITE_GPR_MHI)
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if (pinfo2 & INSN2_WRITE_GPR_MH)
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{
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mask |= 1 << micromips_to_32_reg_h_map[EXTRACT_OPERAND (1, MH, *ip)];
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mask |= 1 << micromips_to_32_reg_i_map[EXTRACT_OPERAND (1, MI, *ip)];
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mask |= 1 << micromips_to_32_reg_h_map1[EXTRACT_OPERAND (1, MH, *ip)];
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mask |= 1 << micromips_to_32_reg_h_map2[EXTRACT_OPERAND (1, MH, *ip)];
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}
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if (pinfo2 & INSN2_WRITE_GPR_MJ)
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mask |= 1 << EXTRACT_OPERAND (1, MJ, *ip);
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@ -9843,8 +9845,8 @@ macro (struct mips_cl_insn *ip, char *str)
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case M_MOVEP:
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gas_assert (mips_opts.micromips);
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gas_assert (mips_opts.insn32);
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dreg = micromips_to_32_reg_h_map[EXTRACT_OPERAND (1, MH, *ip)];
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breg = micromips_to_32_reg_i_map[EXTRACT_OPERAND (1, MI, *ip)];
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dreg = micromips_to_32_reg_h_map1[EXTRACT_OPERAND (1, MH, *ip)];
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breg = micromips_to_32_reg_h_map2[EXTRACT_OPERAND (1, MH, *ip)];
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sreg = micromips_to_32_reg_m_map[EXTRACT_OPERAND (1, MM, *ip)];
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treg = micromips_to_32_reg_n_map[EXTRACT_OPERAND (1, MN, *ip)];
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move_register (dreg, sreg);
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@ -11110,7 +11112,6 @@ validate_micromips_insn (const struct mips_opcode *opc)
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case 'f': USE_BITS (MF); break;
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case 'g': USE_BITS (MG); break;
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case 'h': USE_BITS (MH); break;
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case 'i': USE_BITS (MI); break;
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case 'j': USE_BITS (MJ); break;
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case 'l': USE_BITS (ML); break;
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case 'm': USE_BITS (MM); break;
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@ -11287,7 +11288,7 @@ mips_ip (char *str, struct mips_cl_insn *ip)
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char c = 0;
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struct mips_opcode *insn;
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char *argsStart;
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unsigned int regno;
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unsigned int regno, regno2;
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unsigned int lastregno;
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unsigned int destregno = 0;
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unsigned int lastpos = 0;
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@ -13141,7 +13142,6 @@ mips_ip (char *str, struct mips_cl_insn *ip)
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case 'f':
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case 'g':
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case 'h':
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case 'i':
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case 'j':
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case 'l':
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case 'm':
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@ -13264,47 +13264,32 @@ mips_ip (char *str, struct mips_cl_insn *ip)
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break;
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case 'h':
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regno = mips32_to_micromips_reg_h_map[regno];
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break;
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case 'i':
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switch (EXTRACT_OPERAND (1, MI, *ip))
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s += strspn (s, " \t");
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if (*s != ',')
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{
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case 4:
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if (regno == 21)
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regno = 3;
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else if (regno == 22)
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regno = 4;
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else if (regno == 5)
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regno = 5;
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else if (regno == 6)
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regno = 6;
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else if (regno == 7)
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regno = 7;
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else
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regno = ILLEGAL_REG;
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break;
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case 5:
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if (regno == 6)
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regno = 0;
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else if (regno == 7)
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regno = 1;
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else
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regno = ILLEGAL_REG;
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break;
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case 6:
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if (regno == 7)
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regno = 2;
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else
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regno = ILLEGAL_REG;
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break;
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default:
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regno = ILLEGAL_REG;
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break;
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regno = ILLEGAL_REG;
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break;
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}
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++s;
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s += strspn (s, " \t");
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ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, ®no2);
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if (!ok)
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{
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regno = ILLEGAL_REG;
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break;
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}
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if (regno2 == AT && mips_opts.at)
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{
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if (mips_opts.at == ATREG)
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as_warn (_("Used $at without \".set noat\""));
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else
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as_warn (_("Used $%u with \".set at=$%u\""),
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regno2, mips_opts.at);
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}
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regno = (mips_lookup_reg_pair
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(regno, regno2,
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micromips_to_32_reg_h_map1,
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micromips_to_32_reg_h_map2, 8));
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break;
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case 'l':
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@ -13381,10 +13366,6 @@ mips_ip (char *str, struct mips_cl_insn *ip)
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INSERT_OPERAND (1, MH, *ip, regno);
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break;
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case 'i':
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INSERT_OPERAND (1, MI, *ip, regno);
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break;
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case 'j':
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INSERT_OPERAND (1, MJ, *ip, regno);
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break;
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@ -1,3 +1,11 @@
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2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
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* mips.h: Remove "mi" documentation. Update "mh" documentation.
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(OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
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Delete.
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(INSN2_WRITE_GPR_MHI): Rename to...
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(INSN2_WRITE_GPR_MH): ...this.
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2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
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* mips.h: Remove documentation of "+D" and "+T".
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@ -279,8 +279,6 @@
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#define OP_SH_MG 0
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#define OP_MASK_MH 0
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#define OP_SH_MH 0
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#define OP_MASK_MI 0
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#define OP_SH_MI 0
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#define OP_MASK_MJ 0
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#define OP_SH_MJ 0
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#define OP_MASK_ML 0
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@ -685,8 +683,8 @@ struct mips_opcode
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#define INSN2_UNCOND_BRANCH 0x10000000
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/* Is a conditional branch insn. */
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#define INSN2_COND_BRANCH 0x20000000
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/* Modifies the general purpose registers in MICROMIPSOP_*_MH/I. */
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#define INSN2_WRITE_GPR_MHI 0x40000000
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/* Modifies the general purpose registers in MICROMIPSOP_*_MH. */
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#define INSN2_WRITE_GPR_MH 0x40000000
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/* Reads the general purpose registers in MICROMIPSOP_*_MM/N. */
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#define INSN2_READ_GPR_MMN 0x80000000
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@ -1555,8 +1553,6 @@ extern const int bfd_mips16_num_opcodes;
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#define MICROMIPSOP_SH_MG 0
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#define MICROMIPSOP_MASK_MH 0x7
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#define MICROMIPSOP_SH_MH 7
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#define MICROMIPSOP_MASK_MI 0x7
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#define MICROMIPSOP_SH_MI 7
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#define MICROMIPSOP_MASK_MJ 0x1f
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#define MICROMIPSOP_SH_MJ 0
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#define MICROMIPSOP_MASK_ML 0x7
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@ -1696,9 +1692,7 @@ extern const int bfd_mips16_num_opcodes;
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The same register used as both source and target.
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"mf" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MF) at bit 3
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"mg" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MG) at bit 0
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"mh" MIPS registers 4, 5, 6 (MICROMIPSOP_*_MH) at bit 7
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"mi" MIPS registers 5, 6, 7, 21, 22 (MICROMIPSOP_*_MI) at bit 7
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("mh" and "mi" form a valid 3-bit register pair)
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"mh" 3-bit MIPS register pair (MICROMIPSOP_*_MH) at bit 7
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"mj" 5-bit MIPS registers (MICROMIPSOP_*_MJ) at bit 0
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"ml" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ML) at bit 4
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"mm" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MM) at bit 1
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@ -1,3 +1,16 @@
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2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
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* micromips-opc.c (WR_mhi): Rename to..
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(WR_mh): ...this.
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(micromips_opcodes): Update "movep" entry accordingly. Replace
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"mh,mi" with "mh".
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* mips-dis.c (micromips_to_32_reg_h_map): Rename to...
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(micromips_to_32_reg_h_map1): ...this.
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(micromips_to_32_reg_i_map): Rename to...
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(micromips_to_32_reg_h_map2): ...this.
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(print_micromips_insn): Remove "mi" case. Print both registers
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in the pair for "mh".
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2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
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* mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
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@ -42,7 +42,7 @@
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#define RD_mf INSN2_MOD_GPR_MF
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#define WR_mf INSN2_MOD_GPR_MF
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#define RD_mg INSN2_READ_GPR_MG
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#define WR_mhi INSN2_WRITE_GPR_MHI
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#define WR_mh INSN2_WRITE_GPR_MH
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#define RD_mj INSN2_READ_GPR_MJ
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#define WR_mj INSN2_WRITE_GPR_MJ
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#define RD_ml RD_mc /* Reuse, since the bit position is the same. */
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@ -703,10 +703,10 @@ const struct mips_opcode micromips_opcodes[] =
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{"mov.d", "T,S", 0x5400207b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
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{"mov.s", "T,S", 0x5400007b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
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{"mov.ps", "T,S", 0x5400407b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
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{"movep", "mh,mi,mm,mn", 0x8400, 0xfc01, NODS, WR_mhi|RD_mmn, I1 },
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{"movep", "mh,mm,mn", 0x8400, 0xfc01, NODS, WR_mh|RD_mmn, I1 },
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/* This macro is after the real instruction so that it only matches with
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-minsn32. */
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{"movep", "mh,mi,mm,mn", 0, (int) M_MOVEP, INSN_MACRO, 0, I1 },
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{"movep", "mh,mm,mn", 0, (int) M_MOVEP, INSN_MACRO, 0, I1 },
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{"movf", "t,s,M", 0x5400017b, 0xfc001fff, WR_t|RD_s|RD_CC|FP_S|FP_D, 0, I1 },
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{"movf.d", "T,S,M", 0x54000220, 0xfc001fff, WR_T|RD_S|RD_CC|FP_D, 0, I1 },
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{"movf.s", "T,S,M", 0x54000020, 0xfc001fff, WR_T|RD_S|RD_CC|FP_S, 0, I1 },
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@ -76,13 +76,11 @@ static const unsigned int mips16_to_32_reg_map[] =
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#define micromips_to_32_reg_g_map mips16_to_32_reg_map
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/* The microMIPS registers with type h. */
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static const unsigned int micromips_to_32_reg_h_map[] =
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static const unsigned int micromips_to_32_reg_h_map1[] =
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{
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5, 5, 6, 4, 4, 4, 4, 4
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};
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/* The microMIPS registers with type i. */
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static const unsigned int micromips_to_32_reg_i_map[] =
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static const unsigned int micromips_to_32_reg_h_map2[] =
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{
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6, 7, 7, 21, 22, 5, 6, 7
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};
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@ -2716,13 +2714,10 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
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break;
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case 'h':
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regno = micromips_to_32_reg_h_map[GET_OP (insn, MH)];
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infprintf (is, "%s", mips_gpr_names[regno]);
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break;
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case 'i':
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regno = micromips_to_32_reg_i_map[GET_OP (insn, MI)];
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regno = micromips_to_32_reg_h_map1[GET_OP (insn, MH)];
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infprintf (is, "%s", mips_gpr_names[regno]);
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regno = micromips_to_32_reg_h_map2[GET_OP (insn, MH)];
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infprintf (is, ",%s", mips_gpr_names[regno]);
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break;
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case 'j':
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