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MIPS/BFD: Correct register index calculation in BZ16_REG

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For the 3-bit register encodings of { 0, 1, 2, 3, 4, 5, 6, 7 } return
the 5-bit encodings of { 16, 17, 2, 3, 4, 5, 6, 7 } respectively rather
than { 24, 25, 2, 3, 4, 5, 6, 7 }.

	bfd/
	* elfxx-mips.c (BZ16_REG): Correct calculation.
This commit is contained in:
Maciej W. Rozycki 2016-01-24 00:49:26 +00:00
parent 38ab17f658
commit e67f83e590
2 changed files with 5 additions and 1 deletions
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4
bfd/ChangeLog
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@ -1,3 +1,7 @@
2016-01-24 Maciej W. Rozycki <macro@imgtec.com>
* elfxx-mips.c (BZ16_REG): Correct calculation.
2016-01-21 Nick Clifton <nickc@redhat.com>
* elf32-arc.c (ADD_RELA): Fix compile time warning errors by

2
bfd/elfxx-mips.c
View File

@ -13110,7 +13110,7 @@ static const struct opcode_descriptor bz_insns_16[] = {
/* Switch between a 5-bit register index and its 3-bit shorthand. */
#define BZ16_REG(opcode) ((((((opcode) >> 7) & 7) + 0x1e) & 0x17) + 2)
#define BZ16_REG(opcode) ((((((opcode) >> 7) & 7) + 0x1e) & 0xf) + 2)
#define BZ16_REG_FIELD(r) \
(((2 <= (r) && (r) <= 7) ? (r) : ((r) - 16)) << 7)