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* arm-dis.c (print_insn): Fixed search for next

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symbol and data dumping condition, and the
    initial mapping symbol state.

    * gas/arm/dis-data.d: New test case.
    * gas/arm/dis-data.s: New file.
This commit is contained in:
Nick Clifton 2010-01-06 15:02:45 +00:00
parent 15d123c99f
commit e3e535bc58
8 changed files with 72 additions and 21 deletions
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27
gas/config/tc-arm.c
View File

@ -13666,12 +13666,22 @@ do_vfp_nsyn_cvtz (void)
}
static void
do_neon_cvt (void)
do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED)
{
enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL);
int flavour = neon_cvt_flavour (rs);
/* PR11109: Handle round-to-zero for VCVT conversions. */
if (round_to_zero
&& ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
&& (flavour == 0 || flavour == 1 || flavour == 8 || flavour == 9)
&& (rs == NS_FD || rs == NS_FF))
{
do_vfp_nsyn_cvtz ();
return;
}
/* VFP rather than Neon conversions. */
if (flavour >= 6)
{
@ -13771,6 +13781,18 @@ do_neon_cvt (void)
}
}
static void
do_neon_cvtr (void)
{
do_neon_cvt_1 (FALSE);
}
static void
do_neon_cvt (void)
{
do_neon_cvt_1 (TRUE);
}
static void
do_neon_cvtb (void)
{
@ -17416,7 +17438,8 @@ static const struct asm_opcode insns[] =
NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32b), neon_cvt),
nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32b), neon_cvt),
nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
nCEF(vcvtb, _vcvt, 2, (RVS, RVS), neon_cvtb),
nCEF(vcvtt, _vcvt, 2, (RVS, RVS), neon_cvtt),

5
gas/testsuite/ChangeLog
View File

@ -1,3 +1,8 @@
2010-01-06 Daniel Gutson <dgutson@codesourcery.com>
* gas/arm/dis-data.d: New test case.
* gas/arm/dis-data.s: New file.
2010-01-04 Daniel Gutson <dgutson@codesourcery.com>
* gas/arm/neon-logic.d: New test case.

10
gas/testsuite/gas/arm/dis-data.d Normal file
View File

@ -0,0 +1,10 @@
# name: Data disassembler test
# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
# objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format .*arm.*
Disassembly of section \.text:
0x00000000 20010000 .word 0x20010000
0x00000004 000000f9 .word 0x000000f9
0x00000008 00004cd5 .word 0x00004cd5

5
gas/testsuite/gas/arm/dis-data.s Normal file
View File

@ -0,0 +1,5 @@
.syntax unified
.word 0x20010000
.word 0x000000f9
.word 0x00004cd5

16
gas/testsuite/gas/arm/vfp-neon-syntax.d
View File

@ -93,24 +93,24 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> 0ebc0ae0 (vcvteq\.u32\.f32|ftouizseq) s0, s1
0[0-9a-f]+ <[^>]+> 0ebd0bc1 (vcvteq\.s32\.f64|ftosizdeq) s0, d1
0[0-9a-f]+ <[^>]+> 0ebc0bc1 (vcvteq\.u32\.f64|ftouizdeq) s0, d1
0[0-9a-f]+ <[^>]+> eebd0a60 (vcvtr\.s32\.f32|ftosis) s0, s1
0[0-9a-f]+ <[^>]+> eebc0a60 (vcvtr\.u32\.f32|ftouis) s0, s1
0[0-9a-f]+ <[^>]+> eebd0ae0 (vcvt\.s32\.f32|ftosis) s0, s1
0[0-9a-f]+ <[^>]+> eebc0ae0 (vcvt\.u32\.f32|ftouis) s0, s1
0[0-9a-f]+ <[^>]+> eeb80ae0 (vcvt\.f32\.s32|fsitos) s0, s1
0[0-9a-f]+ <[^>]+> eeb80a60 (vcvt\.f32\.u32|fuitos) s0, s1
0[0-9a-f]+ <[^>]+> eeb70bc1 (vcvt\.f32\.f64|fcvtsd) s0, d1
0[0-9a-f]+ <[^>]+> eeb70ae0 (vcvt\.f64\.f32|fcvtds) d0, s1
0[0-9a-f]+ <[^>]+> eebd0b41 (vcvtr\.s32\.f64|ftosid) s0, d1
0[0-9a-f]+ <[^>]+> eebc0b41 (vcvtr\.u32\.f64|ftouid) s0, d1
0[0-9a-f]+ <[^>]+> eebd0bc1 (vcvt\.s32\.f64|ftosid) s0, d1
0[0-9a-f]+ <[^>]+> eebc0bc1 (vcvt\.u32\.f64|ftouid) s0, d1
0[0-9a-f]+ <[^>]+> eeb80be0 (vcvt\.f64\.s32|fsitod) d0, s1
0[0-9a-f]+ <[^>]+> eeb80b60 (vcvt\.f64\.u32|fuitod) d0, s1
0[0-9a-f]+ <[^>]+> 0ebd0a60 (vcvtreq\.s32\.f32|ftosiseq) s0, s1
0[0-9a-f]+ <[^>]+> 0ebc0a60 (vcvtreq\.u32\.f32|ftouiseq) s0, s1
0[0-9a-f]+ <[^>]+> 0ebd0ae0 (vcvteq\.s32\.f32|ftosiseq) s0, s1
0[0-9a-f]+ <[^>]+> 0ebc0ae0 (vcvteq\.u32\.f32|ftouiseq) s0, s1
0[0-9a-f]+ <[^>]+> 0eb80ae0 (vcvteq\.f32\.s32|fsitoseq) s0, s1
0[0-9a-f]+ <[^>]+> 0eb80a60 (vcvteq\.f32\.u32|fuitoseq) s0, s1
0[0-9a-f]+ <[^>]+> 0eb70bc1 (vcvteq\.f32\.f64|fcvtsdeq) s0, d1
0[0-9a-f]+ <[^>]+> 0eb70ae0 (vcvteq\.f64\.f32|fcvtdseq) d0, s1
0[0-9a-f]+ <[^>]+> 0ebd0b41 (vcvtreq\.s32\.f64|ftosideq) s0, d1
0[0-9a-f]+ <[^>]+> 0ebc0b41 (vcvtreq\.u32\.f64|ftouideq) s0, d1
0[0-9a-f]+ <[^>]+> 0ebd0bc1 (vcvteq\.s32\.f64|ftosideq) s0, d1
0[0-9a-f]+ <[^>]+> 0ebc0bc1 (vcvteq\.u32\.f64|ftouideq) s0, d1
0[0-9a-f]+ <[^>]+> 0eb80be0 (vcvteq\.f64\.s32|fsitodeq) d0, s1
0[0-9a-f]+ <[^>]+> 0eb80b60 (vcvteq\.f64\.u32|fuitodeq) d0, s1
0[0-9a-f]+ <[^>]+> eebe0aef (vcvt\.s32\.f32 s0, s0, #1|ftosls s0, #1)

16
gas/testsuite/gas/arm/vfp-neon-syntax_t2.d
View File

@ -112,26 +112,26 @@ Disassembly of section \.text:
0[0-9a-f]+ <[^>]+> eebc 0ae0 (vcvteq\.u32\.f32|ftouizseq) s0, s1
0[0-9a-f]+ <[^>]+> eebd 0bc1 (vcvteq\.s32\.f64|ftosizdeq) s0, d1
0[0-9a-f]+ <[^>]+> eebc 0bc1 (vcvteq\.u32\.f64|ftouizdeq) s0, d1
0[0-9a-f]+ <[^>]+> eebd 0a60 (vcvtr\.s32\.f32|ftosis) s0, s1
0[0-9a-f]+ <[^>]+> eebc 0a60 (vcvtr\.u32\.f32|ftouis) s0, s1
0[0-9a-f]+ <[^>]+> eebd 0ae0 (vcvt\.s32\.f32|ftosis) s0, s1
0[0-9a-f]+ <[^>]+> eebc 0ae0 (vcvt\.u32\.f32|ftouis) s0, s1
0[0-9a-f]+ <[^>]+> eeb8 0ae0 (vcvt\.f32\.s32|fsitos) s0, s1
0[0-9a-f]+ <[^>]+> eeb8 0a60 (vcvt\.f32\.u32|fuitos) s0, s1
0[0-9a-f]+ <[^>]+> eeb7 0bc1 (vcvt\.f32\.f64|fcvtsd) s0, d1
0[0-9a-f]+ <[^>]+> eeb7 0ae0 (vcvt\.f64\.f32|fcvtds) d0, s1
0[0-9a-f]+ <[^>]+> eebd 0b41 (vcvtr\.s32\.f64|ftosid) s0, d1
0[0-9a-f]+ <[^>]+> eebc 0b41 (vcvtr\.u32\.f64|ftouid) s0, d1
0[0-9a-f]+ <[^>]+> eebd 0bc1 (vcvt\.s32\.f64|ftosid) s0, d1
0[0-9a-f]+ <[^>]+> eebc 0bc1 (vcvt\.u32\.f64|ftouid) s0, d1
0[0-9a-f]+ <[^>]+> eeb8 0be0 (vcvt\.f64\.s32|fsitod) d0, s1
0[0-9a-f]+ <[^>]+> eeb8 0b60 (vcvt\.f64\.u32|fuitod) d0, s1
0[0-9a-f]+ <[^>]+> bf01 itttt eq
0[0-9a-f]+ <[^>]+> eebd 0a60 (vcvtreq\.s32\.f32|ftosiseq) s0, s1
0[0-9a-f]+ <[^>]+> eebc 0a60 (vcvtreq\.u32\.f32|ftouiseq) s0, s1
0[0-9a-f]+ <[^>]+> eebd 0ae0 (vcvteq\.s32\.f32|ftosiseq) s0, s1
0[0-9a-f]+ <[^>]+> eebc 0ae0 (vcvteq\.u32\.f32|ftouiseq) s0, s1
0[0-9a-f]+ <[^>]+> eeb8 0ae0 (vcvteq\.f32\.s32|fsitoseq) s0, s1
0[0-9a-f]+ <[^>]+> eeb8 0a60 (vcvteq\.f32\.u32|fuitoseq) s0, s1
0[0-9a-f]+ <[^>]+> bf01 itttt eq
0[0-9a-f]+ <[^>]+> eeb7 0bc1 (vcvteq\.f32\.f64|fcvtsdeq) s0, d1
0[0-9a-f]+ <[^>]+> eeb7 0ae0 (vcvteq\.f64\.f32|fcvtdseq) d0, s1
0[0-9a-f]+ <[^>]+> eebd 0b41 (vcvtreq\.s32\.f64|ftosideq) s0, d1
0[0-9a-f]+ <[^>]+> eebc 0b41 (vcvtreq\.u32\.f64|ftouideq) s0, d1
0[0-9a-f]+ <[^>]+> eebd 0bc1 (vcvteq\.s32\.f64|ftosideq) s0, d1
0[0-9a-f]+ <[^>]+> eebc 0bc1 (vcvteq\.u32\.f64|ftouideq) s0, d1
0[0-9a-f]+ <[^>]+> bf04 itt eq
0[0-9a-f]+ <[^>]+> eeb8 0be0 (vcvteq\.f64\.s32|fsitodeq) d0, s1
0[0-9a-f]+ <[^>]+> eeb8 0b60 (vcvteq\.f64\.u32|fuitodeq) d0, s1

5
opcodes/ChangeLog
View File

@ -1,3 +1,8 @@
2010-01-06 Daniel Gutson <dgutson@codesourcery.com>
* arm-dis.c (print_insn): Fixed search for next symbol and data
dumping condition, and the initial mapping symbol state.
2010-01-05 Doug Evans <dje@sebabeach.org>
* cgen-ibld.in: #include "cgen/basic-modes.h".

9
opcodes/arm-dis.c
View File

@ -4355,7 +4355,8 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
long given;
int status;
int is_thumb = FALSE;
int is_data = FALSE;
int is_data = (bfd_asymbol_flavour (*info->symtab)
== bfd_target_elf_flavour) ? TRUE : FALSE;
int little_code;
unsigned int size = 4;
void (*printer) (bfd_vma, struct disassemble_info *, long);
@ -4415,7 +4416,7 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
bfd_vma addr;
int n;
int last_sym = -1;
enum map_type type = MAP_ARM;
enum map_type type = MAP_DATA;
if (pc <= last_mapping_addr)
last_mapping_sym = -1;
@ -4478,7 +4479,9 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
for (n = last_sym + 1; n < info->symtab_size; n++)
{
addr = bfd_asymbol_value (info->symtab[n]);
if (addr > pc)
if (addr > pc
&& (info->section == NULL
|| info->section == info->symtab[n]->section))
{
if (addr - pc < size)
size = addr - pc;