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aarch64: Add id_aa64isar2_el1

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Armv8.8-A defines a read-only system register called id_aa64isar2_el1.
The register was previously RES0 and should therefore be accepted
at all architecture levels.
[https://developer.arm.com/documentation/ddi0595/2021-09/AArch64-Registers/ID-AA64ISAR2-EL1--AArch64-Instruction-Set-Attribute-Register-2?lang=en]

opcodes/
	* aarch64-opc.c (aarch64_sys_regs): Add id_aa64isar2_el1.

gas/
	* testsuite/gas/aarch64/sysreg-diagnostic.s: Test writes to
	id_aa64isar2_el1.
	* testsuite/gas/aarch64/sysreg-diagnostic.d: Update accordingly.
	* testsuite/gas/aarch64/sysreg-diagnostic.l: Likewise.
	* testsuite/gas/aarch64/sysreg.s: Test reads from
	id_aa64isar2_el1.
	* testsuite/gas/aarch64/sysreg.d: Update accordingly.
This commit is contained in:
Richard Sandiford 2021-12-02 15:00:56 +00:00
parent 175eafaf37
commit e14c9cb6c8
6 changed files with 9 additions and 0 deletions
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1
gas/testsuite/gas/aarch64/sysreg-diagnostic.d
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@ -12,3 +12,4 @@ Disassembly of section \.text:
.*: d5330503 mrs x3, dbgdtrrx_el0
.*: d5330503 mrs x3, dbgdtrrx_el0
.*: d5180003 msr midr_el1, x3 // note: writing to a read-only register
.*: d5180640 msr id_aa64isar2_el1, x0 // note: writing to a read-only register

1
gas/testsuite/gas/aarch64/sysreg-diagnostic.l
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@ -2,3 +2,4 @@
.*:3: Warning: specified register cannot be written to at operand 1 -- `msr dbgdtrrx_el0,x3'
.*:5: Warning: specified register cannot be read from at operand 2 -- `mrs x3,dbgdtrtx_el0'
.*:6: Warning: specified register cannot be written to at operand 1 -- `msr midr_el1,x3'
.*:7: Warning: specified register cannot be written to at operand 1 -- `msr id_aa64isar2_el1,x0'

1
gas/testsuite/gas/aarch64/sysreg-diagnostic.s
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@ -4,3 +4,4 @@
mrs x3, dbgdtrrx_el0
mrs x3, dbgdtrtx_el0
msr midr_el1, x3
msr id_aa64isar2_el1, x0

2
gas/testsuite/gas/aarch64/sysreg.d
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@ -29,3 +29,5 @@ Disassembly of section \.text:
54: d5184b00 msr s3_0_c4_c11_0, x0
58: d5310300 mrs x0, trcstatr
5c: d5110300 msr trcstatr, x0
60: d5380640 mrs x0, id_aa64isar2_el1
64: d538065e mrs x30, id_aa64isar2_el1

3
gas/testsuite/gas/aarch64/sysreg.s
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@ -30,3 +30,6 @@
mrs x0, s2_1_c0_c3_0
msr s2_1_c0_c3_0, x0
mrs x0, id_aa64isar2_el1
mrs x30, id_aa64isar2_el1

1
opcodes/aarch64-opc.c
View File

@ -4082,6 +4082,7 @@ const aarch64_sys_reg aarch64_sys_regs [] =
SR_CORE ("id_aa64dfr1_el1", CPENC (3,0,C0,C5,1), F_REG_READ),
SR_CORE ("id_aa64isar0_el1", CPENC (3,0,C0,C6,0), F_REG_READ),
SR_CORE ("id_aa64isar1_el1", CPENC (3,0,C0,C6,1), F_REG_READ),
SR_CORE ("id_aa64isar2_el1", CPENC (3,0,C0,C6,2), F_REG_READ),
SR_CORE ("id_aa64mmfr0_el1", CPENC (3,0,C0,C7,0), F_REG_READ),
SR_CORE ("id_aa64mmfr1_el1", CPENC (3,0,C0,C7,1), F_REG_READ),
SR_CORE ("id_aa64mmfr2_el1", CPENC (3,0,C0,C7,2), F_REG_READ),