mirror of
https://sourceware.org/git/binutils-gdb.git
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Add MIPS Allegrex CPU as a MIPS2-based CPU
The Allegrex CPU was created by Sony Interactive Entertainment to power their portable console, the PlayStation Portable. The pspdev organization maintains all sorts of tools to create software for said device including documentation. Signed-off-by: David Guillen Fandos <david@davidgf.net>
This commit is contained in:
David Guillen Fandos
Maciej W. Rozycki
parent
011365baca
commit
df18f71b56
@ -173,6 +173,7 @@ DESCRIPTION
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.#define bfd_mach_mips16000 16000
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.#define bfd_mach_mips16 16
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.#define bfd_mach_mips5 5
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.#define bfd_mach_mips_allegrex 10111431 {* octal 'AL', 31. *}
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.#define bfd_mach_mips_loongson_2e 3001
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.#define bfd_mach_mips_loongson_2f 3002
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.#define bfd_mach_mips_gs464 3003
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@ -1426,6 +1426,7 @@ enum bfd_architecture
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#define bfd_mach_mips16000 16000
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#define bfd_mach_mips16 16
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#define bfd_mach_mips5 5
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#define bfd_mach_mips_allegrex 10111431 /* octal 'AL', 31. */
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#define bfd_mach_mips_loongson_2e 3001
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#define bfd_mach_mips_loongson_2f 3002
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#define bfd_mach_mips_gs464 3003
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@ -108,6 +108,7 @@ enum
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I_mipsocteon3,
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I_xlr,
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I_interaptiv_mr2,
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I_allegrex,
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I_micromips
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};
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@ -163,6 +164,7 @@ static const bfd_arch_info_type arch_info_struct[] =
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N (64, 64, bfd_mach_mips_xlr, "mips:xlr", false, NN(I_xlr)),
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N (32, 32, bfd_mach_mips_interaptiv_mr2, "mips:interaptiv-mr2", false,
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NN(I_interaptiv_mr2)),
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N (32, 32, bfd_mach_mips_allegrex, "mips:allegrex", false, NN(I_allegrex)),
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N (64, 64, bfd_mach_mips_micromips, "mips:micromips", false, NULL)
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};
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@ -6996,6 +6996,9 @@ _bfd_elf_mips_mach (flagword flags)
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case E_MIPS_MACH_4010:
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return bfd_mach_mips4010;
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case E_MIPS_MACH_ALLEGREX:
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return bfd_mach_mips_allegrex;
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case E_MIPS_MACH_4100:
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return bfd_mach_mips4100;
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@ -12331,6 +12334,10 @@ mips_set_isa_flags (bfd *abfd)
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val = E_MIPS_ARCH_2 | E_MIPS_MACH_4010;
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break;
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case bfd_mach_mips_allegrex:
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val = E_MIPS_ARCH_2 | E_MIPS_MACH_ALLEGREX;
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break;
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case bfd_mach_mips4000:
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case bfd_mach_mips4300:
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case bfd_mach_mips4400:
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@ -14588,6 +14595,7 @@ static const struct mips_mach_extension mips_mach_extensions[] =
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{ bfd_mach_mips4000, bfd_mach_mips6000 },
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{ bfd_mach_mipsisa32, bfd_mach_mips6000 },
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{ bfd_mach_mips4010, bfd_mach_mips6000 },
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{ bfd_mach_mips_allegrex, bfd_mach_mips6000 },
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/* MIPS I extensions. */
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{ bfd_mach_mips6000, bfd_mach_mips3000 },
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@ -4044,6 +4044,7 @@ get_machine_flags (Filedata * filedata, unsigned e_flags, unsigned e_machine)
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case E_MIPS_MACH_OCTEON3: strcat (buf, ", octeon3"); break;
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case E_MIPS_MACH_XLR: strcat (buf, ", xlr"); break;
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case E_MIPS_MACH_IAMR2: strcat (buf, ", interaptiv-mr2"); break;
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case E_MIPS_MACH_ALLEGREX: strcat(buf, ", allegrex"); break;
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case 0:
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/* We simply ignore the field in this case to avoid confusion:
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MIPS ELF does not specify EF_MIPS_MACH, it is a GNU
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@ -437,6 +437,7 @@ static int mips_32bitmode = 0;
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|| (ISA) == ISA_MIPS64R3 \
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|| (ISA) == ISA_MIPS64R5 \
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|| (ISA) == ISA_MIPS64R6 \
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|| (CPU) == CPU_ALLEGREX \
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|| (CPU) == CPU_R5900) \
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&& ((CPU) != CPU_GS464 \
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|| (CPU) != CPU_GS464E \
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@ -535,8 +536,9 @@ static int mips_32bitmode = 0;
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#define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
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/* True, if CPU has support for ldc1 and sdc1. */
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#define CPU_HAS_LDC1_SDC1(CPU) \
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((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
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#define CPU_HAS_LDC1_SDC1(CPU) (mips_opts.isa != ISA_MIPS1 \
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&& (CPU) != CPU_ALLEGREX \
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&& (CPU) != CPU_R5900)
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/* True if mflo and mfhi can be immediately followed by instructions
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which write to the HI and LO registers.
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@ -561,6 +563,7 @@ static int mips_32bitmode = 0;
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|| mips_opts.isa == ISA_MIPS64R3 \
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|| mips_opts.isa == ISA_MIPS64R5 \
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|| mips_opts.isa == ISA_MIPS64R6 \
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|| mips_opts.arch == CPU_ALLEGREX \
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|| mips_opts.arch == CPU_R4010 \
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|| mips_opts.arch == CPU_R5900 \
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|| mips_opts.arch == CPU_R10000 \
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@ -20008,6 +20011,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
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/* MIPS II */
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{ "r6000", 0, 0, ISA_MIPS2, CPU_R6000 },
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{ "allegrex", 0, 0, ISA_MIPS2, CPU_ALLEGREX },
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/* MIPS III */
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{ "r4000", 0, 0, ISA_MIPS3, CPU_R4000 },
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265
gas/testsuite/gas/mips/allegrex@c0.d
Normal file
265
gas/testsuite/gas/mips/allegrex@c0.d
Normal file
@ -0,0 +1,265 @@
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#objdump: -d --prefix-addresses --show-raw-insn
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#name: MIPS C0/COP0 instructions
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#as: -32
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#source: c0.s
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.*: +file format .*mips.*
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Disassembly of section \.text:
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[0-9a-f]+ <[^>]*> 42000000 c0 0x0
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[0-9a-f]+ <[^>]*> 42000001 tlbr
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[0-9a-f]+ <[^>]*> 42000002 tlbwi
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[0-9a-f]+ <[^>]*> 42000003 c0 0x3
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[0-9a-f]+ <[^>]*> 42000004 c0 0x4
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[0-9a-f]+ <[^>]*> 42000005 c0 0x5
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[0-9a-f]+ <[^>]*> 42000006 tlbwr
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[0-9a-f]+ <[^>]*> 42000007 c0 0x7
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[0-9a-f]+ <[^>]*> 42000008 tlbp
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[0-9a-f]+ <[^>]*> 42000009 c0 0x9
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[0-9a-f]+ <[^>]*> 4200000a c0 0xa
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[0-9a-f]+ <[^>]*> 4200000b c0 0xb
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[0-9a-f]+ <[^>]*> 4200000c c0 0xc
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[0-9a-f]+ <[^>]*> 4200000d c0 0xd
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[0-9a-f]+ <[^>]*> 4200000e c0 0xe
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[0-9a-f]+ <[^>]*> 4200000f c0 0xf
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[0-9a-f]+ <[^>]*> 42000010 c0 0x10
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[0-9a-f]+ <[^>]*> 42000011 c0 0x11
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[0-9a-f]+ <[^>]*> 42000012 c0 0x12
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[0-9a-f]+ <[^>]*> 42000013 c0 0x13
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[0-9a-f]+ <[^>]*> 42000014 c0 0x14
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[0-9a-f]+ <[^>]*> 42000015 c0 0x15
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[0-9a-f]+ <[^>]*> 42000016 c0 0x16
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[0-9a-f]+ <[^>]*> 42000017 c0 0x17
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[0-9a-f]+ <[^>]*> 42000018 eret
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[0-9a-f]+ <[^>]*> 42000019 c0 0x19
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[0-9a-f]+ <[^>]*> 4200001a c0 0x1a
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[0-9a-f]+ <[^>]*> 4200001b c0 0x1b
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[0-9a-f]+ <[^>]*> 4200001c c0 0x1c
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[0-9a-f]+ <[^>]*> 4200001d c0 0x1d
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[0-9a-f]+ <[^>]*> 4200001e c0 0x1e
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[0-9a-f]+ <[^>]*> 4200001f c0 0x1f
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[0-9a-f]+ <[^>]*> 42000020 c0 0x20
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[0-9a-f]+ <[^>]*> 42000021 c0 0x21
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[0-9a-f]+ <[^>]*> 42000022 c0 0x22
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[0-9a-f]+ <[^>]*> 42000023 c0 0x23
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[0-9a-f]+ <[^>]*> 42000024 c0 0x24
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[0-9a-f]+ <[^>]*> 42000025 c0 0x25
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[0-9a-f]+ <[^>]*> 42000026 c0 0x26
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[0-9a-f]+ <[^>]*> 42000027 c0 0x27
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[0-9a-f]+ <[^>]*> 42000028 c0 0x28
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[0-9a-f]+ <[^>]*> 42000029 c0 0x29
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[0-9a-f]+ <[^>]*> 4200002a c0 0x2a
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[0-9a-f]+ <[^>]*> 4200002b c0 0x2b
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[0-9a-f]+ <[^>]*> 4200002c c0 0x2c
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[0-9a-f]+ <[^>]*> 4200002d c0 0x2d
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[0-9a-f]+ <[^>]*> 4200002e c0 0x2e
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[0-9a-f]+ <[^>]*> 4200002f c0 0x2f
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[0-9a-f]+ <[^>]*> 42000030 c0 0x30
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[0-9a-f]+ <[^>]*> 42000031 c0 0x31
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[0-9a-f]+ <[^>]*> 42000032 c0 0x32
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[0-9a-f]+ <[^>]*> 42000033 c0 0x33
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[0-9a-f]+ <[^>]*> 42000034 c0 0x34
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[0-9a-f]+ <[^>]*> 42000035 c0 0x35
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[0-9a-f]+ <[^>]*> 42000036 c0 0x36
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[0-9a-f]+ <[^>]*> 42000037 c0 0x37
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[0-9a-f]+ <[^>]*> 42000038 c0 0x38
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[0-9a-f]+ <[^>]*> 42000039 c0 0x39
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[0-9a-f]+ <[^>]*> 4200003a c0 0x3a
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[0-9a-f]+ <[^>]*> 4200003b c0 0x3b
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[0-9a-f]+ <[^>]*> 4200003c c0 0x3c
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[0-9a-f]+ <[^>]*> 4200003d c0 0x3d
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[0-9a-f]+ <[^>]*> 4200003e c0 0x3e
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[0-9a-f]+ <[^>]*> 4200003f c0 0x3f
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[0-9a-f]+ <[^>]*> 43000000 c0 0x1000000
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[0-9a-f]+ <[^>]*> 43000001 c0 0x1000001
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[0-9a-f]+ <[^>]*> 43000002 c0 0x1000002
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[0-9a-f]+ <[^>]*> 43000003 c0 0x1000003
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[0-9a-f]+ <[^>]*> 43000004 c0 0x1000004
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[0-9a-f]+ <[^>]*> 43000005 c0 0x1000005
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[0-9a-f]+ <[^>]*> 43000006 c0 0x1000006
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[0-9a-f]+ <[^>]*> 43000007 c0 0x1000007
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[0-9a-f]+ <[^>]*> 43000008 c0 0x1000008
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[0-9a-f]+ <[^>]*> 43000009 c0 0x1000009
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[0-9a-f]+ <[^>]*> 4300000a c0 0x100000a
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[0-9a-f]+ <[^>]*> 4300000b c0 0x100000b
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[0-9a-f]+ <[^>]*> 4300000c c0 0x100000c
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[0-9a-f]+ <[^>]*> 4300000d c0 0x100000d
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[0-9a-f]+ <[^>]*> 4300000e c0 0x100000e
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[0-9a-f]+ <[^>]*> 4300000f c0 0x100000f
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[0-9a-f]+ <[^>]*> 43000010 c0 0x1000010
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[0-9a-f]+ <[^>]*> 43000011 c0 0x1000011
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[0-9a-f]+ <[^>]*> 43000012 c0 0x1000012
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[0-9a-f]+ <[^>]*> 43000013 c0 0x1000013
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[0-9a-f]+ <[^>]*> 43000014 c0 0x1000014
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[0-9a-f]+ <[^>]*> 43000015 c0 0x1000015
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[0-9a-f]+ <[^>]*> 43000016 c0 0x1000016
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[0-9a-f]+ <[^>]*> 43000017 c0 0x1000017
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[0-9a-f]+ <[^>]*> 43000018 c0 0x1000018
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[0-9a-f]+ <[^>]*> 43000019 c0 0x1000019
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[0-9a-f]+ <[^>]*> 4300001a c0 0x100001a
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[0-9a-f]+ <[^>]*> 4300001b c0 0x100001b
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[0-9a-f]+ <[^>]*> 4300001c c0 0x100001c
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[0-9a-f]+ <[^>]*> 4300001d c0 0x100001d
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[0-9a-f]+ <[^>]*> 4300001e c0 0x100001e
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[0-9a-f]+ <[^>]*> 4300001f c0 0x100001f
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[0-9a-f]+ <[^>]*> 43000020 c0 0x1000020
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[0-9a-f]+ <[^>]*> 43000021 c0 0x1000021
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[0-9a-f]+ <[^>]*> 43000022 c0 0x1000022
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[0-9a-f]+ <[^>]*> 43000023 c0 0x1000023
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[0-9a-f]+ <[^>]*> 43000024 c0 0x1000024
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[0-9a-f]+ <[^>]*> 43000025 c0 0x1000025
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[0-9a-f]+ <[^>]*> 43000026 c0 0x1000026
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[0-9a-f]+ <[^>]*> 43000027 c0 0x1000027
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[0-9a-f]+ <[^>]*> 43000028 c0 0x1000028
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[0-9a-f]+ <[^>]*> 43000029 c0 0x1000029
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[0-9a-f]+ <[^>]*> 4300002a c0 0x100002a
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[0-9a-f]+ <[^>]*> 4300002b c0 0x100002b
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[0-9a-f]+ <[^>]*> 4300002c c0 0x100002c
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[0-9a-f]+ <[^>]*> 4300002d c0 0x100002d
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||||
[0-9a-f]+ <[^>]*> 4300002e c0 0x100002e
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||||
[0-9a-f]+ <[^>]*> 4300002f c0 0x100002f
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||||
[0-9a-f]+ <[^>]*> 43000030 c0 0x1000030
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||||
[0-9a-f]+ <[^>]*> 43000031 c0 0x1000031
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||||
[0-9a-f]+ <[^>]*> 43000032 c0 0x1000032
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||||
[0-9a-f]+ <[^>]*> 43000033 c0 0x1000033
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||||
[0-9a-f]+ <[^>]*> 43000034 c0 0x1000034
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||||
[0-9a-f]+ <[^>]*> 43000035 c0 0x1000035
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||||
[0-9a-f]+ <[^>]*> 43000036 c0 0x1000036
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||||
[0-9a-f]+ <[^>]*> 43000037 c0 0x1000037
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||||
[0-9a-f]+ <[^>]*> 43000038 c0 0x1000038
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||||
[0-9a-f]+ <[^>]*> 43000039 c0 0x1000039
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||||
[0-9a-f]+ <[^>]*> 4300003a c0 0x100003a
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||||
[0-9a-f]+ <[^>]*> 4300003b c0 0x100003b
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||||
[0-9a-f]+ <[^>]*> 4300003c c0 0x100003c
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||||
[0-9a-f]+ <[^>]*> 4300003d c0 0x100003d
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||||
[0-9a-f]+ <[^>]*> 4300003e c0 0x100003e
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||||
[0-9a-f]+ <[^>]*> 4300003f c0 0x100003f
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[0-9a-f]+ <[^>]*> 42000000 c0 0x0
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[0-9a-f]+ <[^>]*> 42000001 tlbr
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[0-9a-f]+ <[^>]*> 42000002 tlbwi
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[0-9a-f]+ <[^>]*> 42000003 c0 0x3
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[0-9a-f]+ <[^>]*> 42000004 c0 0x4
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[0-9a-f]+ <[^>]*> 42000005 c0 0x5
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[0-9a-f]+ <[^>]*> 42000006 tlbwr
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||||
[0-9a-f]+ <[^>]*> 42000007 c0 0x7
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[0-9a-f]+ <[^>]*> 42000008 tlbp
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||||
[0-9a-f]+ <[^>]*> 42000009 c0 0x9
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||||
[0-9a-f]+ <[^>]*> 4200000a c0 0xa
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||||
[0-9a-f]+ <[^>]*> 4200000b c0 0xb
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||||
[0-9a-f]+ <[^>]*> 4200000c c0 0xc
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||||
[0-9a-f]+ <[^>]*> 4200000d c0 0xd
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||||
[0-9a-f]+ <[^>]*> 4200000e c0 0xe
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||||
[0-9a-f]+ <[^>]*> 4200000f c0 0xf
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||||
[0-9a-f]+ <[^>]*> 42000010 c0 0x10
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||||
[0-9a-f]+ <[^>]*> 42000011 c0 0x11
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||||
[0-9a-f]+ <[^>]*> 42000012 c0 0x12
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||||
[0-9a-f]+ <[^>]*> 42000013 c0 0x13
|
||||
[0-9a-f]+ <[^>]*> 42000014 c0 0x14
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||||
[0-9a-f]+ <[^>]*> 42000015 c0 0x15
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||||
[0-9a-f]+ <[^>]*> 42000016 c0 0x16
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||||
[0-9a-f]+ <[^>]*> 42000017 c0 0x17
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[0-9a-f]+ <[^>]*> 42000018 eret
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||||
[0-9a-f]+ <[^>]*> 42000019 c0 0x19
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||||
[0-9a-f]+ <[^>]*> 4200001a c0 0x1a
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||||
[0-9a-f]+ <[^>]*> 4200001b c0 0x1b
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||||
[0-9a-f]+ <[^>]*> 4200001c c0 0x1c
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||||
[0-9a-f]+ <[^>]*> 4200001d c0 0x1d
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||||
[0-9a-f]+ <[^>]*> 4200001e c0 0x1e
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||||
[0-9a-f]+ <[^>]*> 4200001f c0 0x1f
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||||
[0-9a-f]+ <[^>]*> 42000020 c0 0x20
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||||
[0-9a-f]+ <[^>]*> 42000021 c0 0x21
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||||
[0-9a-f]+ <[^>]*> 42000022 c0 0x22
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||||
[0-9a-f]+ <[^>]*> 42000023 c0 0x23
|
||||
[0-9a-f]+ <[^>]*> 42000024 c0 0x24
|
||||
[0-9a-f]+ <[^>]*> 42000025 c0 0x25
|
||||
[0-9a-f]+ <[^>]*> 42000026 c0 0x26
|
||||
[0-9a-f]+ <[^>]*> 42000027 c0 0x27
|
||||
[0-9a-f]+ <[^>]*> 42000028 c0 0x28
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||||
[0-9a-f]+ <[^>]*> 42000029 c0 0x29
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||||
[0-9a-f]+ <[^>]*> 4200002a c0 0x2a
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||||
[0-9a-f]+ <[^>]*> 4200002b c0 0x2b
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||||
[0-9a-f]+ <[^>]*> 4200002c c0 0x2c
|
||||
[0-9a-f]+ <[^>]*> 4200002d c0 0x2d
|
||||
[0-9a-f]+ <[^>]*> 4200002e c0 0x2e
|
||||
[0-9a-f]+ <[^>]*> 4200002f c0 0x2f
|
||||
[0-9a-f]+ <[^>]*> 42000030 c0 0x30
|
||||
[0-9a-f]+ <[^>]*> 42000031 c0 0x31
|
||||
[0-9a-f]+ <[^>]*> 42000032 c0 0x32
|
||||
[0-9a-f]+ <[^>]*> 42000033 c0 0x33
|
||||
[0-9a-f]+ <[^>]*> 42000034 c0 0x34
|
||||
[0-9a-f]+ <[^>]*> 42000035 c0 0x35
|
||||
[0-9a-f]+ <[^>]*> 42000036 c0 0x36
|
||||
[0-9a-f]+ <[^>]*> 42000037 c0 0x37
|
||||
[0-9a-f]+ <[^>]*> 42000038 c0 0x38
|
||||
[0-9a-f]+ <[^>]*> 42000039 c0 0x39
|
||||
[0-9a-f]+ <[^>]*> 4200003a c0 0x3a
|
||||
[0-9a-f]+ <[^>]*> 4200003b c0 0x3b
|
||||
[0-9a-f]+ <[^>]*> 4200003c c0 0x3c
|
||||
[0-9a-f]+ <[^>]*> 4200003d c0 0x3d
|
||||
[0-9a-f]+ <[^>]*> 4200003e c0 0x3e
|
||||
[0-9a-f]+ <[^>]*> 4200003f c0 0x3f
|
||||
[0-9a-f]+ <[^>]*> 43000000 c0 0x1000000
|
||||
[0-9a-f]+ <[^>]*> 43000001 c0 0x1000001
|
||||
[0-9a-f]+ <[^>]*> 43000002 c0 0x1000002
|
||||
[0-9a-f]+ <[^>]*> 43000003 c0 0x1000003
|
||||
[0-9a-f]+ <[^>]*> 43000004 c0 0x1000004
|
||||
[0-9a-f]+ <[^>]*> 43000005 c0 0x1000005
|
||||
[0-9a-f]+ <[^>]*> 43000006 c0 0x1000006
|
||||
[0-9a-f]+ <[^>]*> 43000007 c0 0x1000007
|
||||
[0-9a-f]+ <[^>]*> 43000008 c0 0x1000008
|
||||
[0-9a-f]+ <[^>]*> 43000009 c0 0x1000009
|
||||
[0-9a-f]+ <[^>]*> 4300000a c0 0x100000a
|
||||
[0-9a-f]+ <[^>]*> 4300000b c0 0x100000b
|
||||
[0-9a-f]+ <[^>]*> 4300000c c0 0x100000c
|
||||
[0-9a-f]+ <[^>]*> 4300000d c0 0x100000d
|
||||
[0-9a-f]+ <[^>]*> 4300000e c0 0x100000e
|
||||
[0-9a-f]+ <[^>]*> 4300000f c0 0x100000f
|
||||
[0-9a-f]+ <[^>]*> 43000010 c0 0x1000010
|
||||
[0-9a-f]+ <[^>]*> 43000011 c0 0x1000011
|
||||
[0-9a-f]+ <[^>]*> 43000012 c0 0x1000012
|
||||
[0-9a-f]+ <[^>]*> 43000013 c0 0x1000013
|
||||
[0-9a-f]+ <[^>]*> 43000014 c0 0x1000014
|
||||
[0-9a-f]+ <[^>]*> 43000015 c0 0x1000015
|
||||
[0-9a-f]+ <[^>]*> 43000016 c0 0x1000016
|
||||
[0-9a-f]+ <[^>]*> 43000017 c0 0x1000017
|
||||
[0-9a-f]+ <[^>]*> 43000018 c0 0x1000018
|
||||
[0-9a-f]+ <[^>]*> 43000019 c0 0x1000019
|
||||
[0-9a-f]+ <[^>]*> 4300001a c0 0x100001a
|
||||
[0-9a-f]+ <[^>]*> 4300001b c0 0x100001b
|
||||
[0-9a-f]+ <[^>]*> 4300001c c0 0x100001c
|
||||
[0-9a-f]+ <[^>]*> 4300001d c0 0x100001d
|
||||
[0-9a-f]+ <[^>]*> 4300001e c0 0x100001e
|
||||
[0-9a-f]+ <[^>]*> 4300001f c0 0x100001f
|
||||
[0-9a-f]+ <[^>]*> 43000020 c0 0x1000020
|
||||
[0-9a-f]+ <[^>]*> 43000021 c0 0x1000021
|
||||
[0-9a-f]+ <[^>]*> 43000022 c0 0x1000022
|
||||
[0-9a-f]+ <[^>]*> 43000023 c0 0x1000023
|
||||
[0-9a-f]+ <[^>]*> 43000024 c0 0x1000024
|
||||
[0-9a-f]+ <[^>]*> 43000025 c0 0x1000025
|
||||
[0-9a-f]+ <[^>]*> 43000026 c0 0x1000026
|
||||
[0-9a-f]+ <[^>]*> 43000027 c0 0x1000027
|
||||
[0-9a-f]+ <[^>]*> 43000028 c0 0x1000028
|
||||
[0-9a-f]+ <[^>]*> 43000029 c0 0x1000029
|
||||
[0-9a-f]+ <[^>]*> 4300002a c0 0x100002a
|
||||
[0-9a-f]+ <[^>]*> 4300002b c0 0x100002b
|
||||
[0-9a-f]+ <[^>]*> 4300002c c0 0x100002c
|
||||
[0-9a-f]+ <[^>]*> 4300002d c0 0x100002d
|
||||
[0-9a-f]+ <[^>]*> 4300002e c0 0x100002e
|
||||
[0-9a-f]+ <[^>]*> 4300002f c0 0x100002f
|
||||
[0-9a-f]+ <[^>]*> 43000030 c0 0x1000030
|
||||
[0-9a-f]+ <[^>]*> 43000031 c0 0x1000031
|
||||
[0-9a-f]+ <[^>]*> 43000032 c0 0x1000032
|
||||
[0-9a-f]+ <[^>]*> 43000033 c0 0x1000033
|
||||
[0-9a-f]+ <[^>]*> 43000034 c0 0x1000034
|
||||
[0-9a-f]+ <[^>]*> 43000035 c0 0x1000035
|
||||
[0-9a-f]+ <[^>]*> 43000036 c0 0x1000036
|
||||
[0-9a-f]+ <[^>]*> 43000037 c0 0x1000037
|
||||
[0-9a-f]+ <[^>]*> 43000038 c0 0x1000038
|
||||
[0-9a-f]+ <[^>]*> 43000039 c0 0x1000039
|
||||
[0-9a-f]+ <[^>]*> 4300003a c0 0x100003a
|
||||
[0-9a-f]+ <[^>]*> 4300003b c0 0x100003b
|
||||
[0-9a-f]+ <[^>]*> 4300003c c0 0x100003c
|
||||
[0-9a-f]+ <[^>]*> 4300003d c0 0x100003d
|
||||
[0-9a-f]+ <[^>]*> 4300003e c0 0x100003e
|
||||
[0-9a-f]+ <[^>]*> 4300003f c0 0x100003f
|
||||
\.\.\.
|
||||
265
gas/testsuite/gas/mips/allegrex@c1.d
Normal file
265
gas/testsuite/gas/mips/allegrex@c1.d
Normal file
@ -0,0 +1,265 @@
|
||||
#objdump: -d --prefix-addresses --show-raw-insn
|
||||
#name: MIPS C1/COP1 instructions
|
||||
#as: -32
|
||||
#source: c1.s
|
||||
|
||||
.*: +file format .*mips.*
|
||||
|
||||
Disassembly of section \.text:
|
||||
[0-9a-f]+ <[^>]*> 46000000 add\.s \$f0,\$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000001 sub\.s \$f0,\$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000002 mul\.s \$f0,\$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000003 div\.s \$f0,\$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000004 sqrt\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000005 abs\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000006 mov\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000007 neg\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000008 c1 0x8
|
||||
[0-9a-f]+ <[^>]*> 46000009 c1 0x9
|
||||
[0-9a-f]+ <[^>]*> 4600000a c1 0xa
|
||||
[0-9a-f]+ <[^>]*> 4600000b c1 0xb
|
||||
[0-9a-f]+ <[^>]*> 4600000c round\.w\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 4600000d trunc\.w\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 4600000e ceil\.w\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 4600000f floor\.w\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000010 c1 0x10
|
||||
[0-9a-f]+ <[^>]*> 46000011 c1 0x11
|
||||
[0-9a-f]+ <[^>]*> 46000012 c1 0x12
|
||||
[0-9a-f]+ <[^>]*> 46000013 c1 0x13
|
||||
[0-9a-f]+ <[^>]*> 46000014 c1 0x14
|
||||
[0-9a-f]+ <[^>]*> 46000015 c1 0x15
|
||||
[0-9a-f]+ <[^>]*> 46000016 c1 0x16
|
||||
[0-9a-f]+ <[^>]*> 46000017 c1 0x17
|
||||
[0-9a-f]+ <[^>]*> 46000018 c1 0x18
|
||||
[0-9a-f]+ <[^>]*> 46000019 c1 0x19
|
||||
[0-9a-f]+ <[^>]*> 4600001a c1 0x1a
|
||||
[0-9a-f]+ <[^>]*> 4600001b c1 0x1b
|
||||
[0-9a-f]+ <[^>]*> 4600001c c1 0x1c
|
||||
[0-9a-f]+ <[^>]*> 4600001d c1 0x1d
|
||||
[0-9a-f]+ <[^>]*> 4600001e c1 0x1e
|
||||
[0-9a-f]+ <[^>]*> 4600001f c1 0x1f
|
||||
[0-9a-f]+ <[^>]*> 46000020 c1 0x20
|
||||
[0-9a-f]+ <[^>]*> 46000021 c1 0x21
|
||||
[0-9a-f]+ <[^>]*> 46000022 c1 0x22
|
||||
[0-9a-f]+ <[^>]*> 46000023 c1 0x23
|
||||
[0-9a-f]+ <[^>]*> 46000024 cvt\.w\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000025 c1 0x25
|
||||
[0-9a-f]+ <[^>]*> 46000026 c1 0x26
|
||||
[0-9a-f]+ <[^>]*> 46000027 c1 0x27
|
||||
[0-9a-f]+ <[^>]*> 46000028 c1 0x28
|
||||
[0-9a-f]+ <[^>]*> 46000029 c1 0x29
|
||||
[0-9a-f]+ <[^>]*> 4600002a c1 0x2a
|
||||
[0-9a-f]+ <[^>]*> 4600002b c1 0x2b
|
||||
[0-9a-f]+ <[^>]*> 4600002c c1 0x2c
|
||||
[0-9a-f]+ <[^>]*> 4600002d c1 0x2d
|
||||
[0-9a-f]+ <[^>]*> 4600002e c1 0x2e
|
||||
[0-9a-f]+ <[^>]*> 4600002f c1 0x2f
|
||||
[0-9a-f]+ <[^>]*> 46000030 c\.f\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000031 c\.un\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000032 c\.eq\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000033 c\.ueq\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000034 c\.olt\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000035 c\.ult\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000036 c\.ole\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000037 c\.ule\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000038 c\.sf\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000039 c\.ngle\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 4600003a c\.seq\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 4600003b c\.ngl\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 4600003c c\.lt\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 4600003d c\.nge\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 4600003e c\.le\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 4600003f c\.ngt\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 47000000 c1 0x1000000
|
||||
[0-9a-f]+ <[^>]*> 47000001 c1 0x1000001
|
||||
[0-9a-f]+ <[^>]*> 47000002 c1 0x1000002
|
||||
[0-9a-f]+ <[^>]*> 47000003 c1 0x1000003
|
||||
[0-9a-f]+ <[^>]*> 47000004 c1 0x1000004
|
||||
[0-9a-f]+ <[^>]*> 47000005 c1 0x1000005
|
||||
[0-9a-f]+ <[^>]*> 47000006 c1 0x1000006
|
||||
[0-9a-f]+ <[^>]*> 47000007 c1 0x1000007
|
||||
[0-9a-f]+ <[^>]*> 47000008 c1 0x1000008
|
||||
[0-9a-f]+ <[^>]*> 47000009 c1 0x1000009
|
||||
[0-9a-f]+ <[^>]*> 4700000a c1 0x100000a
|
||||
[0-9a-f]+ <[^>]*> 4700000b c1 0x100000b
|
||||
[0-9a-f]+ <[^>]*> 4700000c c1 0x100000c
|
||||
[0-9a-f]+ <[^>]*> 4700000d c1 0x100000d
|
||||
[0-9a-f]+ <[^>]*> 4700000e c1 0x100000e
|
||||
[0-9a-f]+ <[^>]*> 4700000f c1 0x100000f
|
||||
[0-9a-f]+ <[^>]*> 47000010 c1 0x1000010
|
||||
[0-9a-f]+ <[^>]*> 47000011 c1 0x1000011
|
||||
[0-9a-f]+ <[^>]*> 47000012 c1 0x1000012
|
||||
[0-9a-f]+ <[^>]*> 47000013 c1 0x1000013
|
||||
[0-9a-f]+ <[^>]*> 47000014 c1 0x1000014
|
||||
[0-9a-f]+ <[^>]*> 47000015 c1 0x1000015
|
||||
[0-9a-f]+ <[^>]*> 47000016 c1 0x1000016
|
||||
[0-9a-f]+ <[^>]*> 47000017 c1 0x1000017
|
||||
[0-9a-f]+ <[^>]*> 47000018 c1 0x1000018
|
||||
[0-9a-f]+ <[^>]*> 47000019 c1 0x1000019
|
||||
[0-9a-f]+ <[^>]*> 4700001a c1 0x100001a
|
||||
[0-9a-f]+ <[^>]*> 4700001b c1 0x100001b
|
||||
[0-9a-f]+ <[^>]*> 4700001c c1 0x100001c
|
||||
[0-9a-f]+ <[^>]*> 4700001d c1 0x100001d
|
||||
[0-9a-f]+ <[^>]*> 4700001e c1 0x100001e
|
||||
[0-9a-f]+ <[^>]*> 4700001f c1 0x100001f
|
||||
[0-9a-f]+ <[^>]*> 47000020 c1 0x1000020
|
||||
[0-9a-f]+ <[^>]*> 47000021 c1 0x1000021
|
||||
[0-9a-f]+ <[^>]*> 47000022 c1 0x1000022
|
||||
[0-9a-f]+ <[^>]*> 47000023 c1 0x1000023
|
||||
[0-9a-f]+ <[^>]*> 47000024 c1 0x1000024
|
||||
[0-9a-f]+ <[^>]*> 47000025 c1 0x1000025
|
||||
[0-9a-f]+ <[^>]*> 47000026 c1 0x1000026
|
||||
[0-9a-f]+ <[^>]*> 47000027 c1 0x1000027
|
||||
[0-9a-f]+ <[^>]*> 47000028 c1 0x1000028
|
||||
[0-9a-f]+ <[^>]*> 47000029 c1 0x1000029
|
||||
[0-9a-f]+ <[^>]*> 4700002a c1 0x100002a
|
||||
[0-9a-f]+ <[^>]*> 4700002b c1 0x100002b
|
||||
[0-9a-f]+ <[^>]*> 4700002c c1 0x100002c
|
||||
[0-9a-f]+ <[^>]*> 4700002d c1 0x100002d
|
||||
[0-9a-f]+ <[^>]*> 4700002e c1 0x100002e
|
||||
[0-9a-f]+ <[^>]*> 4700002f c1 0x100002f
|
||||
[0-9a-f]+ <[^>]*> 47000030 c1 0x1000030
|
||||
[0-9a-f]+ <[^>]*> 47000031 c1 0x1000031
|
||||
[0-9a-f]+ <[^>]*> 47000032 c1 0x1000032
|
||||
[0-9a-f]+ <[^>]*> 47000033 c1 0x1000033
|
||||
[0-9a-f]+ <[^>]*> 47000034 c1 0x1000034
|
||||
[0-9a-f]+ <[^>]*> 47000035 c1 0x1000035
|
||||
[0-9a-f]+ <[^>]*> 47000036 c1 0x1000036
|
||||
[0-9a-f]+ <[^>]*> 47000037 c1 0x1000037
|
||||
[0-9a-f]+ <[^>]*> 47000038 c1 0x1000038
|
||||
[0-9a-f]+ <[^>]*> 47000039 c1 0x1000039
|
||||
[0-9a-f]+ <[^>]*> 4700003a c1 0x100003a
|
||||
[0-9a-f]+ <[^>]*> 4700003b c1 0x100003b
|
||||
[0-9a-f]+ <[^>]*> 4700003c c1 0x100003c
|
||||
[0-9a-f]+ <[^>]*> 4700003d c1 0x100003d
|
||||
[0-9a-f]+ <[^>]*> 4700003e c1 0x100003e
|
||||
[0-9a-f]+ <[^>]*> 4700003f c1 0x100003f
|
||||
[0-9a-f]+ <[^>]*> 46000000 add\.s \$f0,\$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000001 sub\.s \$f0,\$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000002 mul\.s \$f0,\$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000003 div\.s \$f0,\$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000004 sqrt\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000005 abs\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000006 mov\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000007 neg\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000008 c1 0x8
|
||||
[0-9a-f]+ <[^>]*> 46000009 c1 0x9
|
||||
[0-9a-f]+ <[^>]*> 4600000a c1 0xa
|
||||
[0-9a-f]+ <[^>]*> 4600000b c1 0xb
|
||||
[0-9a-f]+ <[^>]*> 4600000c round\.w\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 4600000d trunc\.w\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 4600000e ceil\.w\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 4600000f floor\.w\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000010 c1 0x10
|
||||
[0-9a-f]+ <[^>]*> 46000011 c1 0x11
|
||||
[0-9a-f]+ <[^>]*> 46000012 c1 0x12
|
||||
[0-9a-f]+ <[^>]*> 46000013 c1 0x13
|
||||
[0-9a-f]+ <[^>]*> 46000014 c1 0x14
|
||||
[0-9a-f]+ <[^>]*> 46000015 c1 0x15
|
||||
[0-9a-f]+ <[^>]*> 46000016 c1 0x16
|
||||
[0-9a-f]+ <[^>]*> 46000017 c1 0x17
|
||||
[0-9a-f]+ <[^>]*> 46000018 c1 0x18
|
||||
[0-9a-f]+ <[^>]*> 46000019 c1 0x19
|
||||
[0-9a-f]+ <[^>]*> 4600001a c1 0x1a
|
||||
[0-9a-f]+ <[^>]*> 4600001b c1 0x1b
|
||||
[0-9a-f]+ <[^>]*> 4600001c c1 0x1c
|
||||
[0-9a-f]+ <[^>]*> 4600001d c1 0x1d
|
||||
[0-9a-f]+ <[^>]*> 4600001e c1 0x1e
|
||||
[0-9a-f]+ <[^>]*> 4600001f c1 0x1f
|
||||
[0-9a-f]+ <[^>]*> 46000020 c1 0x20
|
||||
[0-9a-f]+ <[^>]*> 46000021 c1 0x21
|
||||
[0-9a-f]+ <[^>]*> 46000022 c1 0x22
|
||||
[0-9a-f]+ <[^>]*> 46000023 c1 0x23
|
||||
[0-9a-f]+ <[^>]*> 46000024 cvt\.w\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000025 c1 0x25
|
||||
[0-9a-f]+ <[^>]*> 46000026 c1 0x26
|
||||
[0-9a-f]+ <[^>]*> 46000027 c1 0x27
|
||||
[0-9a-f]+ <[^>]*> 46000028 c1 0x28
|
||||
[0-9a-f]+ <[^>]*> 46000029 c1 0x29
|
||||
[0-9a-f]+ <[^>]*> 4600002a c1 0x2a
|
||||
[0-9a-f]+ <[^>]*> 4600002b c1 0x2b
|
||||
[0-9a-f]+ <[^>]*> 4600002c c1 0x2c
|
||||
[0-9a-f]+ <[^>]*> 4600002d c1 0x2d
|
||||
[0-9a-f]+ <[^>]*> 4600002e c1 0x2e
|
||||
[0-9a-f]+ <[^>]*> 4600002f c1 0x2f
|
||||
[0-9a-f]+ <[^>]*> 46000030 c\.f\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000031 c\.un\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000032 c\.eq\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000033 c\.ueq\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000034 c\.olt\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000035 c\.ult\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000036 c\.ole\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000037 c\.ule\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000038 c\.sf\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 46000039 c\.ngle\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 4600003a c\.seq\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 4600003b c\.ngl\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 4600003c c\.lt\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 4600003d c\.nge\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 4600003e c\.le\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 4600003f c\.ngt\.s \$f0,\$f0
|
||||
[0-9a-f]+ <[^>]*> 47000000 c1 0x1000000
|
||||
[0-9a-f]+ <[^>]*> 47000001 c1 0x1000001
|
||||
[0-9a-f]+ <[^>]*> 47000002 c1 0x1000002
|
||||
[0-9a-f]+ <[^>]*> 47000003 c1 0x1000003
|
||||
[0-9a-f]+ <[^>]*> 47000004 c1 0x1000004
|
||||
[0-9a-f]+ <[^>]*> 47000005 c1 0x1000005
|
||||
[0-9a-f]+ <[^>]*> 47000006 c1 0x1000006
|
||||
[0-9a-f]+ <[^>]*> 47000007 c1 0x1000007
|
||||
[0-9a-f]+ <[^>]*> 47000008 c1 0x1000008
|
||||
[0-9a-f]+ <[^>]*> 47000009 c1 0x1000009
|
||||
[0-9a-f]+ <[^>]*> 4700000a c1 0x100000a
|
||||
[0-9a-f]+ <[^>]*> 4700000b c1 0x100000b
|
||||
[0-9a-f]+ <[^>]*> 4700000c c1 0x100000c
|
||||
[0-9a-f]+ <[^>]*> 4700000d c1 0x100000d
|
||||
[0-9a-f]+ <[^>]*> 4700000e c1 0x100000e
|
||||
[0-9a-f]+ <[^>]*> 4700000f c1 0x100000f
|
||||
[0-9a-f]+ <[^>]*> 47000010 c1 0x1000010
|
||||
[0-9a-f]+ <[^>]*> 47000011 c1 0x1000011
|
||||
[0-9a-f]+ <[^>]*> 47000012 c1 0x1000012
|
||||
[0-9a-f]+ <[^>]*> 47000013 c1 0x1000013
|
||||
[0-9a-f]+ <[^>]*> 47000014 c1 0x1000014
|
||||
[0-9a-f]+ <[^>]*> 47000015 c1 0x1000015
|
||||
[0-9a-f]+ <[^>]*> 47000016 c1 0x1000016
|
||||
[0-9a-f]+ <[^>]*> 47000017 c1 0x1000017
|
||||
[0-9a-f]+ <[^>]*> 47000018 c1 0x1000018
|
||||
[0-9a-f]+ <[^>]*> 47000019 c1 0x1000019
|
||||
[0-9a-f]+ <[^>]*> 4700001a c1 0x100001a
|
||||
[0-9a-f]+ <[^>]*> 4700001b c1 0x100001b
|
||||
[0-9a-f]+ <[^>]*> 4700001c c1 0x100001c
|
||||
[0-9a-f]+ <[^>]*> 4700001d c1 0x100001d
|
||||
[0-9a-f]+ <[^>]*> 4700001e c1 0x100001e
|
||||
[0-9a-f]+ <[^>]*> 4700001f c1 0x100001f
|
||||
[0-9a-f]+ <[^>]*> 47000020 c1 0x1000020
|
||||
[0-9a-f]+ <[^>]*> 47000021 c1 0x1000021
|
||||
[0-9a-f]+ <[^>]*> 47000022 c1 0x1000022
|
||||
[0-9a-f]+ <[^>]*> 47000023 c1 0x1000023
|
||||
[0-9a-f]+ <[^>]*> 47000024 c1 0x1000024
|
||||
[0-9a-f]+ <[^>]*> 47000025 c1 0x1000025
|
||||
[0-9a-f]+ <[^>]*> 47000026 c1 0x1000026
|
||||
[0-9a-f]+ <[^>]*> 47000027 c1 0x1000027
|
||||
[0-9a-f]+ <[^>]*> 47000028 c1 0x1000028
|
||||
[0-9a-f]+ <[^>]*> 47000029 c1 0x1000029
|
||||
[0-9a-f]+ <[^>]*> 4700002a c1 0x100002a
|
||||
[0-9a-f]+ <[^>]*> 4700002b c1 0x100002b
|
||||
[0-9a-f]+ <[^>]*> 4700002c c1 0x100002c
|
||||
[0-9a-f]+ <[^>]*> 4700002d c1 0x100002d
|
||||
[0-9a-f]+ <[^>]*> 4700002e c1 0x100002e
|
||||
[0-9a-f]+ <[^>]*> 4700002f c1 0x100002f
|
||||
[0-9a-f]+ <[^>]*> 47000030 c1 0x1000030
|
||||
[0-9a-f]+ <[^>]*> 47000031 c1 0x1000031
|
||||
[0-9a-f]+ <[^>]*> 47000032 c1 0x1000032
|
||||
[0-9a-f]+ <[^>]*> 47000033 c1 0x1000033
|
||||
[0-9a-f]+ <[^>]*> 47000034 c1 0x1000034
|
||||
[0-9a-f]+ <[^>]*> 47000035 c1 0x1000035
|
||||
[0-9a-f]+ <[^>]*> 47000036 c1 0x1000036
|
||||
[0-9a-f]+ <[^>]*> 47000037 c1 0x1000037
|
||||
[0-9a-f]+ <[^>]*> 47000038 c1 0x1000038
|
||||
[0-9a-f]+ <[^>]*> 47000039 c1 0x1000039
|
||||
[0-9a-f]+ <[^>]*> 4700003a c1 0x100003a
|
||||
[0-9a-f]+ <[^>]*> 4700003b c1 0x100003b
|
||||
[0-9a-f]+ <[^>]*> 4700003c c1 0x100003c
|
||||
[0-9a-f]+ <[^>]*> 4700003d c1 0x100003d
|
||||
[0-9a-f]+ <[^>]*> 4700003e c1 0x100003e
|
||||
[0-9a-f]+ <[^>]*> 4700003f c1 0x100003f
|
||||
\.\.\.
|
||||
5
gas/testsuite/gas/mips/allegrex@c3.d
Normal file
5
gas/testsuite/gas/mips/allegrex@c3.d
Normal file
@ -0,0 +1,5 @@
|
||||
#objdump: -d --prefix-addresses --show-raw-insn
|
||||
#name: MIPS C3/COP3 instructions
|
||||
#as: -32
|
||||
#source: c3.s
|
||||
#dump: mips1@c3.d
|
||||
5
gas/testsuite/gas/mips/allegrex@cp0b.d
Normal file
5
gas/testsuite/gas/mips/allegrex@cp0b.d
Normal file
@ -0,0 +1,5 @@
|
||||
#objdump: -d --prefix-addresses --show-raw-insn
|
||||
#name: MIPS CP0 branch instructions
|
||||
#as: -32
|
||||
#source: cp0b.s
|
||||
#dump: mips1@cp0b.d
|
||||
5
gas/testsuite/gas/mips/allegrex@cp0bl.d
Normal file
5
gas/testsuite/gas/mips/allegrex@cp0bl.d
Normal file
@ -0,0 +1,5 @@
|
||||
#objdump: -d --prefix-addresses --show-raw-insn
|
||||
#name: MIPS CP0 branch likely instructions
|
||||
#as: -32
|
||||
#source: cp0bl.s
|
||||
#dump: mips2@cp0bl.d
|
||||
5
gas/testsuite/gas/mips/allegrex@cp0c.d
Normal file
5
gas/testsuite/gas/mips/allegrex@cp0c.d
Normal file
@ -0,0 +1,5 @@
|
||||
#objdump: -d --prefix-addresses --show-raw-insn
|
||||
#name: MIPS CP0 control register move instructions
|
||||
#as: -32
|
||||
#source: cp0c.s
|
||||
#dump: mips1@cp0c.d
|
||||
5
gas/testsuite/gas/mips/allegrex@cp2d.d
Normal file
5
gas/testsuite/gas/mips/allegrex@cp2d.d
Normal file
@ -0,0 +1,5 @@
|
||||
#objdump: -d --prefix-addresses --show-raw-insn
|
||||
#name: MIPS CP2 doubleword memory access instructions
|
||||
#as: -32
|
||||
#error_output: cp2d.l
|
||||
#source: cp2d.s
|
||||
29
gas/testsuite/gas/mips/allegrex@isa-override-1.d
Normal file
29
gas/testsuite/gas/mips/allegrex@isa-override-1.d
Normal file
@ -0,0 +1,29 @@
|
||||
#objdump: -dr --prefix-addresses --show-raw-insn
|
||||
#name: MIPS ISA override code generation
|
||||
#as: -32
|
||||
#source: r5900@isa-override-1.s
|
||||
|
||||
.*: +file format .*mips.*
|
||||
|
||||
Disassembly of section \.text:
|
||||
[0-9a-f]+ <[^>]*> 8c820000 lw v0,0\(a0\)
|
||||
[0-9a-f]+ <[^>]*> 8c830004 lw v1,4\(a0\)
|
||||
[0-9a-f]+ <[^>]*> 3c0189ab lui at,0x89ab
|
||||
[0-9a-f]+ <[^>]*> 00411025 or v0,v0,at
|
||||
[0-9a-f]+ <[^>]*> dc820000 .word 0xdc820000
|
||||
[0-9a-f]+ <[^>]*> 340189ab li at,0x89ab
|
||||
[0-9a-f]+ <[^>]*> 00010c38 .word 0x10c38
|
||||
[0-9a-f]+ <[^>]*> 00411025 or v0,v0,at
|
||||
[0-9a-f]+ <[^>]*> 3c029000 lui v0,0x9000
|
||||
[0-9a-f]+ <[^>]*> 00021438 .word 0x21438
|
||||
[0-9a-f]+ <[^>]*> 34428000 ori v0,v0,0x8000
|
||||
[0-9a-f]+ <[^>]*> 00021438 .word 0x21438
|
||||
[0-9a-f]+ <[^>]*> 8c820000 lw v0,0\(a0\)
|
||||
[0-9a-f]+ <[^>]*> 8c830004 lw v1,4\(a0\)
|
||||
[0-9a-f]+ <[^>]*> 3c0189ab lui at,0x89ab
|
||||
[0-9a-f]+ <[^>]*> 00411025 or v0,v0,at
|
||||
[0-9a-f]+ <[^>]*> 8c820000 lw v0,0\(a0\)
|
||||
[0-9a-f]+ <[^>]*> 8c830004 lw v1,4\(a0\)
|
||||
[0-9a-f]+ <[^>]*> 3c0189ab lui at,0x89ab
|
||||
[0-9a-f]+ <[^>]*> 00411025 or v0,v0,at
|
||||
\.\.\.
|
||||
4
gas/testsuite/gas/mips/allegrex@isa-override-2.d
Normal file
4
gas/testsuite/gas/mips/allegrex@isa-override-2.d
Normal file
@ -0,0 +1,4 @@
|
||||
#name: MIPS ISA override code generation 2
|
||||
#as: -32
|
||||
#source: isa-override-2.s
|
||||
#error_output: allegrex@isa-override-2.l
|
||||
4
gas/testsuite/gas/mips/allegrex@isa-override-2.l
Normal file
4
gas/testsuite/gas/mips/allegrex@isa-override-2.l
Normal file
@ -0,0 +1,4 @@
|
||||
.*: Assembler messages:
|
||||
.*:5: Error: opcode not supported on this processor: allegrex \(mips2\) `dli \$2,0x9000000080000000'
|
||||
.*:10: Error: opcode not supported on this processor: allegrex \(mips2\) `dli \$2,0x9000000080000000'
|
||||
.*:13: Error: opcode not supported on this processor: allegrex \(mips2\) `dli \$2,0x9000000080000000'
|
||||
5
gas/testsuite/gas/mips/allegrex@save-sub.d
Normal file
5
gas/testsuite/gas/mips/allegrex@save-sub.d
Normal file
@ -0,0 +1,5 @@
|
||||
#objdump: -dr
|
||||
#as: -32 -I$srcdir/$subdir
|
||||
#name: SAVE/RESTORE instruction subset disassembly
|
||||
#source: save-sub.s
|
||||
#dump: mips1@save-sub.d
|
||||
@ -81,7 +81,7 @@
|
||||
# Registers.
|
||||
#
|
||||
# singlefloat
|
||||
# The CPU is 64 bit, but only supports 32 bit FPU.
|
||||
# The FPU only supports 32-bit operations.
|
||||
#
|
||||
# nollsc
|
||||
# The CPU doesn't support ll, sc, lld and scd instructions.
|
||||
@ -509,6 +509,9 @@ mips_arch_create r3000 32 mips1 {} \
|
||||
mips_arch_create r3900 32 mips1 { gpr_ilocks } \
|
||||
{ -march=r3900 -mtune=r3900 } { -mmips:3900 } \
|
||||
{ mipstx39-*-* mipstx39el-*-* }
|
||||
mips_arch_create allegrex 32 mips2 { singlefloat oddspreg } \
|
||||
{ -march=allegrex -mtune=allegrex } \
|
||||
{ -mmips:allegrex }
|
||||
mips_arch_create r4000 64 mips3 {} \
|
||||
{ -march=r4000 -mtune=r4000 } { -mmips:4000 }
|
||||
mips_arch_create vr5400 64 mips4 { ror } \
|
||||
@ -1358,12 +1361,12 @@ if { [istarget mips*-*-vxworks*] } {
|
||||
run_dump_test "cp1-names-mips64r2"
|
||||
run_dump_test "cp1-names-sb1"
|
||||
|
||||
# The VR5400 and R5900 have their own sets of COP2 instructions, so
|
||||
# The VR5400, R5900 & Allegrex have their own sets of COP2 instructions, so
|
||||
# exclude them from generic testing. Likewise the Octeon and DMFC2/DMTC2.
|
||||
run_dump_test_arches "cp2" [mips_arch_list_matching mips1 \
|
||||
!vr5400 !r5900]
|
||||
!vr5400 !r5900 !allegrex]
|
||||
run_dump_test_arches "cp2-64" [mips_arch_list_matching mips1 \
|
||||
!vr5400 !r5900 !octeon]
|
||||
!vr5400 !r5900 !octeon !allegrex]
|
||||
run_dump_test_arches "cp2b" [mips_arch_list_matching mips1]
|
||||
run_dump_test_arches "cp2bl" [mips_arch_list_matching mips1]
|
||||
run_dump_test_arches "cp2m" [mips_arch_list_matching mips1]
|
||||
@ -1858,7 +1861,8 @@ if { [istarget mips*-*-vxworks*] } {
|
||||
run_dump_test_arches "attr-gnu-4-0" "-mfp32 -32" \
|
||||
[mips_arch_list_matching mips1 !mips32r6]
|
||||
run_dump_test_arches "attr-gnu-4-0" "-mfpxx -32" \
|
||||
[mips_arch_list_matching mips2 !r5900]
|
||||
[mips_arch_list_matching mips2 \
|
||||
!r5900 !allegrex]
|
||||
run_dump_test_arches "attr-gnu-4-0" "-mfp64 -32" \
|
||||
[mips_arch_list_matching mips32r2]
|
||||
run_dump_test_arches "attr-gnu-4-0" "-mfp64 -mno-odd-spreg -32" \
|
||||
@ -1888,7 +1892,8 @@ if { [istarget mips*-*-vxworks*] } {
|
||||
[mips_arch_list_matching mips3]
|
||||
}
|
||||
run_dump_test_arches "attr-none-o32-fpxx" \
|
||||
[mips_arch_list_matching mips2 !r5900]
|
||||
[mips_arch_list_matching mips2 \
|
||||
!r5900 !allegrex]
|
||||
run_dump_test_arches "attr-none-o32-fp64" \
|
||||
[mips_arch_list_matching mips32r2]
|
||||
run_dump_test_arches "attr-none-o32-fp64-nooddspreg" \
|
||||
@ -1920,7 +1925,8 @@ if { [istarget mips*-*-vxworks*] } {
|
||||
run_list_test_arches "attr-gnu-4-1-msoft-float" "-32 -msoft-float" \
|
||||
[mips_arch_list_matching mips1]
|
||||
run_dump_test_arches "attr-gnu-4-1" "-32 -mfpxx" \
|
||||
[mips_arch_list_matching mips2 !r5900]
|
||||
[mips_arch_list_matching mips2 \
|
||||
!r5900 !allegrex]
|
||||
run_dump_test_arches "attr-gnu-4-1" "-32 -mfp32" \
|
||||
[mips_arch_list_matching mips1 !mips32r6]
|
||||
if { $has_newabi } {
|
||||
@ -1931,7 +1937,8 @@ if { [istarget mips*-*-vxworks*] } {
|
||||
run_list_test_arches "attr-gnu-4-2-mdouble-float" "-32 -mfp32" \
|
||||
[mips_arch_list_matching mips1 !mips32r6]
|
||||
run_list_test_arches "attr-gnu-4-2-mdouble-float" "-32 -mfpxx" \
|
||||
[mips_arch_list_matching mips2 !r5900]
|
||||
[mips_arch_list_matching mips2 \
|
||||
!r5900 !allegrex]
|
||||
run_list_test_arches "attr-gnu-4-2-mdouble-float" "-32 -mfp64" \
|
||||
[mips_arch_list_matching mips32r2]
|
||||
run_list_test_arches "attr-gnu-4-2-mdouble-float" \
|
||||
@ -1953,7 +1960,8 @@ if { [istarget mips*-*-vxworks*] } {
|
||||
run_list_test_arches "attr-gnu-4-3-mhard-float" "-32 -mfp32" \
|
||||
[mips_arch_list_matching mips1 !mips32r6]
|
||||
run_list_test_arches "attr-gnu-4-3-mhard-float" "-32 -mfpxx" \
|
||||
[mips_arch_list_matching mips2 !r5900]
|
||||
[mips_arch_list_matching mips2 \
|
||||
!r5900 !allegrex]
|
||||
run_list_test_arches "attr-gnu-4-3-mhard-float" "-32 -mfp64" \
|
||||
[mips_arch_list_matching mips32r2]
|
||||
run_list_test_arches "attr-gnu-4-3-mhard-float" \
|
||||
@ -1975,7 +1983,8 @@ if { [istarget mips*-*-vxworks*] } {
|
||||
run_list_test_arches "attr-gnu-4-4" "-32 -mfp32" \
|
||||
[mips_arch_list_matching mips1 !mips32r6]
|
||||
run_list_test_arches "attr-gnu-4-4" "-32 -mfpxx" \
|
||||
[mips_arch_list_matching mips2 !r5900]
|
||||
[mips_arch_list_matching mips2 \
|
||||
!r5900 !allegrex]
|
||||
run_list_test_arches "attr-gnu-4-4" "-32 -mfp64" \
|
||||
[mips_arch_list_matching mips32r2]
|
||||
run_list_test_arches "attr-gnu-4-4" "-32 -mfp64 -mno-odd-spreg" \
|
||||
@ -2004,7 +2013,8 @@ if { [istarget mips*-*-vxworks*] } {
|
||||
run_list_test_arches "attr-gnu-4-5-msoft-float" "-32 -msoft-float" \
|
||||
[mips_arch_list_matching mips1]
|
||||
run_dump_test_arches "attr-gnu-4-5" \
|
||||
[mips_arch_list_matching mips2 !r5900]
|
||||
[mips_arch_list_matching mips2 \
|
||||
!r5900 !allegrex]
|
||||
|
||||
run_list_test_arches "attr-gnu-4-6" "-32 -mfp32" \
|
||||
[mips_arch_list_matching mips1 !mips32r6]
|
||||
@ -2019,7 +2029,8 @@ if { [istarget mips*-*-vxworks*] } {
|
||||
run_list_test_arches "attr-gnu-4-6-msoft-float" "-32 -msoft-float" \
|
||||
[mips_arch_list_matching mips1]
|
||||
run_list_test_arches "attr-gnu-4-6" "-32 -mfpxx" \
|
||||
[mips_arch_list_matching mips2 !r5900]
|
||||
[mips_arch_list_matching mips2 \
|
||||
!r5900 !allegrex]
|
||||
run_dump_test_arches "attr-gnu-4-6" "-32 -mfp64" \
|
||||
[mips_arch_list_matching mips32r2]
|
||||
|
||||
@ -2036,7 +2047,8 @@ if { [istarget mips*-*-vxworks*] } {
|
||||
run_list_test_arches "attr-gnu-4-7-msoft-float" "-32 -msoft-float" \
|
||||
[mips_arch_list_matching mips1]
|
||||
run_list_test_arches "attr-gnu-4-7" "-32 -mfpxx" \
|
||||
[mips_arch_list_matching mips2 !r5900]
|
||||
[mips_arch_list_matching mips2 \
|
||||
!r5900 !allegrex]
|
||||
run_dump_test_arches "attr-gnu-4-7" "-32 -mfp64 -mno-odd-spreg" \
|
||||
[mips_arch_list_matching mips32r2]
|
||||
|
||||
@ -2062,13 +2074,15 @@ if { [istarget mips*-*-vxworks*] } {
|
||||
run_list_test_arches "fpxx-oddfpreg" "-32 -mfpxx -mno-odd-spreg" \
|
||||
[mips_arch_list_matching mips2 !singlefloat]
|
||||
run_dump_test_arches "fpxx-oddfpreg" \
|
||||
[mips_arch_list_matching oddspreg]
|
||||
[mips_arch_list_matching oddspreg !allegrex]
|
||||
run_dump_test_arches "odd-spreg" "-mfp32" [mips_arch_list_matching oddspreg]
|
||||
run_dump_test_arches "odd-spreg" "-mfpxx" [mips_arch_list_matching oddspreg]
|
||||
run_dump_test_arches "odd-spreg" "-mfpxx" \
|
||||
[mips_arch_list_matching oddspreg !allegrex]
|
||||
run_dump_test_arches "odd-spreg" "-mfp64" [mips_arch_list_matching mips32r2]
|
||||
run_dump_test_arches "no-odd-spreg" "-mfp32" [mips_arch_list_matching mips1 \
|
||||
!mips32r6]
|
||||
run_dump_test_arches "no-odd-spreg" "-mfpxx" [mips_arch_list_matching mips2 !r5900]
|
||||
run_dump_test_arches "no-odd-spreg" "-mfpxx" \
|
||||
[mips_arch_list_matching mips2 !r5900 !allegrex]
|
||||
run_dump_test_arches "no-odd-spreg" "-mfp64" [mips_arch_list_matching mips32r2]
|
||||
run_dump_test "module-check"
|
||||
run_list_test "module-check-warn" "-32"
|
||||
|
||||
@ -284,6 +284,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
|
||||
#define E_MIPS_MACH_3900 0x00810000
|
||||
#define E_MIPS_MACH_4010 0x00820000
|
||||
#define E_MIPS_MACH_4100 0x00830000
|
||||
#define E_MIPS_MACH_ALLEGREX 0x00840000
|
||||
#define E_MIPS_MACH_4650 0x00850000
|
||||
#define E_MIPS_MACH_4120 0x00870000
|
||||
#define E_MIPS_MACH_4111 0x00880000
|
||||
|
||||
@ -1265,6 +1265,8 @@ static const unsigned int mips_isa_table[] = {
|
||||
#define INSN_XLR 0x00000020
|
||||
/* Imagination interAptiv MR2. */
|
||||
#define INSN_INTERAPTIV_MR2 0x04000000
|
||||
/* Sony PSP Allegrex instruction. */
|
||||
#define INSN_ALLEGREX 0x08000000
|
||||
|
||||
/* DSP ASE */
|
||||
#define ASE_DSP 0x00000001
|
||||
@ -1377,6 +1379,7 @@ static const unsigned int mips_isa_table[] = {
|
||||
#define CPU_MIPS64R3 66
|
||||
#define CPU_MIPS64R5 68
|
||||
#define CPU_MIPS64R6 69
|
||||
#define CPU_ALLEGREX 10111431 /* octal 'AL', 31. */
|
||||
#define CPU_SB1 12310201 /* octal 'SB', 01. */
|
||||
#define CPU_LOONGSON_2E 3001
|
||||
#define CPU_LOONGSON_2F 3002
|
||||
@ -1459,6 +1462,9 @@ cpu_is_member (int cpu, unsigned int mask)
|
||||
case CPU_INTERAPTIV_MR2:
|
||||
return (mask & INSN_INTERAPTIV_MR2) != 0;
|
||||
|
||||
case CPU_ALLEGREX:
|
||||
return (mask & INSN_ALLEGREX) != 0;
|
||||
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
|
||||
@ -489,6 +489,9 @@ const struct mips_arch_choice mips_arch_choices[] =
|
||||
{ "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, 0,
|
||||
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
|
||||
mips_hwr_names_numeric },
|
||||
{ "allegrex", 1, bfd_mach_mips_allegrex, CPU_ALLEGREX, ISA_MIPS2, 0,
|
||||
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric,
|
||||
mips_hwr_names_numeric },
|
||||
{ "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, 0,
|
||||
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips,
|
||||
mips_hwr_names_numeric },
|
||||
|
||||
@ -317,6 +317,7 @@ decode_mips_operand (const char *p)
|
||||
/* Emotion Engine MIPS r5900. */
|
||||
#define EE INSN_5900
|
||||
#define M1 INSN_10000
|
||||
#define AL INSN_ALLEGREX
|
||||
#define SB1 INSN_SB1
|
||||
#define N411 INSN_4111
|
||||
#define N412 INSN_4120
|
||||
@ -341,8 +342,10 @@ decode_mips_operand (const char *p)
|
||||
|
||||
#define G3 EE
|
||||
|
||||
/* 64 bit CPU with 32 bit FPU (single float). */
|
||||
#define SF EE
|
||||
/* CPU without 64 bit FPU support (single float only). */
|
||||
#define SF (AL \
|
||||
|EE \
|
||||
)
|
||||
|
||||
/* Support for 128 bit MMI instructions. */
|
||||
#define MMI EE
|
||||
@ -1187,7 +1190,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
||||
{"ei", "t", 0x41606020, 0xffe0ffff, WR_1|WR_C0, 0, I33, 0, 0 },
|
||||
{"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, 0, MT32, 0 },
|
||||
{"emt", "t", 0x41600be1, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 },
|
||||
{"eret", "", 0x42000018, 0xffffffff, NODS, 0, I3_32, 0, 0 },
|
||||
{"eret", "", 0x42000018, 0xffffffff, NODS, 0, I3_32|AL, 0, 0 },
|
||||
{"eretnc", "", 0x42000058, 0xffffffff, NODS, 0, I36, 0, 0 },
|
||||
{"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, 0, MT32, 0 },
|
||||
{"evpe", "t", 0x41600021, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 },
|
||||
@ -1277,10 +1280,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
||||
{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF }, /* ldc1 */
|
||||
{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 },
|
||||
{"ldc2", "E,+:(d)", 0x49c00000, 0xffe00000, RD_3|WR_C2|CLD, 0, I37, 0, 0 },
|
||||
{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I2, 0, N54|IOCT|IOCTP|IOCT2|EE|I37 },
|
||||
{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2, 0, N54|IOCT|IOCTP|IOCT2|EE },
|
||||
{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I2, 0, I3_32|EE },
|
||||
{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2, 0, I3_32|EE },
|
||||
{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I2, 0, N54|IOCT|IOCTP|IOCT2|EE|AL|I37 },
|
||||
{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2, 0, N54|IOCT|IOCTP|IOCT2|EE|AL },
|
||||
{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I2, 0, I3_32|EE|AL },
|
||||
{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2, 0, I3_32|EE|AL },
|
||||
{"ldl", "t,o(b)", 0x68000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, I69 },
|
||||
{"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3, 0, I69 },
|
||||
{"ldr", "t,o(b)", 0x6c000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, I69 },
|
||||
@ -1326,8 +1329,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
||||
{"lwc2", "E,+:(d)", 0x49400000, 0xffe00000, RD_3|WR_C2|CLD, 0, I37, 0, 0 },
|
||||
{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE|I37 },
|
||||
{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE },
|
||||
{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I1, 0, I3_32|EE },
|
||||
{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1, 0, I3_32|EE },
|
||||
{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I1, 0, I3_32|EE|AL },
|
||||
{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1, 0, I3_32|EE|AL },
|
||||
{"lwl", "t,o(b)", 0x88000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, I37 },
|
||||
{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1, 0, I37 },
|
||||
{"lcache", "t,o(b)", 0x88000000, 0xfc000000, WR_1|RD_3|LM, 0, I2, 0, I37 }, /* same */
|
||||
@ -1855,10 +1858,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
||||
{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF },
|
||||
{"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF },
|
||||
{"sdc2", "E,+:(d)", 0x49e00000, 0xffe00000, RD_3|RD_C2|SM, 0, I37, 0, 0 },
|
||||
{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, RD_3|RD_C2|SM, 0, I2, 0, N54|IOCT|IOCTP|IOCT2|EE|I37 },
|
||||
{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2, 0, N54|IOCT|IOCTP|IOCT2|EE },
|
||||
{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, RD_3|RD_C3|SM, 0, I2, 0, I3_32|EE },
|
||||
{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2, 0, I3_32|EE },
|
||||
{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, RD_3|RD_C2|SM, 0, I2, 0, N54|IOCT|IOCTP|IOCT2|EE|AL|I37 },
|
||||
{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2, 0, N54|IOCT|IOCTP|IOCT2|EE|AL },
|
||||
{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, RD_3|RD_C3|SM, 0, I2, 0, I3_32|EE|AL },
|
||||
{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2, 0, I3_32|EE|AL },
|
||||
{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, RD_1|RD_3|SM|FP_D, 0, I2, 0, SF },
|
||||
{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 },
|
||||
{"sdl", "t,o(b)", 0xb0000000, 0xfc000000, RD_1|RD_3|SM, 0, I3, 0, I69 },
|
||||
@ -1992,8 +1995,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
||||
{"swc2", "E,+:(d)", 0x49600000, 0xffe00000, RD_3|RD_C2|SM, 0, I37, 0, 0 },
|
||||
{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, RD_3|RD_C2|SM, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE|I37 },
|
||||
{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1, 0, N54|IOCT|IOCTP|IOCT2|EE },
|
||||
{"swc3", "E,o(b)", 0xec000000, 0xfc000000, RD_3|RD_C3|SM, 0, I1, 0, I3_32|EE },
|
||||
{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1, 0, I3_32|EE },
|
||||
{"swc3", "E,o(b)", 0xec000000, 0xfc000000, RD_3|RD_C3|SM, 0, I1, 0, I3_32|EE|AL },
|
||||
{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1, 0, I3_32|EE|AL },
|
||||
{"swl", "t,o(b)", 0xa8000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, I37 },
|
||||
{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1, 0, I37 },
|
||||
{"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_1|RD_3, 0, I2, 0, I37 }, /* same */
|
||||
@ -3343,7 +3346,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
||||
{"ctc0", "t,g", 0x40c00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, I32 },
|
||||
|
||||
/* RFE conflicts with the new Virt spec instruction tlbgp. */
|
||||
{"rfe", "", 0x42000010, 0xffffffff, 0, 0, I1|T3, 0, I3_32 },
|
||||
{"rfe", "", 0x42000010, 0xffffffff, 0, 0, I1|T3, 0, I3_32|AL },
|
||||
|
||||
/* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
|
||||
instructions so they are here for the latters to take precedence. */
|
||||
@ -3390,16 +3393,16 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
||||
|
||||
/* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X
|
||||
instructions, so they are here for the latters to take precedence. */
|
||||
{"bc3f", "p", 0x4d000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, I3_33|EE },
|
||||
{"bc3fl", "p", 0x4d020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, I3_33|EE },
|
||||
{"bc3t", "p", 0x4d010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, I3_33|EE },
|
||||
{"bc3tl", "p", 0x4d030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, I3_33|EE },
|
||||
{"cfc3", "t,g", 0x4c400000, 0xffe007ff, WR_1|RD_C3|LC, 0, I1, 0, I3_33|EE },
|
||||
{"ctc3", "t,g", 0x4cc00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, I3_33|EE },
|
||||
{"mfc3", "t,G", 0x4c000000, 0xffe007ff, WR_1|RD_C3|LC, 0, I1, 0, I3_33|EE },
|
||||
{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, WR_1|RD_C3|LC, 0, I32, 0, I3_33|EE },
|
||||
{"mtc3", "t,G", 0x4c800000, 0xffe007ff, RD_1|WR_C3|WR_CC|CM, 0, I1, 0, I3_33|EE },
|
||||
{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, RD_1|WR_C3|WR_CC|CM, 0, I32, 0, I3_33|EE },
|
||||
{"bc3f", "p", 0x4d000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, I3_33|EE|AL },
|
||||
{"bc3fl", "p", 0x4d020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, I3_33|EE|AL },
|
||||
{"bc3t", "p", 0x4d010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, I3_33|EE|AL },
|
||||
{"bc3tl", "p", 0x4d030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, I3_33|EE|AL },
|
||||
{"cfc3", "t,g", 0x4c400000, 0xffe007ff, WR_1|RD_C3|LC, 0, I1, 0, I3_33|EE|AL },
|
||||
{"ctc3", "t,g", 0x4cc00000, 0xffe007ff, RD_1|WR_CC|CM, 0, I1, 0, I3_33|EE|AL },
|
||||
{"mfc3", "t,G", 0x4c000000, 0xffe007ff, WR_1|RD_C3|LC, 0, I1, 0, I3_33|EE|AL },
|
||||
{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, WR_1|RD_C3|LC, 0, I32, 0, I3_33|EE|AL },
|
||||
{"mtc3", "t,G", 0x4c800000, 0xffe007ff, RD_1|WR_C3|WR_CC|CM, 0, I1, 0, I3_33|EE|AL },
|
||||
{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, RD_1|WR_C3|WR_CC|CM, 0, I32, 0, I3_33|EE|AL },
|
||||
|
||||
/* No hazard protection on coprocessor instructions--they shouldn't
|
||||
change the state of the processor and if they do it's up to the
|
||||
|
||||
Loading…
Reference in New Issue
Block a user