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RX assembler: switch arguments of thw MVTACGU insn.

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Yoshinori Sato 2022-10-31 10:46:37 +00:00 committed by Nick Clifton
parent 18bf56434d
commit de1fbe7889
5 changed files with 21 additions and 12 deletions
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4
gas/ChangeLog
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@ -1,3 +1,7 @@
2022-10-31 Nick Clifton <nickc@redhat.com>
* testsuite/gas/rx/mvtacgu.d: Update expected disassembly.
2022-10-11 Nick Clifton <nickc@redhat.com>
* symbols.c (S_GET_VALUE): If the unresolved symbol is the fake

8
gas/testsuite/gas/rx/mvtacgu.d
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@ -7,7 +7,7 @@
Disassembly of section \.text:
00000000 <\.text>:
0: fd 17 30 mvtacgu a0, r0
3: fd 17 3f mvtacgu a0, r15
6: fd 17 b0 mvtacgu a1, r0
9: fd 17 bf mvtacgu a1, r15
0: fd 17 30 mvtacgu r0, a0
3: fd 17 3f mvtacgu r15, a0
6: fd 17 b0 mvtacgu r0, a1
9: fd 17 bf mvtacgu r15, a1

5
opcodes/ChangeLog
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@ -1,3 +1,8 @@
2022-10-31 Yoshinori Sato <ysato@users.sourceforge.jp>
* rx-decode.opc: Switch arguments of the MVTACGU insn.
* rx-decode.c: Regenerate.
2022-09-22 Yoshinori Sato <ysato@users.sourceforge.jp>
* sh-dis.c (print_insn_sh): Enforce bit7 of LDC Rm,Rn_BANK and STC

12
opcodes/rx-decode.c
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@ -12476,22 +12476,22 @@ rx_decode_opcode (unsigned long pc AU,
break;
case 0x30:
{
/** 1111 1101 0001 0111 a011 rdst mvtacgu %0, %1 */
/** 1111 1101 0001 0111 a011 rsrc mvtacgu %1, %0 */
#line 1110 "rx-decode.opc"
int a AU = (op[2] >> 7) & 0x01;
#line 1110 "rx-decode.opc"
int rdst AU = op[2] & 0x0f;
int rsrc AU = op[2] & 0x0f;
if (trace)
{
printf ("\033[33m%s\033[0m %02x %02x %02x\n",
"/** 1111 1101 0001 0111 a011 rdst mvtacgu %0, %1 */",
"/** 1111 1101 0001 0111 a011 rsrc mvtacgu %1, %0 */",
op[0], op[1], op[2]);
printf (" a = 0x%x,", a);
printf (" rdst = 0x%x\n", rdst);
printf (" rsrc = 0x%x\n", rsrc);
}
SYNTAX("mvtacgu %0, %1");
SYNTAX("mvtacgu %1, %0");
#line 1110 "rx-decode.opc"
ID(mvtacgu); DR(a+32); SR(rdst); F_____;
ID(mvtacgu); SR(rsrc); DR(a+32); F_____;
}
break;

4
opcodes/rx-decode.opc
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@ -1106,8 +1106,8 @@ rx_decode_opcode (unsigned long pc AU,
/** 1111 1101 0001 111i a m11 rdst mvfacgu #%2, %1, %0 */
ID(mvfacgu); S2C(((i^1)<<1)|m); SR(a+32); DR(rdst); F_____;
/** 1111 1101 0001 0111 a011 rdst mvtacgu %0, %1 */
ID(mvtacgu); DR(a+32); SR(rdst); F_____;
/** 1111 1101 0001 0111 a011 rsrc mvtacgu %1, %0 */
ID(mvtacgu); SR(rsrc); DR(a+32); F_____;
/** 1111 1101 0001 1001 a00i 0000 racl #%1, %0 */
ID(racl); SC(i+1); DR(a+32); F_____;