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gas/testsuite/
2008-08-28 Jan Beulich <jbeulich@novell.com>
* gas/i386/intel.s: Add retf.
* gas/i386/intel.{d,e}: Adjust.
* gas/i386/opcode-intel.d: Replace lret with retf.
opcodes/
2008-08-28 Jan Beulich <jbeulich@novell.com>
* i386-dis.c (dis386): Adjust far return mnemonics.
* i386-opc.tbl: Add retf.
* i386-tbl.h: Re-generate.
This commit is contained in:
Jan Beulich
parent
b19d538532
commit
ddab3d5917
@ -1,3 +1,9 @@
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2008-08-28 Jan Beulich <jbeulich@novell.com>
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* gas/i386/intel.s: Add retf.
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* gas/i386/intel.{d,e}: Adjust.
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* gas/i386/opcode-intel.d: Replace lret with retf.
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2008-08-28 Jan Beulich <jbeulich@novell.com>
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* gas/i386/gas/i386/opcode-suffix.d: Add suffixes to cmovXX.
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File diff suppressed because it is too large
Load Diff
@ -3,15 +3,15 @@
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.*:155: Warning: Treating `\[0x90909090\]' as memory reference
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.*:156: Warning: Treating `\[0x90909090\]' as memory reference
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.*:157: Warning: Treating `\[0x90909090\]' as memory reference
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.*:492: Warning: Treating `\[0x90909090\]' as memory reference
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.*:493: Warning: Treating `\[0x90909090\]' as memory reference
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.*:631: Warning: translating to `faddp'
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.*:640: Warning: translating to `fdivp'
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.*:649: Warning: translating to `fdivp st,st\(3\)'
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.*:650: Warning: translating to `fdivrp'
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.*:659: Warning: translating to `fdivrp st,st\(3\)'
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.*:660: Warning: translating to `fmulp'
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.*:669: Warning: translating to `fsubp'
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.*:670: Warning: translating to `fsubrp'
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.*:678: Warning: translating to `fsubp st,st\(3\)'
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.*:688: Warning: translating to `fsubrp st,st\(3\)'
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.*:494: Warning: Treating `\[0x90909090\]' as memory reference
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.*:495: Warning: Treating `\[0x90909090\]' as memory reference
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.*:635: Warning: translating to `faddp'
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.*:644: Warning: translating to `fdivp'
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.*:653: Warning: translating to `fdivp st,st\(3\)'
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.*:654: Warning: translating to `fdivrp'
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.*:663: Warning: translating to `fdivrp st,st\(3\)'
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.*:664: Warning: translating to `fmulp'
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.*:673: Warning: translating to `fsubp'
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.*:674: Warning: translating to `fsubrp'
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.*:682: Warning: translating to `fsubp st,st\(3\)'
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.*:692: Warning: translating to `fsubrp st,st\(3\)'
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@ -193,6 +193,8 @@ foo:
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mov dword ptr 0x90909090[eax], 0x90909090
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enter 0x9090, 0x90
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leave
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retf 0x9090
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retf
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lret 0x9090
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lret
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int3
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@ -513,6 +515,8 @@ foo:
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mov word ptr 0x90909090[eax], 0x9090
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enterw 0x9090, 0x90
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leavew
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retfw 0x9090
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retfw
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lretw 0x9090
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lretw
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iretw
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@ -200,8 +200,8 @@ Disassembly of section .text:
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*[0-9a-f]+: c7 80 90 90 90 90 90 90 90 90[ ]+mov[ ]+DWORD PTR \[eax-0x6f6f6f70\],0x90909090
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*[0-9a-f]+: c8 90 90 90[ ]+enter[ ]+0x9090,0x90
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*[0-9a-f]+: c9[ ]+leave[ ]*
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*[0-9a-f]+: ca 90 90[ ]+lret[ ]+0x9090
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*[0-9a-f]+: cb[ ]+lret[ ]*
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*[0-9a-f]+: ca 90 90[ ]+retf[ ]+0x9090
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*[0-9a-f]+: cb[ ]+retf[ ]*
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*[0-9a-f]+: cc[ ]+int3[ ]*
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*[0-9a-f]+: cd 90[ ]+int[ ]+0x90
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*[0-9a-f]+: ce[ ]+into[ ]*
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@ -537,9 +537,9 @@ Disassembly of section .text:
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*[0-9a-f]+: 66[ ]+data16
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*[0-9a-f]+: c9[ ]+leave[ ]*
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*[0-9a-f]+: 66[ ]+data16
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*[0-9a-f]+: ca 90 90[ ]+lret[ ]+0x9090
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*[0-9a-f]+: ca 90 90[ ]+retf[ ]+0x9090
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*[0-9a-f]+: 66[ ]+data16
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*[0-9a-f]+: cb[ ]+lret[ ]*
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*[0-9a-f]+: cb[ ]+retf[ ]*
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*[0-9a-f]+: 66[ ]+data16
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*[0-9a-f]+: cf[ ]+iret[ ]*
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*[0-9a-f]+: 66 d1 90 90 90 90 90[ ]+rcl[ ]+WORD PTR \[eax-0x6f6f6f70\],1
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@ -1,3 +1,9 @@
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2008-08-28 Jan Beulich <jbeulich@novell.com>
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* i386-dis.c (dis386): Adjust far return mnemonics.
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* i386-opc.tbl: Add retf.
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* i386-tbl.h: Re-generate.
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2008-08-28 Jan Beulich <jbeulich@novell.com>
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* i386-dis.c (dis386_twobyte): Adjust cmovXX mnemonics.
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@ -1530,8 +1530,8 @@ static const struct dis386 dis386[] = {
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/* c8 */
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{ "enterT", { Iw, Ib } },
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{ "leaveT", { XX } },
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{ "lretP", { Iw } },
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{ "lretP", { XX } },
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{ "Jret{|f}P", { Iw } },
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{ "Jret{|f}P", { XX } },
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{ "int3", { XX } },
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{ "int", { Ib } },
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{ X86_64_TABLE (X86_64_CE) },
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@ -346,6 +346,10 @@ ret, 0, 0xc3, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex
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ret, 1, 0xc2, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Imm16 }
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lret, 0, 0xcb, None, 1, 0, DefaultSize|No_bSuf|No_sSuf|No_ldSuf, { 0 }
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lret, 1, 0xca, None, 1, 0, DefaultSize|No_bSuf|No_sSuf|No_ldSuf, { Imm16 }
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// Intel Syntax.
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retf, 0, 0xcb, None, 1, 0, DefaultSize|No_bSuf|No_sSuf|No_ldSuf, { 0 }
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retf, 1, 0xca, None, 1, 0, DefaultSize|No_bSuf|No_sSuf|No_ldSuf, { Imm16 }
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enter, 2, 0xc8, None, 1, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16, Imm8 }
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enter, 2, 0xc8, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Imm16, Imm8 }
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leave, 0, 0xc9, None, 1, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
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@ -2530,6 +2530,24 @@ const template i386_optab[] =
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{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0 } } } },
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{ "retf", 0, 0xcb, None, 1,
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1,
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0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0 } } } },
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{ "retf", 1, 0xca, None, 1,
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1,
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0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0 } } } },
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{ "enter", 2, 0xc8, None, 1,
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{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
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