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Updated from specs in HDD-tool-0611 document.
This commit is contained in:
Nick Clifton
parent
aaba39af9a
commit
d87a154282
@ -1,3 +1,11 @@
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Fri Aug 22 10:35:15 1997 Nick Clifton <nickc@cygnus.com>
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* v850-dis.c (disassemble): Use curly brace syntax for register
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lists.
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* v850-opc.c (v850_opcodes[]): Add NOT_R0 flag to decect cases
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where r0 is being used as a destination register.
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start-sanitize-v850e
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Thu Aug 21 11:09:09 1997 Nick Clifton <nickc@cygnus.com>
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@ -38,54 +38,27 @@ static const char *const v850_cc_names[] =
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{ "v", "c/l", "z", "nh", "s/n", "t", "lt", "le",
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"nv", "nc/nl", "nz", "h", "ns/p", "sa", "ge", "gt" };
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int
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print_insn_v850 (memaddr, info)
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static int
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disassemble (memaddr, info, insn)
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bfd_vma memaddr;
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struct disassemble_info *info;
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{
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int status;
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bfd_byte buffer[4];
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unsigned long insn;
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/* First figure out how big the opcode is. */
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status = (*info->read_memory_func) (memaddr, buffer, 2, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return -1;
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}
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insn = bfd_getl16 (buffer);
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/* If this is a 4 byte insn, read 4 bytes of stuff. */
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if ((insn & 0x0600) == 0x0600)
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{
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status = (*info->read_memory_func) (memaddr, buffer, 2, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return -1;
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}
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insn = bfd_getl32 (buffer);
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}
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disassemble (insn, info);
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/* Make sure we tell our caller how many bytes we consumed. */
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if ((insn & 0x0600) == 0x0600)
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return 4;
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else
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return 2;
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}
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disassemble (insn, info)
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unsigned long insn;
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struct disassemble_info *info;
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{
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struct v850_opcode *op = (struct v850_opcode *)v850_opcodes;
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const struct v850_operand *operand;
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int match = 0;
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struct v850_opcode * op = (struct v850_opcode *)v850_opcodes;
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const struct v850_operand * operand;
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int match = 0;
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int short_op = ((insn & 0x0600) != 0x0600);
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int bytes_read;
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/* Special case: 32 bit MOV */
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if ((insn & 0xffe0) == 0x0620)
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short_op = true;
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bytes_read = short_op ? 2 : 4;
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/* If this is a two byte insn, then mask off the high bits. */
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if ((insn & 0x0600) != 0x0600)
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if (short_op)
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insn &= 0xffff;
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/* Find the opcode. */
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@ -93,41 +66,188 @@ disassemble (insn, info)
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{
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if ((op->mask & insn) == op->opcode)
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{
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const unsigned char *opindex_ptr;
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const unsigned char * opindex_ptr;
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unsigned int opnum;
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unsigned int memop;
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match = 1;
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(*info->fprintf_func) (info->stream, "%s\t", op->name);
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//fprintf (stderr, "match: mask: %x insn: %x, opcode: %x, name: %s\n", op->mask, insn, op->opcode, op->name );
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/* Now print the operands. */
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for (opindex_ptr = op->operands; *opindex_ptr != 0; opindex_ptr++)
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memop = op->memop;
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/* Now print the operands.
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MEMOP is the operand number at which a memory
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address specification starts, or zero if this
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instruction has no memory addresses.
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A memory address is always two arguments.
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This information allows us to determine when to
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insert commas into the output stream as well as
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when to insert disp[reg] expressions onto the
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output stream. */
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for (opindex_ptr = op->operands, opnum = 1;
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*opindex_ptr != 0;
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opindex_ptr++, opnum++)
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{
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unsigned long value;
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long value;
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int flag;
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int status;
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bfd_byte buffer[ 4 ];
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operand = &v850_operands[*opindex_ptr];
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if (operand->extract)
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value = (operand->extract) (insn, 0);
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else if (operand->bits == -1)
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value = (insn & operand->shift);
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else
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value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
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if ((operand->flags & V850_OPERAND_SIGNED) != 0)
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value = ((signed long)(value << (32 - operand->bits))
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if (operand->flags & V850_OPERAND_SIGNED)
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value = ((long)(value << (32 - operand->bits))
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>> (32 - operand->bits));
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if ((operand->flags & V850_OPERAND_REG) != 0)
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(*info->fprintf_func) (info->stream, "%s",
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v850_reg_names[value]);
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else if ((operand->flags & V850_OPERAND_SRG) != 0)
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(*info->fprintf_func) (info->stream, "%s",
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v850_sreg_names[value]);
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else if ((operand->flags & V850_OPERAND_CC) != 0)
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(*info->fprintf_func) (info->stream, "%s",
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v850_cc_names[value]);
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else if ((operand->flags & V850_OPERAND_EP) != 0)
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(*info->fprintf_func) (info->stream, "ep");
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else
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(*info->fprintf_func) (info->stream, "%d", value);
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/* The first operand is always output without any
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special handling.
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For the following arguments:
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If memop && opnum == memop + 1, then we need '[' since
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we're about to output the register used in a memory
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reference.
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If memop && opnum == memop + 2, then we need ']' since
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we just finished the register in a memory reference. We
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also need a ',' before this operand.
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Else we just need a comma.
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We may need to output a trailing ']' if the last operand
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in an instruction is the register for a memory address.
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The exception (and there's always an exception) is the
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"jmp" insn which needs square brackets around it's only
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register argument. */
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if (memop && opnum == memop + 1) info->fprintf_func (info->stream, "[");
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else if (memop && opnum == memop + 2) info->fprintf_func (info->stream, "],");
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else if (memop == 1 && opnum == 1
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&& (operand->flags & V850_OPERAND_REG))
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info->fprintf_func (info->stream, "[");
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else if (opnum > 1) info->fprintf_func (info->stream, ", ");
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/* extract the flags, ignorng ones which do not effect disassembly output. */
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flag = operand->flags;
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flag &= ~ V850_OPERAND_SIGNED;
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flag &= ~ V850_OPERAND_RELAX;
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flag &= ~ V850_OPERAND_ADJUST_SHORT_MEMORY;
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flag &= - flag;
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switch (flag)
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{
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case V850_OPERAND_REG: info->fprintf_func (info->stream, "%s", v850_reg_names[value]); break;
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case V850_OPERAND_SRG: info->fprintf_func (info->stream, "%s", v850_sreg_names[value]); break;
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case V850_OPERAND_CC: info->fprintf_func (info->stream, "%s", v850_cc_names[value]); break;
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case V850_OPERAND_EP: info->fprintf_func (info->stream, "ep"); break;
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case V850_OPERAND_DISP: info->print_address_func (value + memaddr, info); break;
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default: info->fprintf_func (info->stream, "%d", value); break;
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/* start-sanitize-v850e */
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case V850E_PUSH_POP:
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{
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static int list12_regs[32] = { 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24 };
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/* start-sanitize-v850eq */
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static int list18_h_regs[32] = { 19, 18, 17, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1, 30, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24 };
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static int list18_l_regs[32] = { 3, 2, 1, -2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1, 14, 15, 13, 12, 7, 6, 5, 4, 11, 10, 9, 8 };
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/* end-sanitize-v850eq */
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int * regs;
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int i;
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int shown_one = false;
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switch (operand->shift)
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{
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case 0xffe00001: regs = list12_regs; break;
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/* start-sanitize-v850eq */
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case 0xfff8000f: regs = list18_h_regs; break;
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case 0xfff8001f: regs = list18_l_regs; value &= ~0x10; break; /* Do not include magic bit */
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/* end-sanitize-v850eq */
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default:
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fprintf (stderr, "unknown operand shift: %x\n", operand->shift );
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abort();
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}
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info->fprintf_func (info->stream, "{");
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for (i = 0; i < 32; i++)
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{
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if (value & (1 << i))
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{
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if (shown_one)
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info->fprintf_func (info->stream, ",");
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else
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shown_one = true;
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switch (regs[ i ])
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{
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default: info->fprintf_func (info->stream, "%s", v850_reg_names[regs[ i ]]); break;
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/* start-sanitize-v850eq */
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case 0: fprintf (stderr, "unknown pop reg: %d\n", i ); abort();
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case -1: info->fprintf_func (info->stream, "PC "); break;
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case -2: info->fprintf_func (info->stream, "SR"); break;
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/* end-sanitize-v850eq */
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}
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}
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}
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info->fprintf_func (info->stream, "}");
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}
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break;
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case V850E_IMMEDIATE16:
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status = info->read_memory_func (memaddr + bytes_read, buffer, 2, info);
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if (status == 0)
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{
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bytes_read += 2;
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value = bfd_getl16 (buffer);
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/* If this is a DISPOSE instruction with ff set to 0x10, then shift value up by 16. */
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if ((insn & 0x001fffc0) == 0x00130780)
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value <<= 16;
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info->fprintf_func (info->stream, "0x%x", value);
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}
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else
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{
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info->memory_error_func (status, memaddr + bytes_read, info);
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}
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break;
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case V850E_IMMEDIATE32:
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status = info->read_memory_func (memaddr + bytes_read, buffer, 4, info);
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if (status == 0)
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{
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bytes_read += 4;
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value = bfd_getl32 (buffer);
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info->fprintf_func (info->stream, "0x%lx", value);
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}
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else
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{
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info->memory_error_func (status, memaddr + bytes_read, info);
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}
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break;
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/* end-sanitize-v850e */
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}
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/* Handle jmp correctly. */
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if (memop == 1 && opnum == 1
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&& ((operand->flags & V850_OPERAND_REG) != 0))
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(*info->fprintf_func) (info->stream, "]");
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}
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/* Close any square bracket we left open. */
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if (memop && opnum == memop + 2)
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(*info->fprintf_func) (info->stream, "]");
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/* All done. */
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break;
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}
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@ -136,9 +256,50 @@ disassemble (insn, info)
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if (!match)
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{
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if ((insn & 0x0600) != 0x0600)
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(*info->fprintf_func) (info->stream, ".short\t0x%04x", insn);
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if (short_op)
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info->fprintf_func (info->stream, ".short\t0x%04x", insn);
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else
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(*info->fprintf_func) (info->stream, ".long\t0x%08x", insn);
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info->fprintf_func (info->stream, ".long\t0x%08x", insn);
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}
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return bytes_read;
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}
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int
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print_insn_v850 (memaddr, info)
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bfd_vma memaddr;
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struct disassemble_info * info;
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{
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int status;
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bfd_byte buffer[ 4 ];
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unsigned long insn;
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/* First figure out how big the opcode is. */
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status = info->read_memory_func (memaddr, buffer, 2, info);
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if (status == 0)
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{
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insn = bfd_getl16 (buffer);
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if ( (insn & 0x0600) == 0x0600
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&& (insn & 0xffe0) != 0x0620)
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{
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/* If this is a 4 byte insn, read 4 bytes of stuff. */
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status = info->read_memory_func (memaddr, buffer, 4, info);
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if (status == 0)
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insn = bfd_getl32 (buffer);
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}
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}
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if (status != 0)
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{
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info->memory_error_func (status, memaddr, info);
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return -1;
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}
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/* Make sure we tell our caller how many bytes we consumed. */
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return disassemble (memaddr, info, insn);
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}
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@ -335,7 +335,8 @@ extract_i5div (insn, invalid)
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/* end-sanitize-v850eq */
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const struct v850_operand v850_operands[] = {
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const struct v850_operand v850_operands[] =
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{
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#define UNUSED 0
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{ 0, 0, 0, 0, 0 },
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@ -343,12 +344,20 @@ const struct v850_operand v850_operands[] = {
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#define R1 (UNUSED+1)
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{ 5, 0, 0, 0, V850_OPERAND_REG },
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/* The R1 field in a format 1, 6, 7, or 9 insn. */
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#define R1_NOTR0 (R1 + 1)
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{ 5, 0, 0, 0, V850_OPERAND_REG | V850_NOT_R0 },
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/* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */
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#define R2 (R1+1)
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#define R2 (R1_NOTR0 + 1)
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{ 5, 11, 0, 0, V850_OPERAND_REG },
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/* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */
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#define R2_NOTR0 (R2 + 1)
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{ 5, 11, 0, 0, V850_OPERAND_REG | V850_NOT_R0 },
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/* The IMM5 field in a format 2 insn. */
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#define I5 (R2+1)
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#define I5 (R2_NOTR0 + 1)
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{ 5, 0, 0, 0, V850_OPERAND_SIGNED },
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#define I5U (I5+1)
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@ -465,7 +474,7 @@ const struct v850_operand v850_operands[] = {
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/* Reg2 in dispose instruction. */
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#define R2DISPOSE (IMM5 + 1)
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{ 5, 16, 0, 0, V850_OPERAND_REG },
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{ 5, 16, 0, 0, V850_OPERAND_REG | V850_NOT_R0 },
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/* Stack pointer in prepare instruction. */
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#define SP (R2DISPOSE + 1)
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@ -533,15 +542,15 @@ const struct v850_opcode v850_opcodes[] =
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/* load/store instructions */
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#ifdef ARCH_v850eq
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{ "sld.bu", one (0x0300), one (0x0780), {D7, EP, R2}, 1 },
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{ "sld.hu", one (0x0400), one (0x0780), {D8_7, EP, R2}, 1 },
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{ "sld.bu", one (0x0300), one (0x0780), {D7, EP, R2_NOTR0}, 1 },
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{ "sld.hu", one (0x0400), one (0x0780), {D8_7, EP, R2_NOTR0}, 1 },
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{ "sld.b", one (0x0060), one (0x07f0), {D4, EP, R2}, 1 },
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{ "sld.h", one (0x0070), one (0x07f0), {D5_4, EP, R2}, 1 },
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#else
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{ "sld.b", one (0x0300), one (0x0780), {D7, EP, R2}, 1 },
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{ "sld.h", one (0x0400), one (0x0780), {D8_7, EP, R2}, 1 },
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{ "sld.bu", one (0x0060), one (0x07f0), {D4, EP, R2}, 1 },
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{ "sld.hu", one (0x0070), one (0x07f0), {D5_4, EP, R2}, 1 },
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{ "sld.bu", one (0x0060), one (0x07f0), {D4, EP, R2_NOTR0}, 1 },
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{ "sld.hu", one (0x0070), one (0x07f0), {D5_4, EP, R2_NOTR0}, 1 },
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#endif
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{ "sld.w", one (0x0500), one (0x0781), {D8_6, EP, R2}, 1 },
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{ "sst.b", one (0x0380), one (0x0780), {R2, D7, EP}, 2 },
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@ -569,8 +578,8 @@ const struct v850_opcode v850_opcodes[] =
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{ "ld.h", two (0x0720, 0x0000), two (0x07e0, 0x0001), {D16_15, R1, R2}, 1 },
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{ "ld.w", two (0x0720, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2}, 1 },
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/* start-sanitize-v850e */
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{ "ld.bu", two (0x0780, 0x0001), two (0x07c0, 0x0001), {D16_16, R1, R2}, 1 },
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{ "ld.hu", two (0x07e0, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2}, 1 },
|
||||
{ "ld.bu", two (0x0780, 0x0001), two (0x07c0, 0x0001), {D16_16, R1, R2_NOTR0}, 1 },
|
||||
{ "ld.hu", two (0x07e0, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2_NOTR0}, 1 },
|
||||
/* end-sanitize-v850e */
|
||||
{ "st.b", two (0x0740, 0x0000), two (0x07e0, 0x0000), {R2, D16, R1}, 2 },
|
||||
{ "st.h", two (0x0760, 0x0000), two (0x07e0, 0x0001), {R2, D16_15, R1}, 2 },
|
||||
@ -578,10 +587,10 @@ const struct v850_opcode v850_opcodes[] =
|
||||
|
||||
/* start-sanitize-v850e */
|
||||
/* byte swap/extend instructions */
|
||||
{ "zxb", one (0x0080), one (0xffe0), {R1}, 0 },
|
||||
{ "zxh", one (0x00c0), one (0xffe0), {R1}, 0 },
|
||||
{ "sxb", one (0x00a0), one (0xffe0), {R1}, 0 },
|
||||
{ "sxh", one (0x00e0), one (0xffe0), {R1}, 0 },
|
||||
{ "zxb", one (0x0080), one (0xffe0), {R1_NOTR0}, 0 },
|
||||
{ "zxh", one (0x00c0), one (0xffe0), {R1_NOTR0}, 0 },
|
||||
{ "sxb", one (0x00a0), one (0xffe0), {R1_NOTR0}, 0 },
|
||||
{ "sxh", one (0x00e0), one (0xffe0), {R1_NOTR0}, 0 },
|
||||
{ "bsh", two (0x07e0, 0x0342), two (0x07ff, 0x07ff), {R2, R3}, 0 },
|
||||
{ "bsw", two (0x07e0, 0x0340), two (0x07ff, 0x07ff), {R2, R3}, 0 },
|
||||
{ "hsw", two (0x07e0, 0x0344), two (0x07ff, 0x07ff), {R2, R3}, 0 },
|
||||
@ -611,7 +620,7 @@ const struct v850_opcode v850_opcodes[] =
|
||||
{ "divhu", two (0x07e0, 0x0282), two (0x07e0, 0x07ff), {R1, R2, R3}, 0 },
|
||||
{ "divh", two (0x07e0, 0x0280), two (0x07e0, 0x07ff), {R1, R2, R3}, 0 },
|
||||
/* end-sanitize-v850e */
|
||||
{ "divh", OP (0x02), OP_MASK, IF1, 0 },
|
||||
{ "divh", OP (0x02), OP_MASK, {R1, R2_NOTR0}, 0 },
|
||||
|
||||
/* start-sanitize-v850eq */
|
||||
{ "divhn", two (0x07e0, 0x0280), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0 },
|
||||
@ -625,30 +634,30 @@ const struct v850_opcode v850_opcodes[] =
|
||||
/* end-sanitize-v850eq */
|
||||
|
||||
{ "nop", one (0x00), one (0xffff), {0}, 0 },
|
||||
{ "mov", OP (0x00), OP_MASK, IF1, 0 },
|
||||
{ "mov", OP (0x10), OP_MASK, IF2, 0 },
|
||||
{ "mov", OP (0x10), OP_MASK, {I5, R2_NOTR0}, 0 },
|
||||
/* start-sanitize-v850e */
|
||||
{ "mov", one (0x0620), one (0xffe0), {IMM32, R1}, 0 },
|
||||
{ "mov", one (0x0620), one (0xffe0), {IMM32, R1_NOTR0}, 0 },
|
||||
/* end-sanitize-v850e */
|
||||
{ "movea", OP (0x31), OP_MASK, IF6, 0 },
|
||||
{ "movhi", OP (0x32), OP_MASK, IF6, 0 },
|
||||
{ "mov", OP (0x00), OP_MASK, {R1, R2_NOTR0}, 0 },
|
||||
{ "movea", OP (0x31), OP_MASK, {I16, R1, R2_NOTR0}, 0 },
|
||||
{ "movhi", OP (0x32), OP_MASK, {I16, R1, R2_NOTR0}, 0 },
|
||||
{ "add", OP (0x0e), OP_MASK, IF1, 0 },
|
||||
{ "add", OP (0x12), OP_MASK, IF2, 0 },
|
||||
{ "addi", OP (0x30), OP_MASK, IF6, 0 },
|
||||
{ "sub", OP (0x0d), OP_MASK, IF1, 0 },
|
||||
{ "subr", OP (0x0c), OP_MASK, IF1, 0 },
|
||||
{ "mulh", OP (0x07), OP_MASK, IF1, 0 },
|
||||
{ "mulh", OP (0x17), OP_MASK, IF2, 0 },
|
||||
{ "mulhi", OP (0x37), OP_MASK, IF6, 0 },
|
||||
{ "mulh", OP (0x17), OP_MASK, {I5, R2_NOTR0}, 0 },
|
||||
{ "mulh", OP (0x07), OP_MASK, {R1, R2_NOTR0}, 0 },
|
||||
{ "mulhi", OP (0x37), OP_MASK, {I16, R1, R2_NOTR0}, 0 },
|
||||
{ "cmp", OP (0x0f), OP_MASK, IF1, 0 },
|
||||
{ "cmp", OP (0x13), OP_MASK, IF2, 0 },
|
||||
|
||||
/* saturated operation instructions */
|
||||
{ "satadd", OP (0x06), OP_MASK, IF1, 0 },
|
||||
{ "satadd", OP (0x11), OP_MASK, IF2, 0 },
|
||||
{ "satsub", OP (0x05), OP_MASK, IF1, 0 },
|
||||
{ "satsubi", OP (0x33), OP_MASK, IF6, 0 },
|
||||
{ "satsubr", OP (0x04), OP_MASK, IF1, 0 },
|
||||
{ "satadd", OP (0x11), OP_MASK, {I5, R2_NOTR0}, 0 },
|
||||
{ "satadd", OP (0x06), OP_MASK, {R1, R2_NOTR0}, 0 },
|
||||
{ "satsub", OP (0x05), OP_MASK, {R1, R2_NOTR0}, 0 },
|
||||
{ "satsubi", OP (0x33), OP_MASK, {I16, R1, R2_NOTR0}, 0 },
|
||||
{ "satsubr", OP (0x04), OP_MASK, {R1, R2_NOTR0}, 0 },
|
||||
|
||||
/* logical operation instructions */
|
||||
{ "tst", OP (0x0b), OP_MASK, IF1, 0 },
|
||||
|
||||
Loading…
Reference in New Issue
Block a user