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* m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended

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when loaded into XR registers.
This commit is contained in:
Alexandre Oliva 2004-01-16 03:16:00 +00:00
parent ceef1284d2
commit d164ea7f0f
2 changed files with 8 additions and 3 deletions
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5
opcodes/ChangeLog
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@ -1,3 +1,8 @@
2004-01-16 Alexandre Oliva <aoliva@redhat.com>
* m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
when loaded into XR registers.
2004-01-14 Richard Sandiford <rsandifo@redhat.com>
* frv-desc.h: Regenerate.

6
opcodes/m10300-opc.c
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@ -1,5 +1,5 @@
/* Assemble Matsushita MN10300 instructions.
Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
Copyright 1996, 1997, 1998, 1999, 2000, 2004 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@ -561,8 +561,8 @@ const struct mn10300_opcode mn10300_opcodes[] = {
{ "mov", 0xfb080000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, RN02}},
{ "mov", 0xfd080000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, RN02}},
{ "mov", 0xfe080000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, RN02}},
{ "mov", 0xfbf80000, 0xffff0000, 0, FMT_D7, AM33, {SIMM8, XRN02}},
{ "mov", 0xfdf80000, 0xffff0000, 0, FMT_D8, AM33, {SIMM24, XRN02}},
{ "mov", 0xfbf80000, 0xffff0000, 0, FMT_D7, AM33, {IMM8, XRN02}},
{ "mov", 0xfdf80000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, XRN02}},
{ "mov", 0xfef80000, 0xffff0000, 0, FMT_D9, AM33, {IMM32_HIGH8, XRN02}},
{ "mov", 0xfe0e0000, 0xffff0f00, 0, FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM), RN2}},
{ "mov", 0xfe1e0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM(IMM32_HIGH8_MEM)}},