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CSKY: Add ck803r2 series cpu.
gas/
* config/tc-csky.c (CSKY_ISA_803R2): New.
(csky_archs): Add ck803r2 series.
(md_begin): Fix warning about -medsp.
(csky_get_freg_val): Support lowercase of fpu register name.
* testsuite/gas/csky/cskyv2_ck803r2.s: New file.
* testsuite/gas/csky/cskyv2_ck803r2.d: New file.
include/
* csky.h (CSKYV2_ISA_3E3R2): New.
opcodes/
* csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
This commit is contained in:
Cooper Qu
Lifang Xia
parent
b9e188dc8b
commit
d04aee0f41
@ -1,3 +1,12 @@
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2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
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* config/tc-csky.c (CSKY_ISA_803R2): New.
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(csky_archs): Add ck803r2 series.
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(md_begin): Fix warning about -medsp.
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(csky_get_freg_val): Support lowercase of fpu register name.
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* testsuite/gas/csky/cskyv2_ck803r2.s: New file.
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* testsuite/gas/csky/cskyv2_ck803r2.d: New file.
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2020-08-23 Alan Modra <amodra@gmail.com>
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PR 26513
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@ -604,6 +604,7 @@ const struct csky_cpu_info csky_cpus[] =
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/* CK803 series. */
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#define CSKY_ISA_803 (CSKY_ISA_802 | CSKYV2_ISA_2E3 | CSKY_ISA_MP)
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#define CSKY_ISA_803R1 (CSKY_ISA_803 | CSKYV2_ISA_3E3R1)
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#define CSKY_ISA_803R2 (CSKY_ISA_803 | CSKYV2_ISA_3E3R1 | CSKYV2_ISA_3E3R2)
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#define CSKY_ISA_FLOAT_803 (CSKY_ISA_FLOAT_E1 | CSKY_ISA_FLOAT_1E3)
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{"ck803", CSKY_ARCH_803, CSKY_ISA_803 },
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{"ck803h", CSKY_ARCH_803, CSKY_ISA_803 },
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@ -636,6 +637,22 @@ const struct csky_cpu_info csky_cpus[] =
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{"ck803eftr1", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
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{"ck803ehftr1", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
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{"ck803r2", CSKY_ARCH_803, CSKY_ISA_803R2},
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{"ck803hr2", CSKY_ARCH_803, CSKY_ISA_803R2},
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{"ck803tr2", CSKY_ARCH_803, CSKY_ISA_803R2 | CSKY_ISA_TRUST},
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{"ck803htr2", CSKY_ARCH_803, CSKY_ISA_803R2 | CSKY_ISA_TRUST},
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{"ck803fr2", CSKY_ARCH_803 | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_FLOAT_803},
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{"ck803fhr2", CSKY_ARCH_803 | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_FLOAT_803},
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{"ck803er2", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE},
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{"ck803ehr2", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE},
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{"ck803etr2", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_TRUST},
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{"ck803ehtr2", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_TRUST},
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{"ck803efr2", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803},
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{"ck803efhr2", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803},
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{"ck803ftr2", CSKY_ARCH_803 | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
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{"ck803eftr2", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
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{"ck803efhtr2", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R2 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST},
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{"ck803s", CSKY_ARCH_803, CSKY_ISA_803R1 },
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{"ck803se", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R1 | CSKYV2_ISA_DSP},
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{"ck803sj", CSKY_ARCH_803 | CSKY_ARCH_JAVA, CSKY_ISA_803R1 | CSKY_ISA_JAVA},
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@ -1250,16 +1267,34 @@ md_begin (void)
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{
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if (IS_CSKY_ARCH_803 (mach_flag))
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{
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/* In 803, dspv1 is conflict with dspv2. We keep dspv2. */
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if ((dsp_flag & CSKY_DSP_FLAG_V1) && (dsp_flag & CSKY_DSP_FLAG_V2))
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as_warn (_("option -mdsp conflicts with -medsp, only enabling -medsp"));
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isa_flag &= ~(CSKY_ISA_MAC_DSP | CSKY_ISA_DSP);
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isa_flag |= CSKY_ISA_DSP_ENHANCE;
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if ((dsp_flag & CSKY_DSP_FLAG_V1))
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{
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isa_flag |= (CSKY_ISA_MAC_DSP | CSKY_ISA_DSP);
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isa_flag &= ~CSKY_ISA_DSP_ENHANCE;
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}
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if ((dsp_flag & CSKY_DSP_FLAG_V2))
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{
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isa_flag &= ~(CSKY_ISA_MAC_DSP | CSKY_ISA_DSP);
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isa_flag |= CSKY_ISA_DSP_ENHANCE;
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}
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if ((dsp_flag & CSKY_DSP_FLAG_V1)
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&& (dsp_flag & CSKY_DSP_FLAG_V2))
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{
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/* In 803, dspv1 is conflict with dspv2. We keep dspv2. */
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as_warn ("option -mdsp conflicts with -medsp, only enabling -medsp");
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isa_flag &= ~(CSKY_ISA_MAC_DSP | CSKY_ISA_DSP);
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isa_flag |= CSKY_ISA_DSP_ENHANCE;
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}
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}
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else
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{
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isa_flag &= ~CSKY_ISA_DSP_ENHANCE;
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as_warn (_("-medsp option is only supported by ck803s, ignoring -medsp"));
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if (dsp_flag & CSKY_DSP_FLAG_V2)
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{
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isa_flag &= ~CSKY_ISA_DSP_ENHANCE;
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as_warn ("-medsp option is only supported by ck803s, ignoring -medsp");
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}
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}
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;
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}
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@ -2330,7 +2365,8 @@ csky_get_freg_val (char *str, int *len)
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{
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int reg = 0;
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char *s = NULL;
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if ((str[0] == 'v' || str[0] == 'f') && (str[1] == 'r'))
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if ((TOLOWER(str[0]) == 'v' || TOLOWER(str[0]) == 'f')
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&& (TOLOWER(str[1]) == 'r'))
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{
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/* It is fpu register. */
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s = &str[2];
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12
gas/testsuite/gas/csky/cskyv2_ck803r2.d
Normal file
12
gas/testsuite/gas/csky/cskyv2_ck803r2.d
Normal file
@ -0,0 +1,12 @@
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# name: csky - ck803r2
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#as: -mcpu=ck803r2
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#objdump: -D
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.*: +file format .*csky.*
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Disassembly of section \.text:
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#...
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\s*[0-9a-f]*:\s*e8200002\s*bnezad\s*r0, 0x4.*
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#...
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\s*[0-9a-f]*:\s*6c03\s*mov\s*r0,\s*r0
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\s*[0-9a-f]*:\s*e820fffd\s*bnezad\s*r0,\s*0.*
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6
gas/testsuite/gas/csky/cskyv2_ck803r2.s
Normal file
6
gas/testsuite/gas/csky/cskyv2_ck803r2.s
Normal file
@ -0,0 +1,6 @@
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ck803r2:
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bnezad r0, hello
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hello:
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nop
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bnezad r0, ck803r2
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@ -1,3 +1,7 @@
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2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
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* csky.h (CSKYV2_ISA_3E3R2): New.
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2020-08-21 Mark Wielaard <mark@klomp.org>
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* diagnostics.h (DIAGNOSTIC_IGNORE_DEPRECATED_REGISTER): Also define
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@ -29,6 +29,7 @@
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#define CSKYV2_ISA_3E7 (1 << 4)
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#define CSKYV2_ISA_7E10 (1 << 5)
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#define CSKYV2_ISA_3E3R1 (1 << 6)
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#define CSKYV2_ISA_3E3R2 (1 << 7)
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#define CSKY_ISA_TRUST (1 << 11)
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#define CSKY_ISA_CACHE (1 << 12)
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@ -1,3 +1,7 @@
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2020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
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* csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
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2020-08-21 Nick Clifton <nickc@redhat.com>
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* aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
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@ -4565,12 +4565,19 @@ const struct csky_opcode csky_v2_opcodes[] =
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OPCODE_INFO1 (0xe8400000,
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(0_15, COND16b, OPRND_SHIFT_1_BIT)),
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CSKYV2_ISA_1E2),
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#undef _RELAX
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#undef _RELOC16
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#define _RELAX 0
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#define _RELOC16 0
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OP32 ("bnezad",
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OPCODE_INFO2 (0xe8200000,
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(16_20, AREG, OPRND_SHIFT_0_BIT),
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(0_15, COND16b, OPRND_SHIFT_1_BIT)),
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CSKYV2_ISA_3E3R2),
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#undef _RELOC16
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#undef _RELOC32
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#undef _RELAX
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#define _RELOC16 0
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#define _RELOC32 0
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#define _RELAX 0
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#undef _TRANSFER
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#define _TRANSFER 1
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OP16_WITH_WORK ("jbr",
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