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RISC-V: Relax "fmv.[sdq]" requirements

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This commit relaxes requirements to "fmv.s" instructions from 'F' to ('F'
or 'Zfinx').  The same applies to "fmv.d" and "fmv.q".  Note that 'Zhinx'
extension already contains "fmv.h" instruction (as well as 'Zfh').

gas/ChangeLog:

	* testsuite/gas/riscv/zfinx.s: Add "fmv.s" instruction.
	* testsuite/gas/riscv/zfinx.d: Likewise.
	* testsuite/gas/riscv/zdinx.s: Add "fmv.d" instruction.
	* testsuite/gas/riscv/zdinx.d: Likewise.
	* testsuite/gas/riscv/zqinx.d: Add "fmv.q" instruction.
	* testsuite/gas/riscv/zqinx.s: Likewise.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Relax requirements to "fmv.[sdq]"
	instructions to support those in 'Zfinx'/'Zdinx'/'Zqinx'.
This commit is contained in:
Tsukasa OI 2022-02-01 19:00:00 +09:00
parent 38cb335c76
commit cfc0ffd31e
7 changed files with 9 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
gas/testsuite/gas/riscv/zdinx.d
View File

@ -51,6 +51,7 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+a2c58553[ ]+fle.d[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+a2b61553[ ]+flt.d[ ]+a0,a2,a1
[ ]+[0-9a-f]+:[ ]+a2b60553[ ]+fle.d[ ]+a0,a2,a1
[ ]+[0-9a-f]+:[ ]+22b58553[ ]+fmv.d[ ]+a0,a1
[ ]+[0-9a-f]+:[ ]+22b59553[ ]+fneg.d[ ]+a0,a1
[ ]+[0-9a-f]+:[ ]+22b5a553[ ]+fabs.d[ ]+a0,a1
[ ]+[0-9a-f]+:[ ]+e2059553[ ]+fclass.d[ ]+a0,a1

1
gas/testsuite/gas/riscv/zdinx.s
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@ -47,6 +47,7 @@ target:
fle.d a0, a1, a2
fgt.d a0, a1, a2
fge.d a0, a1, a2
fmv.d a0, a1
fneg.d a0, a1
fabs.d a0, a1
fclass.d a0, a1

1
gas/testsuite/gas/riscv/zfinx.d
View File

@ -50,6 +50,7 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+a0c58553[ ]+fle.s[ ]+a0,a1,a2
[ ]+[0-9a-f]+:[ ]+a0b61553[ ]+flt.s[ ]+a0,a2,a1
[ ]+[0-9a-f]+:[ ]+a0b60553[ ]+fle.s[ ]+a0,a2,a1
[ ]+[0-9a-f]+:[ ]+20b58553[ ]+fmv.s[ ]+a0,a1
[ ]+[0-9a-f]+:[ ]+20b59553[ ]+fneg.s[ ]+a0,a1
[ ]+[0-9a-f]+:[ ]+20b5a553[ ]+fabs.s[ ]+a0,a1
[ ]+[0-9a-f]+:[ ]+e0059553[ ]+fclass.s[ ]+a0,a1

1
gas/testsuite/gas/riscv/zfinx.s
View File

@ -45,6 +45,7 @@ target:
fle.s a0, a1, a2
fgt.s a0, a1, a2
fge.s a0, a1, a2
fmv.s a0, a1
fneg.s a0, a1
fabs.s a0, a1
fclass.s a0, a1

1
gas/testsuite/gas/riscv/zqinx.d
View File

@ -52,6 +52,7 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+a6e60553[ ]+fle.q[ ]+a0,a2,a4
[ ]+[0-9a-f]+:[ ]+a6c71553[ ]+flt.q[ ]+a0,a4,a2
[ ]+[0-9a-f]+:[ ]+a6c70553[ ]+fle.q[ ]+a0,a4,a2
[ ]+[0-9a-f]+:[ ]+26c60553[ ]+fmv.q[ ]+a0,a2
[ ]+[0-9a-f]+:[ ]+26c61553[ ]+fneg.q[ ]+a0,a2
[ ]+[0-9a-f]+:[ ]+26c62553[ ]+fabs.q[ ]+a0,a2
[ ]+[0-9a-f]+:[ ]+e6061553[ ]+fclass.q[ ]+a0,a2

1
gas/testsuite/gas/riscv/zqinx.s
View File

@ -48,6 +48,7 @@ target:
fle.q a0, a2, a4
fgt.q a0, a2, a4
fge.q a0, a2, a4
fmv.q a0, a2
fneg.q a0, a2
fabs.q a0, a2
fclass.q a0, a2

6
opcodes/riscv-opc.c
View File

@ -695,7 +695,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"fmv.w.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 },
{"fmv.x.s", 0, INSN_CLASS_F, "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 },
{"fmv.s.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 },
{"fmv.s", 0, INSN_CLASS_F, "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS },
{"fmv.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS },
{"fneg.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS },
{"fabs.s", 0, INSN_CLASS_F_OR_ZFINX, "D,U", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS },
{"fsgnj.s", 0, INSN_CLASS_F_OR_ZFINX, "D,S,T", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 },
@ -753,7 +753,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"fsd", 0, INSN_CLASS_D_AND_C, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
{"fsd", 0, INSN_CLASS_D, "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE },
{"fsd", 0, INSN_CLASS_D, "T,A,s", 0, (int) M_FSD, match_never, INSN_MACRO },
{"fmv.d", 0, INSN_CLASS_D, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS },
{"fmv.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS },
{"fneg.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS },
{"fabs.d", 0, INSN_CLASS_D_OR_ZDINX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS },
{"fsgnj.d", 0, INSN_CLASS_D_OR_ZDINX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 },
@ -810,7 +810,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"flq", 0, INSN_CLASS_Q, "D,A,s", 0, (int) M_FLQ, match_never, INSN_MACRO },
{"fsq", 0, INSN_CLASS_Q, "T,q(s)", MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE },
{"fsq", 0, INSN_CLASS_Q, "T,A,s", 0, (int) M_FSQ, match_never, INSN_MACRO },
{"fmv.q", 0, INSN_CLASS_Q, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS },
{"fmv.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS },
{"fneg.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS },
{"fabs.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS },
{"fsgnj.q", 0, INSN_CLASS_Q_OR_ZQINX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 },