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* mn10300-opc.c (mn10300_opcodes): Start fleshing out the
opcode table. Checkpointint 10300 work.
This commit is contained in:
Jeff Law
parent
afb8f218ab
commit
cd8a9026b9
@ -1,7 +1,7 @@
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Thu Oct 3 17:17:02 1996 Ian Lance Taylor <ian@cygnus.com>
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* Makefile.in (ALL_MACHINES): Add mn10200-dis.o, mn10200-opc.o,
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mn10300-dis.o, and mn10300-opc.o.
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* mn10300-opc.c (mn10300_opcodes): Start fleshing out the
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opcode table.
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Thu Oct 3 10:06:07 1996 Jeffrey A Law (law@cygnus.com)
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@ -42,8 +42,257 @@ const struct mn10300_operand mn10300_operands[] = {
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specific instructions before more general instructions. It is also
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sorted by major opcode. */
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#define S0 0
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#define S1 0
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#define D0 0
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#define D1 0
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#define D2 0
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#define D4 0
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#define D5 0
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#define S2 0
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#define S4 0
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#define S6 0
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#define DN 0
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#define DM 0
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#define AN 0
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#define AM 0
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#define IMM8 0
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#define IMM16 0
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#define IMM32 0
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#define D8 0
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#define D16 0
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#define UIMM8 0
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#define SP 0
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#define PSW 0
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#define D32 0
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#define MDR 0
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#define ABS16 0
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#define ABS32 0
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#define DI 0
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#define REGS 0
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const struct mn10300_opcode mn10300_opcodes[] = {
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{ 0, 0, 0, {0}, } } ;
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{ "mov", 0x8000, 0xf000, {S1, IMM8, DN}, },
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{ "mov", 0x80, 0xf0, {S0, DM, DN}, },
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{ "mov", 0xf1d0, 0xfff0, {D0, AM, DN}, },
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{ "mov", 0x9000, 0xf000, {S1, IMM8, AN}, },
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{ "mov", 0x90, 0xf0, {S0, AM, AN}, },
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{ "mov", 0x3c, 0xfc, {S0, SP, AN}, },
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{ "mov", 0xf2f0, 0xfff3, {D0, AM, SP}, },
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{ "mov", 0xf2e4, 0xfffc, {D0, PSW, DN}, },
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{ "mov", 0xf2f3, 0xfff3, {D0, DM, PSW}, },
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{ "mov", 0xf2e0, 0xfffc, {D0, MDR, DN}, },
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{ "mov", 0xf2f2, 0xfff3, {D0, DM, MDR}, },
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{ "mov", 0x70, 0xf0, {S0, AM, DN}, },
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{ "mov", 0xf80000, 0xfff000, {D1, D8, AM, DN}, },
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{ "mov", 0xfa000000, 0xfff00000, {D2, D16, AM, DN}, },
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{ "mov", 0xfc000000, 0xfff00000, {D4, D32, AM, DN}, },
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{ "mov", 0x5800, 0xfc00, {S1, IMM8, SP, DN}, },
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{ "mov", 0xfab40000, 0xfffc0000, {D2, D16, SP, DN}, },
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{ "mov", 0xfcb40000, 0xfffc0000, {D4, D32, SP, DN}, },
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{ "mov", 0xf300, 0xffc0, {D0, DI, AM, DN}, },
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{ "mov", 0x300000, 0xfc0000, {S2, ABS16, DN}, },
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{ "mov", 0xfca40000, 0xfffc0000, {D4, ABS32, DN}, },
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{ "mov", 0x0, 0x0, {D0, AM, AN}, },
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{ "mov", 0x0, 0x0, {D1, D8, AM, AN}, },
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{ "mov", 0x0, 0x0, {D2, D16, AM, AN}, },
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{ "mov", 0x0, 0x0, {D4, D32, AM, AN}, },
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{ "mov", 0x0, 0x0, {S1, D8, SP, AN}, },
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{ "mov", 0x0, 0x0, {D2, D16, SP, AN}, },
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{ "mov", 0x0, 0x0, {D4, D32, SP, AN}, },
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{ "mov", 0x0, 0x0, {D0, DI, AM, AN}, },
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{ "mov", 0x0, 0x0, {D2, ABS16, DN}, },
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{ "mov", 0x0, 0x0, {D4, ABS32, DN}, },
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{ "mov", 0x0, 0x0, {D1, D8, AM, SP}, },
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{ "mov", 0x0, 0x0, {S0, DM, AN}, },
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{ "mov", 0x0, 0x0, {D1, DM, D8, AN}, },
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{ "mov", 0x0, 0x0, {D2, DM, D16, AN}, },
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{ "mov", 0x0, 0x0, {D4, DM, D32, AN}, },
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{ "mov", 0x0, 0x0, {S1, DM, D8, SP}, },
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{ "mov", 0x0, 0x0, {D2, DM, D16, SP}, },
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{ "mov", 0x0, 0x0, {D4, DM, D32, SP}, },
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{ "mov", 0x0, 0x0, {D0, DM, DI, AN}, },
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{ "mov", 0x0, 0x0, {S2, DM, ABS16}, },
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{ "mov", 0x0, 0x0, {D4, DM, ABS32}, },
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{ "mov", 0x0, 0x0, {D0, AM, AN}, },
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{ "mov", 0x0, 0x0, {D1, AM, D8, AN}, },
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{ "mov", 0x0, 0x0, {D2, AM, D16, AN}, },
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{ "mov", 0x0, 0x0, {D4, AM, D32, AN}, },
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{ "mov", 0x0, 0x0, {S1, AM, D32, SP}, },
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{ "mov", 0x0, 0x0, {D2, AM, D16, SP}, },
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{ "mov", 0x0, 0x0, {D4, AM, D32, SP}, },
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{ "mov", 0x0, 0x0, {D0, AM, DI, AN}, },
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{ "mov", 0x0, 0x0, {D2, AM, ABS16}, },
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{ "mov", 0x0, 0x0, {D4, AM, ABS32}, },
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{ "mov", 0x0, 0x0, {D1, SP, D8, AN}, },
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{ "mov", 0x0, 0x0, {S2, IMM16, DN}, },
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{ "mov", 0x0, 0x0, {D4, IMM32, DN}, },
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{ "mov", 0x0, 0x0, {S2, IMM16, AN}, },
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{ "mov", 0x0, 0x0, {D4, IMM32, AN}, },
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{ "movbu", 0, 0, {D0, AM, DN}, },
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{ "movbu", 0, 0, {D1, D8, AM, DN}, },
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{ "movbu", 0, 0, {D2, D16, AM, DN}, },
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{ "movbu", 0, 0, {D4, D32, AM, DN}, },
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{ "movbu", 0, 0, {D1, D8, SP, DN}, },
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{ "movbu", 0, 0, {D2, D16, SP, DN}, },
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{ "movbu", 0, 0, {D4, D32, SP, DN}, },
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{ "movbu", 0, 0, {D0, DI, AM, DN}, },
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{ "movbu", 0, 0, {S2, ABS16, DN}, },
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{ "movbu", 0, 0, {D4, ABS32, DN}, },
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{ "movbu", 0, 0, {D0, DM, AN}, },
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{ "movbu", 0, 0, {D1, DM, D8, AN}, },
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{ "movbu", 0, 0, {D2, DM, D16, AN}, },
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{ "movbu", 0, 0, {D4, DM, D32, AN}, },
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{ "movbu", 0, 0, {D1, DM, D8, SP}, },
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{ "movbu", 0, 0, {D2, DM, D16, SP}, },
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{ "movbu", 0, 0, {D4, DM, D32, SP}, },
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{ "movbu", 0, 0, {D0, DM, DI, AN}, },
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{ "movbu", 0, 0, {S2, ABS16, AN}, },
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{ "movbu", 0, 0, {D4, ABS32, AN}, },
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{ "movhu", 0, 0, {D0, AM, DN}, },
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{ "movhu", 0, 0, {D1, D8, AM, DN}, },
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{ "movhu", 0, 0, {D2, D16, AM, DN}, },
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{ "movhu", 0, 0, {D4, D32, AM, DN}, },
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{ "movhu", 0, 0, {D1, D8, SP, DN}, },
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{ "movhu", 0, 0, {D2, D16, SP, DN}, },
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{ "movhu", 0, 0, {D4, D32, SP, DN}, },
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{ "movhu", 0, 0, {D0, DI, AM, DN}, },
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{ "movhu", 0, 0, {S2, ABS16, DN}, },
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{ "movhu", 0, 0, {D4, ABS32, DN}, },
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{ "movhu", 0, 0, {D0, DM, AN}, },
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{ "movhu", 0, 0, {D1, DM, D8, AN}, },
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{ "movhu", 0, 0, {D2, DM, D16, AN}, },
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{ "movhu", 0, 0, {D4, DM, D32, AN}, },
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{ "movhu", 0, 0, {D1, DM, D8, SP}, },
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{ "movhu", 0, 0, {D2, DM, D16, SP}, },
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{ "movhu", 0, 0, {D4, DM, D32, SP}, },
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{ "movhu", 0, 0, {D0, DM, DI, AN}, },
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{ "movhu", 0, 0, {S2, ABS16, AN}, },
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{ "movbu", 0, 0, {D4, ABS32, AN}, },
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{ "ext", 0xf2d0, 0xfffc, {D0, DN}, },
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{ "extb", 0x10, 0xfc, {S0, DN}, },
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{ "extbu", 0x14, 0xfc, {S0, DN}, },
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{ "exth", 0x18, 0xfc, {S0, DN}, },
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{ "exthu", 0x1c, 0xfc, {S0, DN}, },
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{ "movm", 0, 0, {S1, SP, REGS}, },
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{ "movm", 0, 0, {S1, REGS, SP}, },
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{ "clr", 0x00, 0xf3, {S0, DN}, },
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{ "add", 0, 0, {S0, DM, DN}, },
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{ "add", 0, 0, {D0, DM, AN}, },
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{ "add", 0, 0, {D0, AM, DN}, },
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{ "add", 0, 0, {D0, AM, AN}, },
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{ "add", 0, 0, {S1, IMM8, DN}, },
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{ "add", 0, 0, {D2, IMM16, DN}, },
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{ "add", 0, 0, {D4, IMM32, DN}, },
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{ "add", 0, 0, {S1, IMM8, AN}, },
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{ "add", 0, 0, {D2, IMM16, AN}, },
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{ "add", 0, 0, {D4, IMM32, AN}, },
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{ "add", 0, 0, {D1, IMM8, SP}, },
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{ "add", 0, 0, {D2, IMM16, SP}, },
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{ "add", 0, 0, {D4, IMM32, SP}, },
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{ "addc", 0xf140, 0xfff0, {D0, DM, DN}, },
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{ "sub", 0, 0, {D0, DM, DN}, },
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{ "sub", 0, 0, {D0, DM, AN}, },
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{ "sub", 0, 0, {D0, AM, DN}, },
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{ "sub", 0, 0, {D0, AM, AN}, },
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{ "sub", 0, 0, {D4, IMM32, DN}, },
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{ "sub", 0, 0, {D4, IMM32, AN}, },
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{ "subc", 0xf180, 0xfff0, {D0, DM, DN}, },
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{ "mul", 0, 0, {D0, DM, DN}, },
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{ "mulu", 0, 0, {D0, DM, DN}, },
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{ "div", 0, 0, {D0, DM, DN}, },
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{ "divu", 0, 0, {D0, DM, DN}, },
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{ "inc", 0x40, 0xf3, {S0, DN}, },
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{ "inc", 0x41, 0xf3, {S0, AN}, },
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{ "inc4", 0x50, 0xfc, {S0, AN}, },
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{ "cmp", 0, 0, {S1, IMM8, DN}, },
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{ "cmp", 0, 0, {S0, DM, DN}, },
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{ "cmp", 0, 0, {D0, DM, AN}, },
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{ "cmp", 0, 0, {D0, AM, DN}, },
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{ "cmp", 0, 0, {S1, IMM8, AN}, },
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{ "cmp", 0, 0, {S0, AM, AN}, },
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{ "cmp", 0, 0, {D2, IMM16, DN}, },
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{ "cmp", 0, 0, {D4, IMM32, DN}, },
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{ "cmp", 0, 0, {D2, IMM16, AN}, },
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{ "cmp", 0, 0, {D4, IMM32, AN}, },
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{ "and", 0, 0, {D0, DM, DN}, },
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{ "and", 0, 0, {D1, IMM8, DN}, },
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{ "and", 0, 0, {D2, IMM16, DN}, },
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{ "and", 0, 0, {D4, IMM32, DN}, },
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{ "and", 0, 0, {D2, PSW, DN}, },
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{ "or", 0, 0, {D0, DM, DN}, },
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{ "or", 0, 0, {D1, IMM8, DN}, },
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{ "or", 0, 0, {D2, IMM16, DN}, },
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{ "or", 0, 0, {D4, IMM32, DN}, },
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{ "or", 0, 0, {D2, PSW, DN}, },
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{ "xor", 0, 0, {D0, DM, DN}, },
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{ "xor", 0, 0, {D2, IMM16, DN}, },
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{ "xor", 0, 0, {D4, IMM32, DN}, },
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{ "not", 0xf230, 0xfffc, {D0, DN}, },
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{ "btst", 0, 0, {D1, IMM8, DN}, },
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{ "btst", 0, 0, {D2, IMM16, DN}, },
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{ "btst", 0, 0, {D4, IMM32, DN}, },
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{ "btst", 0, 0, {D2, IMM8, D8, AN}, },
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{ "btst", 0, 0, {D5, IMM8, ABS32}, },
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{ "bset", 0, 0, {D0, DM, AN}, },
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{ "bset", 0, 0, {D2, IMM8, D8, AN}, },
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{ "bset", 0, 0, {D5, IMM8, ABS32}, },
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{ "bclr", 0, 0, {D0, DM, AN}, },
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{ "bclr", 0, 0, {D2, IMM8, D8, AN}, },
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{ "bclr", 0, 0, {D5, IMM8, ABS32}, },
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{ "asr", 0xf2b0, 0xfff0, {D0, DM, DN}, },
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{ "asr", 0xf8c800, 0xfffc00, {D1, UIMM8, DN}, },
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{ "lsr", 0xf2a0, 0xfff0, {D0, DM, DN}, },
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{ "lsr", 0xf8c4, 0xfffc00, {D0, UIMM8, DN}, },
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{ "asl", 0xf290, 0xfff0, {D0, DM, DN}, },
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{ "asl", 0xf8c000, 0xfffc00, {D0, UIMM8, DN}, },
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{ "asl2", 0x54, 0xfc, {S0, DN}, },
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{ "ror", 0xf284, 0xfffc, {D0, DN}, },
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{ "rol", 0xf280, 0xfffc, {D0, DN}, },
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{ "beq", 0xc800, 0xff00, {S1, D8}, },
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{ "bne", 0xc900, 0xff00, {S1, D8}, },
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{ "bgt", 0xc100, 0xff00, {S1, D8}, },
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{ "bge", 0xc200, 0xff00, {S1, D8}, },
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{ "ble", 0xc300, 0xff00, {S1, D8}, },
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{ "blt", 0xc000, 0xff00, {S1, D8}, },
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{ "bhi", 0xc500, 0xff00, {S1, D8}, },
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{ "bcc", 0xc600, 0xff00, {S1, D8}, },
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{ "bls", 0xc700, 0xff00, {S1, D8}, },
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{ "bcs", 0xc400, 0xff00, {S1, D8}, },
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{ "bvc", 0xf8e800, 0xffff00, {D1, D8}, },
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{ "bvs", 0xf8e900, 0xffff00, {D1, D8}, },
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{ "bnc", 0xf8ea00, 0xffff00, {D1, D8}, },
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{ "bns", 0xf8eb00, 0xffff00, {D1, D8}, },
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{ "bra", 0xca00, 0xff00, {S1, D8}, },
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{ "leq", 0xd8, 0xff, {S0}, },
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{ "lne", 0xd9, 0xff, {S0}, },
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{ "lgt", 0xd1, 0xff, {S0}, },
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{ "lge", 0xd2, 0xff, {S0}, },
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{ "lle", 0xd3, 0xff, {S0}, },
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{ "llt", 0xd0, 0xff, {S0}, },
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{ "lhi", 0xd5, 0xff, {S0}, },
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{ "lcc", 0xd6, 0xff, {S0}, },
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{ "lls", 0xd7, 0xff, {S0}, },
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{ "lcs", 0xd4, 0xff, {S0}, },
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{ "lra", 0xda, 0xff, {S0}, },
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{ "lcc", 0xd6, 0xff, {S0}, },
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{ "setlb", 0xdb, 0xff, {S0}, },
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{ "jmp", 0xf0f4, 0xfffc, {D0, AN}, },
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{ "jmp", 0xcc0000, 0xff0000, {S2, D16}, },
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{ "jmp", 0xdc0000, 0xff0000, {S4, D32}, },
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{ "call", 0, 0, {S4, D16,}, },
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{ "call", 0, 0, {S6, D32,}, },
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{ "calls", 0, 0, {D0, AN}, },
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{ "calls", 0, 0, {D2, D16}, },
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{ "calls", 0, 0, {D4, D32}, },
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{ "ret", 0, 0, {S2}, },
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{ "retf", 0, 0, {S2}, },
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{ "rets", 0xf0fc, 0xffff, {D0}, },
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{ "rti", 0xf0fd, 0xffff, {D0}, },
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{ "trap", 0xf0fe, 0xffff, {D0}, },
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{ "nop", 0xcb, 0xff, {S0}, },
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/* { "udf", 0, 0, {0}, }, */
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} ;
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const int mn10300_num_opcodes =
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sizeof (mn10300_opcodes) / sizeof (mn10300_opcodes[0]);
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