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aarch64: Add the SME2 ZT0 instructions
SME2 adds lookup table instructions for quantisation. They use a new lookup table register called ZT0. LUTI2 takes an unsuffixed SVE vector index of the form Zn[<imm>], which is the first time that this syntax has been used.
This commit is contained in:
Richard Sandiford
parent
99e01a66b4
commit
cbd11b8818
@ -312,6 +312,7 @@ struct reloc_entry
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BASIC_REG_TYPE(ZAT) /* za[0-15] (ZA tile) */ \
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BASIC_REG_TYPE(ZATH) /* za[0-15]h (ZA tile horizontal slice) */ \
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BASIC_REG_TYPE(ZATV) /* za[0-15]v (ZA tile vertical slice) */ \
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BASIC_REG_TYPE(ZT0) /* zt0 */ \
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/* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \
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MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \
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/* Typecheck: same, plus SVE registers. */ \
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@ -483,11 +484,11 @@ get_reg_expected_msg (unsigned int mask, unsigned int seen)
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if (mask == reg_type_masks[REG_TYPE_VZP])
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return N_("expected a vector or predicate register at operand %d");
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/* ZA-related registers. */
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/* SME-related registers. */
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if (mask == reg_type_masks[REG_TYPE_ZA])
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return N_("expected a ZA array vector at operand %d");
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if (mask == reg_type_masks[REG_TYPE_ZA_ZAT])
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return N_("expected 'za' or a ZA tile at operand %d");
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if (mask == (reg_type_masks[REG_TYPE_ZA_ZAT] | reg_type_masks[REG_TYPE_ZT0]))
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return N_("expected ZT0 or a ZA mask at operand %d");
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if (mask == reg_type_masks[REG_TYPE_ZAT])
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return N_("expected a ZA tile at operand %d");
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if (mask == reg_type_masks[REG_TYPE_ZATHV])
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@ -1279,7 +1280,10 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,
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if (!(flags & PTR_FULL_REG) && skip_past_char (&str, '['))
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{
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/* Reject Sn[index] syntax. */
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if (reg->type != REG_TYPE_PN && !is_typed_vecreg)
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if (reg->type != REG_TYPE_Z
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&& reg->type != REG_TYPE_PN
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&& reg->type != REG_TYPE_ZT0
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&& !is_typed_vecreg)
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{
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first_error (_("this type of register can't be indexed"));
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return NULL;
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@ -6722,6 +6726,12 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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case AARCH64_OPND_SVE_Zm4_11_INDEX:
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case AARCH64_OPND_SVE_Zm4_INDEX:
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case AARCH64_OPND_SVE_Zn_INDEX:
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case AARCH64_OPND_SME_Zn_INDEX1_16:
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case AARCH64_OPND_SME_Zn_INDEX2_15:
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case AARCH64_OPND_SME_Zn_INDEX2_16:
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case AARCH64_OPND_SME_Zn_INDEX3_14:
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case AARCH64_OPND_SME_Zn_INDEX3_15:
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case AARCH64_OPND_SME_Zn_INDEX4_14:
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reg_type = REG_TYPE_Z;
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goto vector_reg_index;
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@ -6735,14 +6745,23 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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reg = aarch64_reg_parse (&str, reg_type, &vectype);
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if (!reg)
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goto failure;
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if (vectype.type == NT_invtype || !(vectype.defined & NTA_HASINDEX))
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if (!(vectype.defined & NTA_HASINDEX))
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goto failure;
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if (reg->type == REG_TYPE_Z && vectype.type == NT_invtype)
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/* Unqualified Zn[index] is allowed in LUTI2 instructions. */
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info->qualifier = AARCH64_OPND_QLF_NIL;
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else
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{
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if (vectype.type == NT_invtype)
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goto failure;
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info->qualifier = vectype_to_qualifier (&vectype);
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if (info->qualifier == AARCH64_OPND_QLF_NIL)
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goto failure;
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}
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info->reglane.regno = reg->number;
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info->reglane.index = vectype.index;
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info->qualifier = vectype_to_qualifier (&vectype);
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if (info->qualifier == AARCH64_OPND_QLF_NIL)
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goto failure;
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break;
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case AARCH64_OPND_SVE_ZnxN:
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@ -7740,6 +7759,39 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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goto failure;
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break;
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case AARCH64_OPND_SME_ZT0:
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po_reg_or_fail (REG_TYPE_ZT0);
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break;
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case AARCH64_OPND_SME_ZT0_INDEX:
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reg = aarch64_reg_parse (&str, REG_TYPE_ZT0, &vectype);
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if (!reg || vectype.type != NT_invtype)
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goto failure;
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if (!(vectype.defined & NTA_HASINDEX))
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{
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set_syntax_error (_("missing register index"));
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goto failure;
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}
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info->imm.value = vectype.index;
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break;
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case AARCH64_OPND_SME_ZT0_LIST:
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if (*str != '{')
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{
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set_expected_reglist_error (REG_TYPE_ZT0, parse_reg (&str));
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goto failure;
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}
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str++;
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if (!parse_typed_reg (&str, REG_TYPE_ZT0, &vectype, PTR_IN_REGLIST))
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goto failure;
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if (*str != '}')
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{
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set_syntax_error (_("expected '}' after ZT0"));
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goto failure;
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}
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str++;
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break;
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case AARCH64_OPND_SME_PNn3_INDEX1:
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case AARCH64_OPND_SME_PNn3_INDEX2:
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reg = aarch64_reg_parse (&str, REG_TYPE_PN, &vectype);
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@ -8462,7 +8514,10 @@ static const reg_entry reg_names[] = {
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REGSET16S (za, h, ZATH), REGSET16S (ZA, H, ZATH),
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/* SME ZA tile registers (vertical slice). */
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REGSET16S (za, v, ZATV), REGSET16S (ZA, V, ZATV)
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REGSET16S (za, v, ZATV), REGSET16S (ZA, V, ZATV),
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/* SME2 ZT0. */
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REGDEF (zt0, 0, ZT0), REGDEF (ZT0, 0, ZT0)
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};
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#undef REGDEF
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@ -22,11 +22,11 @@
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[^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {za,}'
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[^:]*:[0-9]+: Error: unexpected character `}' in element size at operand 1 -- `zero {za.}'
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[^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za-}'
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[^:]*:[0-9]+: Error: expected 'za' or a ZA tile at operand 1 -- `zero {za_}'
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[^:]*:[0-9]+: Error: expected ZT0 or a ZA mask at operand 1 -- `zero {za_}'
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[^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za#}'
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[^:]*:[0-9]+: Error: expected 'za' or a ZA tile at operand 1 -- `zero {zaX}'
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[^:]*:[0-9]+: Error: expected ZT0 or a ZA mask at operand 1 -- `zero {zaX}'
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[^:]*:[0-9]+: Error: missing ZA tile size at operand 1 -- `zero {za0}'
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[^:]*:[0-9]+: Error: expected 'za' or a ZA tile at operand 1 -- `zero {zax}'
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[^:]*:[0-9]+: Error: expected ZT0 or a ZA mask at operand 1 -- `zero {zax}'
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[^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za{}'
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[^:]*:[0-9]+: Error: unexpected characters following instruction at operand 1 -- `zero {za}}'
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[^:]*:[0-9]+: Error: ZA tile masks do not operate at .Q granularity at operand 1 -- `zero {za0\.q}'
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3
gas/testsuite/gas/aarch64/sme2-8-invalid.d
Normal file
3
gas/testsuite/gas/aarch64/sme2-8-invalid.d
Normal file
@ -0,0 +1,3 @@
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#as: -march=armv8-a
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#source: sme2-8-invalid.s
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#error_output: sme2-8-invalid.l
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208
gas/testsuite/gas/aarch64/sme2-8-invalid.l
Normal file
208
gas/testsuite/gas/aarch64/sme2-8-invalid.l
Normal file
@ -0,0 +1,208 @@
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[^ :]+: Assembler messages:
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[^ :]+:[0-9]+: Error: expected '{' at operand 1 -- `zero 0'
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[^ :]+:[0-9]+: Error: expected '{' at operand 1 -- `zero zt0'
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[^ :]+:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {'
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[^ :]+:[0-9]+: Error: expected ZT0 or a ZA mask at operand 1 -- `zero {foo}'
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[^ :]+:[0-9]+: Error: expected ZT0 or a ZA mask at operand 1 -- `zero {zt}'
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[^ :]+:[0-9]+: Error: expected ZT0 or a ZA mask at operand 1 -- `zero {x0}'
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[^ :]+:[0-9]+: Error: expected ZT0 or a ZA mask at operand 1 -- `zero {z0}'
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[^ :]+:[0-9]+: Error: expected '}' after ZT0 at operand 1 -- `zero {zt0'
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[^ :]+:[0-9]+: Error: expected '}' after ZT0 at operand 1 -- `zero {zt0\.b}'
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[^ :]+:[0-9]+: Error: expected '}' after ZT0 at operand 1 -- `zero {zt0,zt0}'
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[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `movt 0,zt0\[0\]'
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[^ :]+:[0-9]+: Error: expected a register at operand 2 -- `movt x0,0'
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[^ :]+:[0-9]+: Error: missing register index at operand 1 -- `movt zt0,x0'
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[^ :]+:[0-9]+: Error: unexpected register type at operand 1 -- `movt za\[0\],x0'
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[^ :]+:[0-9]+: Error: unexpected register type at operand 1 -- `movt za0\[0\],x0'
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[^ :]+:[0-9]+: Error: bad expression at operand 1 -- `movt zt0\[#0\],x0'
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[^ :]+:[0-9]+: Error: register element index out of range 0 to 56 at operand 1 -- `movt zt0\[-1\],x0'
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[^ :]+:[0-9]+: Error: byte index must be a multiple of 8 at operand 1 -- `movt zt0\[1\],x0'
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[^ :]+:[0-9]+: Error: byte index must be a multiple of 8 at operand 1 -- `movt zt0\[2\],x0'
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[^ :]+:[0-9]+: Error: byte index must be a multiple of 8 at operand 1 -- `movt zt0\[4\],x0'
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[^ :]+:[0-9]+: Error: byte index must be a multiple of 8 at operand 1 -- `movt zt0\[7\],x0'
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[^ :]+:[0-9]+: Error: byte index must be a multiple of 8 at operand 1 -- `movt zt0\[49\],x0'
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[^ :]+:[0-9]+: Error: byte index must be a multiple of 8 at operand 1 -- `movt zt0\[50\],x0'
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[^ :]+:[0-9]+: Error: byte index must be a multiple of 8 at operand 1 -- `movt zt0\[52\],x0'
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[^ :]+:[0-9]+: Error: register element index out of range 0 to 56 at operand 1 -- `movt zt0\[57\],x0'
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[^ :]+:[0-9]+: Error: register element index out of range 0 to 56 at operand 1 -- `movt zt0\[64\],x0'
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[^ :]+:[0-9]+: Error: register element index out of range 0 to 56 at operand 1 -- `movt zt0\[1<<32\],x0'
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[^ :]+:[0-9]+: Error: missing register index at operand 1 -- `movt zt0\.b\[0\],x0'
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[^ :]+:[0-9]+: Error: missing register index at operand 1 -- `movt zt0/z\[0\],x0'
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[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `movt zt0\[0\],sp'
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[^ :]+:[0-9]+: Error: operand mismatch -- `movt zt0\[0\],w0'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: movt zt0\[0\], x0
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[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `movt zt0\[0\],wsp'
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[^ :]+:[0-9]+: Error: operand mismatch -- `movt zt0\[0\],wzr'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: movt zt0\[0\], xzr
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[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `movt zt0\[0\],0'
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[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `ldr 0,\[x0\]'
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[^ :]+:[0-9]+: Error: invalid addressing mode at operand 2 -- `ldr zt0,0'
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[^ :]+:[0-9]+: Error: operand 2 must be an address with base register \(no offset\) -- `ldr zt0,\[x0,#0\]'
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[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `ldr Zt0,\[x0\]'
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[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `ldr zT0,\[x0\]'
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[^ :]+:[0-9]+: Error: '\]' expected at operand 2 -- `ldr zt0,\[x0,#0,mul vl\]'
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[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 2 -- `ldr zt0,\[w0\]'
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[^ :]+:[0-9]+: Error: missing offset in the pre-indexed address at operand 2 -- `ldr zt0,\[x0\]!'
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[^ :]+:[0-9]+: Error: invalid base register at operand 2 -- `ldr zt0,\[xzr\]'
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[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 2 -- `ldr zt0,\[wsp\]'
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[^ :]+:[0-9]+: Error: invalid addressing mode at operand 2 -- `ldr zt0,\[x0,xzr\]'
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[^ :]+:[0-9]+: Error: invalid addressing mode at operand 2 -- `ldr zt0,\[x1,x2\]'
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[^ :]+:[0-9]+: Error: register element index out of range 0 to 15 at operand 3 -- `luti2 z0\.b,zt0,z0\[-1\]'
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[^ :]+:[0-9]+: Error: register element index out of range 0 to 15 at operand 3 -- `luti2 z0\.b,zt0,z0\[16\]'
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[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 z0\.b,zt0,z0\.b\[0\]'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: luti2 z0\.b, zt0, z0\[0\]
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[^ :]+:[0-9]+: Info: other valid variant\(s\):
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[^ :]+:[0-9]+: Info: luti2 z0\.h, zt0, z0\[0\]
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[^ :]+:[0-9]+: Info: luti2 z0\.s, zt0, z0\[0\]
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[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 z0,zt0,z0\[0\]'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: luti2 z0\.b, zt0, z0\[0\]
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[^ :]+:[0-9]+: Info: other valid variant\(s\):
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[^ :]+:[0-9]+: Info: luti2 z0\.h, zt0, z0\[0\]
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[^ :]+:[0-9]+: Info: luti2 z0\.s, zt0, z0\[0\]
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[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 z0\.d,zt0,z0\[0\]'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: luti2 z0\.b, zt0, z0\[0\]
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[^ :]+:[0-9]+: Info: other valid variant\(s\):
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[^ :]+:[0-9]+: Info: luti2 z0\.h, zt0, z0\[0\]
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[^ :]+:[0-9]+: Info: luti2 z0\.s, zt0, z0\[0\]
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[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 z0\.q,zt0,z0\[0\]'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: luti2 z0\.b, zt0, z0\[0\]
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[^ :]+:[0-9]+: Info: other valid variant\(s\):
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[^ :]+:[0-9]+: Info: luti2 z0\.h, zt0, z0\[0\]
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[^ :]+:[0-9]+: Info: luti2 z0\.s, zt0, z0\[0\]
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[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `luti2 z0\.b,zt0,zt0'
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[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti2 0,zt0,z0\[0\]'
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[^ :]+:[0-9]+: Error: expected a register at operand 2 -- `luti2 z0\.b,0,z0\[0\]'
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[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `luti2 z0\.b,zt0,0'
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[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `luti2 {z1\.b-z2\.b},zt0,z0\[0\]'
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[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti2 {z0\.b-z1\.b},z0,z0\[0\]'
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[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti2 {z0\.b-z1\.b},za,z0\[0\]'
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[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 {z0\.h-z1\.h},zt0,z0\.h\[0\]'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: luti2 {z0\.h-z1\.h}, zt0, z0\[0\]
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[^ :]+:[0-9]+: Info: other valid variant\(s\):
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[^ :]+:[0-9]+: Info: luti2 {z0\.b-z1\.b}, zt0, z0\[0\]
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[^ :]+:[0-9]+: Info: luti2 {z0\.s-z1\.s}, zt0, z0\[0\]
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[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `luti2 {z0\.h-z1\.h},zt0,z0\[-1\]'
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[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `luti2 {z0\.h-z1\.h},zt0,z0\[8\]'
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[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 {z0\.d-z1\.d},zt0,z0\[0\]'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: luti2 {z0\.b-z1\.b}, zt0, z0\[0\]
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[^ :]+:[0-9]+: Info: other valid variant\(s\):
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[^ :]+:[0-9]+: Info: luti2 {z0\.h-z1\.h}, zt0, z0\[0\]
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[^ :]+:[0-9]+: Info: luti2 {z0\.s-z1\.s}, zt0, z0\[0\]
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[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 {z0\.q-z1\.q},zt0,z0\[0\]'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: luti2 {z0\.b-z1\.b}, zt0, z0\[0\]
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[^ :]+:[0-9]+: Info: other valid variant\(s\):
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[^ :]+:[0-9]+: Info: luti2 {z0\.h-z1\.h}, zt0, z0\[0\]
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[^ :]+:[0-9]+: Info: luti2 {z0\.s-z1\.s}, zt0, z0\[0\]
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[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `luti2 {z1\.s-z4\.s},zt0,z0\[0\]'
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[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `luti2 {z2\.s-z5\.s},zt0,z0\[0\]'
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[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `luti2 {z3\.s-z6\.s},zt0,z0\[0\]'
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[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti2 {z0\.s-z3\.s},z0,z0\[0\]'
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[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti2 {z0\.b-z3\.b},za,z0\[0\]'
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[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 {z0\.b-z3\.b},zt0,z0\.b\[0\]'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: luti2 {z0\.b-z3\.b}, zt0, z0\[0\]
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[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: luti2 {z0\.h-z3\.h}, zt0, z0\[0\]
|
||||
[^ :]+:[0-9]+: Info: luti2 {z0\.s-z3\.s}, zt0, z0\[0\]
|
||||
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `luti2 {z0\.b-z3\.b},zt0,z0\[-1\]'
|
||||
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `luti2 {z0\.b-z3\.b},zt0,z0\[4\]'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 {z0\.d-z3\.d},zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: luti2 {z0\.b-z3\.b}, zt0, z0\[0\]
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: luti2 {z0\.h-z3\.h}, zt0, z0\[0\]
|
||||
[^ :]+:[0-9]+: Info: luti2 {z0\.s-z3\.s}, zt0, z0\[0\]
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 {z0\.q-z3\.q},zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: luti2 {z0\.b-z3\.b}, zt0, z0\[0\]
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: luti2 {z0\.h-z3\.h}, zt0, z0\[0\]
|
||||
[^ :]+:[0-9]+: Info: luti2 {z0\.s-z3\.s}, zt0, z0\[0\]
|
||||
[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti4 0,zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: expected a register at operand 2 -- `luti4 z0\.b,0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `luti4 z0\.b,zt0,0'
|
||||
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `luti4 z0\.h,zt0,z0\[-1\]'
|
||||
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `luti4 z0\.h,zt0,z0\[8\]'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 z0\.h,zt0,z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: luti4 z0\.h, zt0, z0\[0\]
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: luti4 z0\.b, zt0, z0\[0\]
|
||||
[^ :]+:[0-9]+: Info: luti4 z0\.s, zt0, z0\[0\]
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 z0,zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: luti4 z0\.b, zt0, z0\[0\]
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: luti4 z0\.h, zt0, z0\[0\]
|
||||
[^ :]+:[0-9]+: Info: luti4 z0\.s, zt0, z0\[0\]
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 z0\.d,zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: luti4 z0\.b, zt0, z0\[0\]
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: luti4 z0\.h, zt0, z0\[0\]
|
||||
[^ :]+:[0-9]+: Info: luti4 z0\.s, zt0, z0\[0\]
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 z0\.q,zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: luti4 z0\.b, zt0, z0\[0\]
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: luti4 z0\.h, zt0, z0\[0\]
|
||||
[^ :]+:[0-9]+: Info: luti4 z0\.s, zt0, z0\[0\]
|
||||
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `luti4 z0\.h,zt0,zt0'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `luti4 {z1\.h-z2\.h},zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti4 {z0\.h-z1\.h},z0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti4 {z0\.h-z1\.h},za,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 {z0\.h-z1\.h},zt0,z0\.h\[0\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: luti4 {z0\.h-z1\.h}, zt0, z0\[0\]
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: luti4 {z0\.b-z1\.b}, zt0, z0\[0\]
|
||||
[^ :]+:[0-9]+: Info: luti4 {z0\.s-z1\.s}, zt0, z0\[0\]
|
||||
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `luti4 {z0\.h-z1\.h},zt0,z0\[-1\]'
|
||||
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `luti4 {z0\.h-z1\.h},zt0,z0\[4\]'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 {z0\.d-z1\.d},zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: luti4 {z0\.b-z1\.b}, zt0, z0\[0\]
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: luti4 {z0\.h-z1\.h}, zt0, z0\[0\]
|
||||
[^ :]+:[0-9]+: Info: luti4 {z0\.s-z1\.s}, zt0, z0\[0\]
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 {z0\.q-z1\.q},zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: luti4 {z0\.b-z1\.b}, zt0, z0\[0\]
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: luti4 {z0\.h-z1\.h}, zt0, z0\[0\]
|
||||
[^ :]+:[0-9]+: Info: luti4 {z0\.s-z1\.s}, zt0, z0\[0\]
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `luti4 {z1\.s-z4\.s},zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `luti4 {z2\.s-z5\.s},zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `luti4 {z3\.s-z6\.s},zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti4 {z0\.s-z3\.s},z0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti4 {z0\.s-z3\.s},za,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 {z0\.s-z3\.s},zt0,z0\.s\[0\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: luti4 {z0\.s-z3\.s}, zt0, z0\[0\]
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: luti4 {z0\.b-z3\.b}, zt0, z0\[0\]
|
||||
[^ :]+:[0-9]+: Info: luti4 {z0\.h-z3\.h}, zt0, z0\[0\]
|
||||
[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `luti4 {z0\.s-z3\.s},zt0,z0\[-1\]'
|
||||
[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `luti4 {z0\.s-z3\.s},zt0,z0\[2\]'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `luti4 {z0\.b-z3\.b},zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 {z0\.d-z3\.d},zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: luti4 {z0\.b-z3\.b}, zt0, z0\[0\]
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: luti4 {z0\.h-z3\.h}, zt0, z0\[0\]
|
||||
[^ :]+:[0-9]+: Info: luti4 {z0\.s-z3\.s}, zt0, z0\[0\]
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 {z0\.q-z3\.q},zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: luti4 {z0\.b-z3\.b}, zt0, z0\[0\]
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: luti4 {z0\.h-z3\.h}, zt0, z0\[0\]
|
||||
[^ :]+:[0-9]+: Info: luti4 {z0\.s-z3\.s}, zt0, z0\[0\]
|
||||
116
gas/testsuite/gas/aarch64/sme2-8-invalid.s
Normal file
116
gas/testsuite/gas/aarch64/sme2-8-invalid.s
Normal file
@ -0,0 +1,116 @@
|
||||
zero 0
|
||||
|
||||
zero zt0
|
||||
zero {
|
||||
zero { foo }
|
||||
zero { zt }
|
||||
zero { x0 }
|
||||
zero { z0 }
|
||||
zero { zt0
|
||||
zero { zt0.b }
|
||||
zero { zt0, zt0 }
|
||||
|
||||
movt 0, zt0[0]
|
||||
movt x0, 0
|
||||
|
||||
movt zt0, x0
|
||||
movt za[0], x0
|
||||
movt za0[0], x0
|
||||
movt zt0[#0], x0
|
||||
movt zt0[-1], x0
|
||||
movt zt0[1],x0
|
||||
movt zt0[2],x0
|
||||
movt zt0[4],x0
|
||||
movt zt0[7],x0
|
||||
movt zt0[49],x0
|
||||
movt zt0[50],x0
|
||||
movt zt0[52],x0
|
||||
movt zt0[57],x0
|
||||
movt zt0[64], x0
|
||||
movt zt0[1<<32], x0
|
||||
movt zt0.b[0], x0
|
||||
movt zt0/z[0], x0
|
||||
movt zt0[0], sp
|
||||
movt zt0[0], w0
|
||||
movt zt0[0], wsp
|
||||
movt zt0[0], wzr
|
||||
movt zt0[0], 0
|
||||
|
||||
ldr 0, [x0]
|
||||
ldr zt0, 0
|
||||
|
||||
ldr zt0, [x0, #0]
|
||||
ldr Zt0, [x0]
|
||||
ldr zT0, [x0]
|
||||
ldr zt0, [x0, #0, mul vl]
|
||||
ldr zt0, [w0]
|
||||
ldr zt0, [x0]!
|
||||
ldr zt0, [xzr]
|
||||
ldr zt0, [wsp]
|
||||
ldr zt0, [x0, xzr]
|
||||
ldr zt0, [x1, x2]
|
||||
|
||||
luti2 z0.b, zt0, z0[-1]
|
||||
luti2 z0.b, zt0, z0[16]
|
||||
luti2 z0.b, zt0, z0.b[0]
|
||||
luti2 z0, zt0, z0[0]
|
||||
luti2 z0.d, zt0, z0[0]
|
||||
luti2 z0.q, zt0, z0[0]
|
||||
luti2 z0.b, zt0, zt0
|
||||
|
||||
luti2 0, zt0, z0[0]
|
||||
luti2 z0.b, 0, z0[0]
|
||||
luti2 z0.b, zt0, 0
|
||||
|
||||
luti2 { z1.b - z2.b }, zt0, z0[0]
|
||||
luti2 { z0.b - z1.b }, z0, z0[0]
|
||||
luti2 { z0.b - z1.b }, za, z0[0]
|
||||
luti2 { z0.h - z1.h }, zt0, z0.h[0]
|
||||
luti2 { z0.h - z1.h }, zt0, z0[-1]
|
||||
luti2 { z0.h - z1.h }, zt0, z0[8]
|
||||
luti2 { z0.d - z1.d }, zt0, z0[0]
|
||||
luti2 { z0.q - z1.q }, zt0, z0[0]
|
||||
|
||||
luti2 { z1.s - z4.s }, zt0, z0[0]
|
||||
luti2 { z2.s - z5.s }, zt0, z0[0]
|
||||
luti2 { z3.s - z6.s }, zt0, z0[0]
|
||||
luti2 { z0.s - z3.s }, z0, z0[0]
|
||||
luti2 { z0.b - z3.b }, za, z0[0]
|
||||
luti2 { z0.b - z3.b }, zt0, z0.b[0]
|
||||
luti2 { z0.b - z3.b }, zt0, z0[-1]
|
||||
luti2 { z0.b - z3.b }, zt0, z0[4]
|
||||
luti2 { z0.d - z3.d }, zt0, z0[0]
|
||||
luti2 { z0.q - z3.q }, zt0, z0[0]
|
||||
|
||||
luti4 0, zt0, z0[0]
|
||||
luti4 z0.b, 0, z0[0]
|
||||
luti4 z0.b, zt0, 0
|
||||
|
||||
luti4 z0.h, zt0, z0[-1]
|
||||
luti4 z0.h, zt0, z0[8]
|
||||
luti4 z0.h, zt0, z0.h[0]
|
||||
luti4 z0, zt0, z0[0]
|
||||
luti4 z0.d, zt0, z0[0]
|
||||
luti4 z0.q, zt0, z0[0]
|
||||
luti4 z0.h, zt0, zt0
|
||||
|
||||
luti4 { z1.h - z2.h }, zt0, z0[0]
|
||||
luti4 { z0.h - z1.h }, z0, z0[0]
|
||||
luti4 { z0.h - z1.h }, za, z0[0]
|
||||
luti4 { z0.h - z1.h }, zt0, z0.h[0]
|
||||
luti4 { z0.h - z1.h }, zt0, z0[-1]
|
||||
luti4 { z0.h - z1.h }, zt0, z0[4]
|
||||
luti4 { z0.d - z1.d }, zt0, z0[0]
|
||||
luti4 { z0.q - z1.q }, zt0, z0[0]
|
||||
|
||||
luti4 { z1.s - z4.s }, zt0, z0[0]
|
||||
luti4 { z2.s - z5.s }, zt0, z0[0]
|
||||
luti4 { z3.s - z6.s }, zt0, z0[0]
|
||||
luti4 { z0.s - z3.s }, z0, z0[0]
|
||||
luti4 { z0.s - z3.s }, za, z0[0]
|
||||
luti4 { z0.s - z3.s }, zt0, z0.s[0]
|
||||
luti4 { z0.s - z3.s }, zt0, z0[-1]
|
||||
luti4 { z0.s - z3.s }, zt0, z0[2]
|
||||
luti4 { z0.b - z3.b }, zt0, z0[0]
|
||||
luti4 { z0.d - z3.d }, zt0, z0[0]
|
||||
luti4 { z0.q - z3.q }, zt0, z0[0]
|
||||
3
gas/testsuite/gas/aarch64/sme2-8-noarch.d
Normal file
3
gas/testsuite/gas/aarch64/sme2-8-noarch.d
Normal file
@ -0,0 +1,3 @@
|
||||
#as: -march=armv8-a+sme
|
||||
#source: sme2-8.s
|
||||
#error_output: sme2-8-noarch.l
|
||||
104
gas/testsuite/gas/aarch64/sme2-8-noarch.l
Normal file
104
gas/testsuite/gas/aarch64/sme2-8-noarch.l
Normal file
@ -0,0 +1,104 @@
|
||||
[^ :]+: Assembler messages:
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `zero {zt0}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `zero {ZT0}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `movt x0,zt0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `movt X0,ZT0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `movt x30,zt0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `movt xzr,zt0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `movt x0,zt0\[56\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `movt x9,zt0\[24\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `movt x15,zt0\[40\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `movt x22,zt0\[48\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `movt zt0\[0\],x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `movt ZT0\[0\],X0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `movt zt0\[56\],x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `movt zt0\[0\],x30'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `movt zt0\[0\],xzr'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `movt zt0\[8\],x20'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `movt zt0\[16\],x25'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `movt zt0\[32\],x27'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `movt zt0\[24\],x29'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldr zt0,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldr ZT0,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldr zt0,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldr zt0,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `str zt0,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `str ZT0,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `str zt0,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `str zt0,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z0\.b,zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 Z0\.B,ZT0,Z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z31\.b,zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z0\.b,zt0,z31\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z0\.b,zt0,z0\[15\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z0\.h,zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z31\.h,zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z0\.h,zt0,z31\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z0\.h,zt0,z0\[15\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z0\.s,zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z31\.s,zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z0\.s,zt0,z31\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z0\.s,zt0,z0\[15\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.b-z1\.b},zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {Z0\.B-Z1\.B},ZT0,Z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z30\.b-z31\.b},zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.b-z1\.b},zt0,z31\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.b-z1\.b},zt0,z0\[7\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.h-z1\.h},zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z30\.h-z31\.h},zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.h-z1\.h},zt0,z31\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.h-z1\.h},zt0,z0\[7\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.s-z1\.s},zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z30\.s-z31\.s},zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.s-z1\.s},zt0,z31\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.s-z1\.s},zt0,z0\[7\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.b-z3\.b},zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {Z0\.B-Z3\.B},ZT0,Z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z28\.b-z31\.b},zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.b-z3\.b},zt0,z31\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.b-z3\.b},zt0,z0\[3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.h-z3\.h},zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z28\.h-z31\.h},zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.h-z3\.h},zt0,z31\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.h-z3\.h},zt0,z0\[3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.s-z3\.s},zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z28\.s-z31\.s},zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.s-z3\.s},zt0,z31\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.s-z3\.s},zt0,z0\[3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z0\.b,zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti4 Z0\.b,ZT0,Z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z31\.b,zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z0\.b,zt0,z31\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z0\.b,zt0,z0\[7\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z0\.h,zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti4 Z0\.H,ZT0,Z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z31\.h,zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z0\.h,zt0,z31\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z0\.h,zt0,z0\[7\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z0\.s,zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z31\.s,zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z0\.s,zt0,z31\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z0\.s,zt0,z0\[7\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.b-z1\.b},zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {Z0\.b-Z1\.b},ZT0,Z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z30\.b-z31\.b},zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.b-z1\.b},zt0,z31\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.b-z1\.b},zt0,z0\[3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.h-z1\.h},zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {Z0\.H-Z1\.H},ZT0,Z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z30\.h-z31\.h},zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.h-z1\.h},zt0,z31\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.h-z1\.h},zt0,z0\[3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.s-z1\.s},zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z30\.s-z31\.s},zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.s-z1\.s},zt0,z31\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.s-z1\.s},zt0,z0\[3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.h-z3\.h},zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {Z0\.H-Z3\.H},ZT0,Z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z28\.h-z31\.h},zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.h-z3\.h},zt0,z31\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.h-z3\.h},zt0,z0\[1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.s-z3\.s},zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z28\.s-z31\.s},zt0,z0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.s-z3\.s},zt0,z31\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.s-z3\.s},zt0,z0\[1\]'
|
||||
112
gas/testsuite/gas/aarch64/sme2-8.d
Normal file
112
gas/testsuite/gas/aarch64/sme2-8.d
Normal file
@ -0,0 +1,112 @@
|
||||
#as: -march=armv8-a+sme2
|
||||
#objdump: -dr
|
||||
|
||||
[^:]+: file format .*
|
||||
|
||||
|
||||
[^:]+:
|
||||
|
||||
[^:]+:
|
||||
[^:]+: c0480001 zero {zt0}
|
||||
[^:]+: c0480001 zero {zt0}
|
||||
[^:]+: c04c03e0 movt x0, zt0\[0\]
|
||||
[^:]+: c04c03e0 movt x0, zt0\[0\]
|
||||
[^:]+: c04c03fe movt x30, zt0\[0\]
|
||||
[^:]+: c04c03ff movt xzr, zt0\[0\]
|
||||
[^:]+: c04c73e0 movt x0, zt0\[56\]
|
||||
[^:]+: c04c33e9 movt x9, zt0\[24\]
|
||||
[^:]+: c04c53ef movt x15, zt0\[40\]
|
||||
[^:]+: c04c63f6 movt x22, zt0\[48\]
|
||||
[^:]+: c04e03e0 movt zt0\[0\], x0
|
||||
[^:]+: c04e03e0 movt zt0\[0\], x0
|
||||
[^:]+: c04e73e0 movt zt0\[56\], x0
|
||||
[^:]+: c04e03fe movt zt0\[0\], x30
|
||||
[^:]+: c04e03ff movt zt0\[0\], xzr
|
||||
[^:]+: c04e13f4 movt zt0\[8\], x20
|
||||
[^:]+: c04e23f9 movt zt0\[16\], x25
|
||||
[^:]+: c04e43fb movt zt0\[32\], x27
|
||||
[^:]+: c04e33fd movt zt0\[24\], x29
|
||||
[^:]+: e11f8000 ldr zt0, \[x0\]
|
||||
[^:]+: e11f8000 ldr zt0, \[x0\]
|
||||
[^:]+: e11f83c0 ldr zt0, \[x30\]
|
||||
[^:]+: e11f83e0 ldr zt0, \[sp\]
|
||||
[^:]+: e13f8000 str zt0, \[x0\]
|
||||
[^:]+: e13f8000 str zt0, \[x0\]
|
||||
[^:]+: e13f83c0 str zt0, \[x30\]
|
||||
[^:]+: e13f83e0 str zt0, \[sp\]
|
||||
[^:]+: c0cc0000 luti2 z0\.b, zt0, z0\[0\]
|
||||
[^:]+: c0cc0000 luti2 z0\.b, zt0, z0\[0\]
|
||||
[^:]+: c0cc001f luti2 z31\.b, zt0, z0\[0\]
|
||||
[^:]+: c0cc03e0 luti2 z0\.b, zt0, z31\[0\]
|
||||
[^:]+: c0cfc000 luti2 z0\.b, zt0, z0\[15\]
|
||||
[^:]+: c0cc1000 luti2 z0\.h, zt0, z0\[0\]
|
||||
[^:]+: c0cc101f luti2 z31\.h, zt0, z0\[0\]
|
||||
[^:]+: c0cc13e0 luti2 z0\.h, zt0, z31\[0\]
|
||||
[^:]+: c0cfd000 luti2 z0\.h, zt0, z0\[15\]
|
||||
[^:]+: c0cc2000 luti2 z0\.s, zt0, z0\[0\]
|
||||
[^:]+: c0cc201f luti2 z31\.s, zt0, z0\[0\]
|
||||
[^:]+: c0cc23e0 luti2 z0\.s, zt0, z31\[0\]
|
||||
[^:]+: c0cfe000 luti2 z0\.s, zt0, z0\[15\]
|
||||
[^:]+: c08c4000 luti2 {z0\.b-z1\.b}, zt0, z0\[0\]
|
||||
[^:]+: c08c4000 luti2 {z0\.b-z1\.b}, zt0, z0\[0\]
|
||||
[^:]+: c08c401e luti2 {z30\.b-z31\.b}, zt0, z0\[0\]
|
||||
[^:]+: c08c43e0 luti2 {z0\.b-z1\.b}, zt0, z31\[0\]
|
||||
[^:]+: c08fc000 luti2 {z0\.b-z1\.b}, zt0, z0\[7\]
|
||||
[^:]+: c08c5000 luti2 {z0\.h-z1\.h}, zt0, z0\[0\]
|
||||
[^:]+: c08c501e luti2 {z30\.h-z31\.h}, zt0, z0\[0\]
|
||||
[^:]+: c08c53e0 luti2 {z0\.h-z1\.h}, zt0, z31\[0\]
|
||||
[^:]+: c08fd000 luti2 {z0\.h-z1\.h}, zt0, z0\[7\]
|
||||
[^:]+: c08c6000 luti2 {z0\.s-z1\.s}, zt0, z0\[0\]
|
||||
[^:]+: c08c601e luti2 {z30\.s-z31\.s}, zt0, z0\[0\]
|
||||
[^:]+: c08c63e0 luti2 {z0\.s-z1\.s}, zt0, z31\[0\]
|
||||
[^:]+: c08fe000 luti2 {z0\.s-z1\.s}, zt0, z0\[7\]
|
||||
[^:]+: c08c8000 luti2 {z0\.b-z3\.b}, zt0, z0\[0\]
|
||||
[^:]+: c08c8000 luti2 {z0\.b-z3\.b}, zt0, z0\[0\]
|
||||
[^:]+: c08c801c luti2 {z28\.b-z31\.b}, zt0, z0\[0\]
|
||||
[^:]+: c08c83e0 luti2 {z0\.b-z3\.b}, zt0, z31\[0\]
|
||||
[^:]+: c08f8000 luti2 {z0\.b-z3\.b}, zt0, z0\[3\]
|
||||
[^:]+: c08c9000 luti2 {z0\.h-z3\.h}, zt0, z0\[0\]
|
||||
[^:]+: c08c901c luti2 {z28\.h-z31\.h}, zt0, z0\[0\]
|
||||
[^:]+: c08c93e0 luti2 {z0\.h-z3\.h}, zt0, z31\[0\]
|
||||
[^:]+: c08f9000 luti2 {z0\.h-z3\.h}, zt0, z0\[3\]
|
||||
[^:]+: c08ca000 luti2 {z0\.s-z3\.s}, zt0, z0\[0\]
|
||||
[^:]+: c08ca01c luti2 {z28\.s-z31\.s}, zt0, z0\[0\]
|
||||
[^:]+: c08ca3e0 luti2 {z0\.s-z3\.s}, zt0, z31\[0\]
|
||||
[^:]+: c08fa000 luti2 {z0\.s-z3\.s}, zt0, z0\[3\]
|
||||
[^:]+: c0ca0000 luti4 z0\.b, zt0, z0\[0\]
|
||||
[^:]+: c0ca0000 luti4 z0\.b, zt0, z0\[0\]
|
||||
[^:]+: c0ca001f luti4 z31\.b, zt0, z0\[0\]
|
||||
[^:]+: c0ca03e0 luti4 z0\.b, zt0, z31\[0\]
|
||||
[^:]+: c0cbc000 luti4 z0\.b, zt0, z0\[7\]
|
||||
[^:]+: c0ca1000 luti4 z0\.h, zt0, z0\[0\]
|
||||
[^:]+: c0ca1000 luti4 z0\.h, zt0, z0\[0\]
|
||||
[^:]+: c0ca101f luti4 z31\.h, zt0, z0\[0\]
|
||||
[^:]+: c0ca13e0 luti4 z0\.h, zt0, z31\[0\]
|
||||
[^:]+: c0cbd000 luti4 z0\.h, zt0, z0\[7\]
|
||||
[^:]+: c0ca2000 luti4 z0\.s, zt0, z0\[0\]
|
||||
[^:]+: c0ca201f luti4 z31\.s, zt0, z0\[0\]
|
||||
[^:]+: c0ca23e0 luti4 z0\.s, zt0, z31\[0\]
|
||||
[^:]+: c0cbe000 luti4 z0\.s, zt0, z0\[7\]
|
||||
[^:]+: c08a4000 luti4 {z0\.b-z1\.b}, zt0, z0\[0\]
|
||||
[^:]+: c08a4000 luti4 {z0\.b-z1\.b}, zt0, z0\[0\]
|
||||
[^:]+: c08a401e luti4 {z30\.b-z31\.b}, zt0, z0\[0\]
|
||||
[^:]+: c08a43e0 luti4 {z0\.b-z1\.b}, zt0, z31\[0\]
|
||||
[^:]+: c08bc000 luti4 {z0\.b-z1\.b}, zt0, z0\[3\]
|
||||
[^:]+: c08a5000 luti4 {z0\.h-z1\.h}, zt0, z0\[0\]
|
||||
[^:]+: c08a5000 luti4 {z0\.h-z1\.h}, zt0, z0\[0\]
|
||||
[^:]+: c08a501e luti4 {z30\.h-z31\.h}, zt0, z0\[0\]
|
||||
[^:]+: c08a53e0 luti4 {z0\.h-z1\.h}, zt0, z31\[0\]
|
||||
[^:]+: c08bd000 luti4 {z0\.h-z1\.h}, zt0, z0\[3\]
|
||||
[^:]+: c08a6000 luti4 {z0\.s-z1\.s}, zt0, z0\[0\]
|
||||
[^:]+: c08a601e luti4 {z30\.s-z31\.s}, zt0, z0\[0\]
|
||||
[^:]+: c08a63e0 luti4 {z0\.s-z1\.s}, zt0, z31\[0\]
|
||||
[^:]+: c08be000 luti4 {z0\.s-z1\.s}, zt0, z0\[3\]
|
||||
[^:]+: c08a9000 luti4 {z0\.h-z3\.h}, zt0, z0\[0\]
|
||||
[^:]+: c08a9000 luti4 {z0\.h-z3\.h}, zt0, z0\[0\]
|
||||
[^:]+: c08a901c luti4 {z28\.h-z31\.h}, zt0, z0\[0\]
|
||||
[^:]+: c08a93e0 luti4 {z0\.h-z3\.h}, zt0, z31\[0\]
|
||||
[^:]+: c08b9000 luti4 {z0\.h-z3\.h}, zt0, z0\[1\]
|
||||
[^:]+: c08aa000 luti4 {z0\.s-z3\.s}, zt0, z0\[0\]
|
||||
[^:]+: c08aa01c luti4 {z28\.s-z31\.s}, zt0, z0\[0\]
|
||||
[^:]+: c08aa3e0 luti4 {z0\.s-z3\.s}, zt0, z31\[0\]
|
||||
[^:]+: c08ba000 luti4 {z0\.s-z3\.s}, zt0, z0\[1\]
|
||||
124
gas/testsuite/gas/aarch64/sme2-8.s
Normal file
124
gas/testsuite/gas/aarch64/sme2-8.s
Normal file
@ -0,0 +1,124 @@
|
||||
zero { zt0 }
|
||||
ZERO { ZT0 }
|
||||
|
||||
movt x0, zt0[0]
|
||||
MOVT X0, ZT0[0]
|
||||
movt x30, zt0[0]
|
||||
movt xzr, zt0[0]
|
||||
movt x0, zt0[56]
|
||||
movt x9, zt0[24]
|
||||
movt x15, zt0[40]
|
||||
movt x22, zt0[48]
|
||||
|
||||
movt zt0[0], x0
|
||||
MOVT ZT0[0], X0
|
||||
movt zt0[56], x0
|
||||
movt zt0[0], x30
|
||||
movt zt0[0], xzr
|
||||
movt zt0[8], x20
|
||||
movt zt0[16], x25
|
||||
movt zt0[32], x27
|
||||
movt zt0[24], x29
|
||||
|
||||
ldr zt0, [x0]
|
||||
LDR ZT0, [X0]
|
||||
ldr zt0, [x30]
|
||||
ldr zt0, [sp]
|
||||
|
||||
str zt0, [x0]
|
||||
STR ZT0, [X0]
|
||||
str zt0, [x30]
|
||||
str zt0, [sp]
|
||||
|
||||
luti2 z0.b, zt0, z0[0]
|
||||
LUTI2 Z0.B, ZT0, Z0[0]
|
||||
luti2 z31.b, zt0, z0[0]
|
||||
luti2 z0.b, zt0, z31[0]
|
||||
luti2 z0.b, zt0, z0[15]
|
||||
|
||||
luti2 z0.h, zt0, z0[0]
|
||||
luti2 z31.h, zt0, z0[0]
|
||||
luti2 z0.h, zt0, z31[0]
|
||||
luti2 z0.h, zt0, z0[15]
|
||||
|
||||
luti2 z0.s, zt0, z0[0]
|
||||
luti2 z31.s, zt0, z0[0]
|
||||
luti2 z0.s, zt0, z31[0]
|
||||
luti2 z0.s, zt0, z0[15]
|
||||
|
||||
luti2 { z0.b - z1.b }, zt0, z0[0]
|
||||
LUTI2 { Z0.B - Z1.B }, ZT0, Z0[0]
|
||||
luti2 { z30.b - z31.b }, zt0, z0[0]
|
||||
luti2 { z0.b - z1.b }, zt0, z31[0]
|
||||
luti2 { z0.b - z1.b }, zt0, z0[7]
|
||||
|
||||
luti2 { z0.h - z1.h }, zt0, z0[0]
|
||||
luti2 { z30.h - z31.h }, zt0, z0[0]
|
||||
luti2 { z0.h - z1.h }, zt0, z31[0]
|
||||
luti2 { z0.h - z1.h }, zt0, z0[7]
|
||||
|
||||
luti2 { z0.s - z1.s }, zt0, z0[0]
|
||||
luti2 { z30.s - z31.s }, zt0, z0[0]
|
||||
luti2 { z0.s - z1.s }, zt0, z31[0]
|
||||
luti2 { z0.s - z1.s }, zt0, z0[7]
|
||||
|
||||
luti2 { z0.b - z3.b }, zt0, z0[0]
|
||||
LUTI2 { Z0.B - Z3.B }, ZT0, Z0[0]
|
||||
luti2 { z28.b - z31.b }, zt0, z0[0]
|
||||
luti2 { z0.b - z3.b }, zt0, z31[0]
|
||||
luti2 { z0.b - z3.b }, zt0, z0[3]
|
||||
|
||||
luti2 { z0.h - z3.h }, zt0, z0[0]
|
||||
luti2 { z28.h - z31.h }, zt0, z0[0]
|
||||
luti2 { z0.h - z3.h }, zt0, z31[0]
|
||||
luti2 { z0.h - z3.h }, zt0, z0[3]
|
||||
|
||||
luti2 { z0.s - z3.s }, zt0, z0[0]
|
||||
luti2 { z28.s - z31.s }, zt0, z0[0]
|
||||
luti2 { z0.s - z3.s }, zt0, z31[0]
|
||||
luti2 { z0.s - z3.s }, zt0, z0[3]
|
||||
|
||||
luti4 z0.b, zt0, z0[0]
|
||||
LUTI4 Z0.b, ZT0, Z0[0]
|
||||
luti4 z31.b, zt0, z0[0]
|
||||
luti4 z0.b, zt0, z31[0]
|
||||
luti4 z0.b, zt0, z0[7]
|
||||
|
||||
luti4 z0.h, zt0, z0[0]
|
||||
LUTI4 Z0.H, ZT0, Z0[0]
|
||||
luti4 z31.h, zt0, z0[0]
|
||||
luti4 z0.h, zt0, z31[0]
|
||||
luti4 z0.h, zt0, z0[7]
|
||||
|
||||
luti4 z0.s, zt0, z0[0]
|
||||
luti4 z31.s, zt0, z0[0]
|
||||
luti4 z0.s, zt0, z31[0]
|
||||
luti4 z0.s, zt0, z0[7]
|
||||
|
||||
luti4 { z0.b - z1.b }, zt0, z0[0]
|
||||
LUTI4 { Z0.b - Z1.b }, ZT0, Z0[0]
|
||||
luti4 { z30.b - z31.b }, zt0, z0[0]
|
||||
luti4 { z0.b - z1.b }, zt0, z31[0]
|
||||
luti4 { z0.b - z1.b }, zt0, z0[3]
|
||||
|
||||
luti4 { z0.h - z1.h }, zt0, z0[0]
|
||||
LUTI4 { Z0.H - Z1.H }, ZT0, Z0[0]
|
||||
luti4 { z30.h - z31.h }, zt0, z0[0]
|
||||
luti4 { z0.h - z1.h }, zt0, z31[0]
|
||||
luti4 { z0.h - z1.h }, zt0, z0[3]
|
||||
|
||||
luti4 { z0.s - z1.s }, zt0, z0[0]
|
||||
luti4 { z30.s - z31.s }, zt0, z0[0]
|
||||
luti4 { z0.s - z1.s }, zt0, z31[0]
|
||||
luti4 { z0.s - z1.s }, zt0, z0[3]
|
||||
|
||||
luti4 { z0.h - z3.h }, zt0, z0[0]
|
||||
LUTI4 { Z0.H - Z3.H }, ZT0, Z0[0]
|
||||
luti4 { z28.h - z31.h }, zt0, z0[0]
|
||||
luti4 { z0.h - z3.h }, zt0, z31[0]
|
||||
luti4 { z0.h - z3.h }, zt0, z0[1]
|
||||
|
||||
luti4 { z0.s - z3.s }, zt0, z0[0]
|
||||
luti4 { z28.s - z31.s }, zt0, z0[0]
|
||||
luti4 { z0.s - z3.s }, zt0, z31[0]
|
||||
luti4 { z0.s - z3.s }, zt0, z0[1]
|
||||
@ -932,6 +932,14 @@
|
||||
.*: Error: register element index out of range 0 to 63 at operand 2 -- `dup z0\.b,z1\.b\[-1\]'
|
||||
.*: Error: register element index out of range 0 to 63 at operand 2 -- `dup z0\.b,z1\.b\[64\]'
|
||||
.*: Error: constant expression required at operand 2 -- `dup z0\.b,z1\.b\[x0\]'
|
||||
.*: Error: operand mismatch -- `dup z0\.b,z1\[0\]'
|
||||
.*: Info: did you mean this\?
|
||||
.*: Info: dup z0\.b, z1\.b\[0\]
|
||||
.*: Info: other valid variant\(s\):
|
||||
.*: Info: dup z0\.h, z1\.h\[0\]
|
||||
.*: Info: dup z0\.s, z1\.s\[0\]
|
||||
.*: Info: dup z0\.d, z1\.d\[0\]
|
||||
.*: Info: dup z0\.q, z1\.q\[0\]
|
||||
.*: Error: register element index out of range 0 to 31 at operand 2 -- `dup z0\.h,z1\.h\[-1\]'
|
||||
.*: Error: register element index out of range 0 to 31 at operand 2 -- `dup z0\.h,z1\.h\[32\]'
|
||||
.*: Error: constant expression required at operand 2 -- `dup z0\.h,z1\.h\[x0\]'
|
||||
|
||||
@ -1143,6 +1143,7 @@
|
||||
dup z0.b, z1.b[63] // OK
|
||||
dup z0.b, z1.b[64]
|
||||
dup z0.b, z1.b[x0]
|
||||
dup z0.b, z1[0]
|
||||
|
||||
dup z0.h, z1.h[-1]
|
||||
dup z0.h, z1.h[0] // OK
|
||||
|
||||
@ -515,8 +515,17 @@ enum aarch64_opnd
|
||||
AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [<Xn|SP>{, #<imm>, MUL VL}]. */
|
||||
AARCH64_OPND_SME_SM_ZA, /* SME {SM | ZA}. */
|
||||
AARCH64_OPND_SME_PnT_Wm_imm, /* SME <Pn>.<T>[<Wm>, #<imm>]. */
|
||||
AARCH64_OPND_SME_Zn_INDEX1_16, /* Zn[index], bits [9:5] and [16:16]. */
|
||||
AARCH64_OPND_SME_Zn_INDEX2_15, /* Zn[index], bits [9:5] and [16:15]. */
|
||||
AARCH64_OPND_SME_Zn_INDEX2_16, /* Zn[index], bits [9:5] and [17:16]. */
|
||||
AARCH64_OPND_SME_Zn_INDEX3_14, /* Zn[index], bits [9:5] and [16:14]. */
|
||||
AARCH64_OPND_SME_Zn_INDEX3_15, /* Zn[index], bits [9:5] and [17:15]. */
|
||||
AARCH64_OPND_SME_Zn_INDEX4_14, /* Zn[index], bits [9:5] and [17:14]. */
|
||||
AARCH64_OPND_SME_VLxN_10, /* VLx2 or VLx4, in bit 10. */
|
||||
AARCH64_OPND_SME_VLxN_13, /* VLx2 or VLx4, in bit 13. */
|
||||
AARCH64_OPND_SME_ZT0, /* The fixed token zt0/ZT0 (not encoded). */
|
||||
AARCH64_OPND_SME_ZT0_INDEX, /* ZT0[<imm>], bits [14:12]. */
|
||||
AARCH64_OPND_SME_ZT0_LIST, /* { zt0/ZT0 } (not encoded). */
|
||||
AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */
|
||||
AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
|
||||
AARCH64_OPND_MOPS_ADDR_Rd, /* [Rd]!, in bits [0, 4]. */
|
||||
@ -690,6 +699,8 @@ enum aarch64_insn_class
|
||||
sme_mov,
|
||||
sme_ldr,
|
||||
sme_psel,
|
||||
sme_size_12_bhs,
|
||||
sme_size_12_hs,
|
||||
sme_size_22,
|
||||
sme_str,
|
||||
sme_start,
|
||||
|
||||
@ -684,7 +684,7 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 33:
|
||||
case 34:
|
||||
case 35:
|
||||
case 247:
|
||||
case 256:
|
||||
return aarch64_ins_reglane (self, info, code, inst, errors);
|
||||
case 36:
|
||||
return aarch64_ins_reglist (self, info, code, inst, errors);
|
||||
@ -730,11 +730,12 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 193:
|
||||
case 194:
|
||||
case 236:
|
||||
case 244:
|
||||
case 245:
|
||||
case 246:
|
||||
case 250:
|
||||
case 251:
|
||||
case 252:
|
||||
case 253:
|
||||
case 255:
|
||||
case 260:
|
||||
case 261:
|
||||
return aarch64_ins_imm (self, info, code, inst, errors);
|
||||
case 44:
|
||||
case 45:
|
||||
@ -803,6 +804,8 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 107:
|
||||
return aarch64_ins_prfop (self, info, code, inst, errors);
|
||||
case 108:
|
||||
case 252:
|
||||
case 254:
|
||||
return aarch64_ins_none (self, info, code, inst, errors);
|
||||
case 109:
|
||||
return aarch64_ins_hint (self, info, code, inst, errors);
|
||||
@ -915,6 +918,12 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
|
||||
case 234:
|
||||
case 235:
|
||||
case 244:
|
||||
case 245:
|
||||
case 246:
|
||||
case 247:
|
||||
case 248:
|
||||
case 249:
|
||||
return aarch64_ins_simple_index (self, info, code, inst, errors);
|
||||
case 238:
|
||||
case 239:
|
||||
@ -926,9 +935,9 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
|
||||
case 243:
|
||||
return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
|
||||
case 248:
|
||||
case 249:
|
||||
case 250:
|
||||
case 257:
|
||||
case 258:
|
||||
case 259:
|
||||
return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
|
||||
default: assert (0); abort ();
|
||||
}
|
||||
|
||||
@ -404,6 +404,8 @@ aarch64_ins_imm (const aarch64_operand *self, const aarch64_opnd_info *info,
|
||||
imm = info->imm.value;
|
||||
if (operand_need_shift_by_two (self))
|
||||
imm >>= 2;
|
||||
if (operand_need_shift_by_three (self))
|
||||
imm >>= 3;
|
||||
if (operand_need_shift_by_four (self))
|
||||
imm >>= 4;
|
||||
insert_all_fields (self, code, imm);
|
||||
@ -1946,11 +1948,21 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
|
||||
/* The variant is encoded as part of the immediate. */
|
||||
break;
|
||||
|
||||
case sme_size_12_bhs:
|
||||
insert_field (FLD_SME_size_12, &inst->value,
|
||||
aarch64_get_variant (inst), 0);
|
||||
break;
|
||||
|
||||
case sme_size_22:
|
||||
insert_field (FLD_SME_size_22, &inst->value,
|
||||
aarch64_get_variant (inst), 0);
|
||||
break;
|
||||
|
||||
case sme_size_12_hs:
|
||||
insert_field (FLD_SME_size_12, &inst->value,
|
||||
aarch64_get_variant (inst) + 1, 0);
|
||||
break;
|
||||
|
||||
case sve_cpy:
|
||||
insert_fields (&inst->value, aarch64_get_variant (inst),
|
||||
0, 2, FLD_SVE_M_14, FLD_size);
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -702,6 +702,8 @@ aarch64_ext_imm (const aarch64_operand *self, aarch64_opnd_info *info,
|
||||
|
||||
if (operand_need_shift_by_two (self))
|
||||
imm <<= 2;
|
||||
else if (operand_need_shift_by_three (self))
|
||||
imm <<= 3;
|
||||
else if (operand_need_shift_by_four (self))
|
||||
imm <<= 4;
|
||||
|
||||
@ -3072,6 +3074,19 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
|
||||
}
|
||||
break;
|
||||
|
||||
case sme_size_12_bhs:
|
||||
variant = extract_field (FLD_SME_size_12, inst->value, 0);
|
||||
if (variant >= 3)
|
||||
return false;
|
||||
break;
|
||||
|
||||
case sme_size_12_hs:
|
||||
variant = extract_field (FLD_SME_size_12, inst->value, 0);
|
||||
if (variant != 1 && variant != 2)
|
||||
return false;
|
||||
variant -= 1;
|
||||
break;
|
||||
|
||||
case sme_size_22:
|
||||
variant = extract_field (FLD_SME_size_22, inst->value, 0);
|
||||
break;
|
||||
|
||||
@ -268,8 +268,17 @@ const struct aarch64_operand aarch64_operands[] =
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SME_ADDR_RI_U4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm4_0}, "memory offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SME_SM_ZA", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "streaming mode"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SME_PnT_Wm_imm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl}, "Source scalable predicate register with index "},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX1_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm1_16}, "an indexed SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX2_15", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm2_15}, "an indexed SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX2_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm2_16}, "an indexed SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX3_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm3_14}, "an indexed SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX3_15", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm3_15}, "an indexed SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX4_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm4_14}, "an indexed SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SME_VLxN_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_VL_10}, "VLx2 or VLx4"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SME_VLxN_13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_VL_13}, "VLx2 or VLx4"},
|
||||
{AARCH64_OPND_CLASS_SYSTEM, "SME_ZT0", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "ZT0"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SME_ZT0_INDEX", OPD_F_SHIFT_BY_3 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm3_12}, "a ZT0 index"},
|
||||
{AARCH64_OPND_CLASS_SYSTEM, "SME_ZT0_LIST", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "{ ZT0 }"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "TME_UIMM16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16_5}, "a 16-bit unsigned immediate for TME tcancel"},
|
||||
{AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate"},
|
||||
{AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a register destination address with writeback"},
|
||||
|
||||
@ -249,6 +249,7 @@ const aarch64_field fields[] =
|
||||
{ 0, 3 }, /* SME_Zt3: lower 3 bits of Zt, bits [2:0]. */
|
||||
{ 0, 2 }, /* SME_Zt2: lower 2 bits of Zt, bits [1:0]. */
|
||||
{ 23, 1 }, /* SME_i1: immediate field, bit 23. */
|
||||
{ 12, 2 }, /* SME_size_12: bits [13:12]. */
|
||||
{ 22, 2 }, /* SME_size_22: size<1>, size<0> class field, [23:22]. */
|
||||
{ 22, 1 }, /* SME_tszh: immediate and qualifier field, bit 22. */
|
||||
{ 18, 3 }, /* SME_tszl: immediate and qualifier field, bits [20:18]. */
|
||||
@ -318,14 +319,21 @@ const aarch64_field fields[] =
|
||||
{ 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */
|
||||
{ 21, 2 }, /* hw: in move wide constant instructions. */
|
||||
{ 8, 1 }, /* imm1_8: general immediate in bits [8]. */
|
||||
{ 16, 1 }, /* imm1_16: general immediate in bits [16]. */
|
||||
{ 8, 2 }, /* imm2_8: general immediate in bits [9:8]. */
|
||||
{ 15, 2 }, /* imm2_15: 2-bit immediate, bits [16:15] */
|
||||
{ 16, 2 }, /* imm2_16: 2-bit immediate, bits [17:16] */
|
||||
{ 0, 3 }, /* imm3_0: general immediate in bits [2:0]. */
|
||||
{ 5, 3 }, /* imm3_5: general immediate in bits [7:5]. */
|
||||
{ 10, 3 }, /* imm3_10: in add/sub extended reg instructions. */
|
||||
{ 12, 3 }, /* imm3_12: general immediate in bits [14:12]. */
|
||||
{ 14, 3 }, /* imm3_14: general immediate in bits [16:14]. */
|
||||
{ 15, 3 }, /* imm3_15: general immediate in bits [17:15]. */
|
||||
{ 0, 4 }, /* imm4_0: in rmif instructions. */
|
||||
{ 5, 4 }, /* imm4_5: in SME instructions. */
|
||||
{ 10, 4 }, /* imm4_10: in adddg/subg instructions. */
|
||||
{ 11, 4 }, /* imm4_11: in advsimd ext and advsimd ins instructions. */
|
||||
{ 14, 4 }, /* imm4_14: general immediate in bits [17:14]. */
|
||||
{ 16, 5 }, /* imm5: in conditional compare (immediate) instructions. */
|
||||
{ 10, 6 }, /* imm6_10: in add/sub reg shifted instructions. */
|
||||
{ 15, 6 }, /* imm6_15: in rmif instructions. */
|
||||
@ -1744,6 +1752,18 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
|
||||
return 0;
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_SME_Zn_INDEX1_16:
|
||||
case AARCH64_OPND_SME_Zn_INDEX2_15:
|
||||
case AARCH64_OPND_SME_Zn_INDEX2_16:
|
||||
case AARCH64_OPND_SME_Zn_INDEX3_14:
|
||||
case AARCH64_OPND_SME_Zn_INDEX3_15:
|
||||
case AARCH64_OPND_SME_Zn_INDEX4_14:
|
||||
size = get_operand_fields_width (get_operand_from_code (type)) - 5;
|
||||
if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31,
|
||||
0, (1 << size) - 1))
|
||||
return 0;
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_SME_PnT_Wm_imm:
|
||||
size = aarch64_get_qualifier_esize (opnd->qualifier);
|
||||
max_value = 16 / size - 1;
|
||||
@ -2862,6 +2882,20 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
|
||||
}
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_SME_ZT0_INDEX:
|
||||
if (!value_in_range_p (opnd->imm.value, 0, 56))
|
||||
{
|
||||
set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, 56);
|
||||
return 0;
|
||||
}
|
||||
if (opnd->imm.value % 8 != 0)
|
||||
{
|
||||
set_other_error (mismatch_detail, idx,
|
||||
_("byte index must be a multiple of 8"));
|
||||
return 0;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
@ -3867,9 +3901,17 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
|
||||
case AARCH64_OPND_SVE_Zm4_11_INDEX:
|
||||
case AARCH64_OPND_SVE_Zm4_INDEX:
|
||||
case AARCH64_OPND_SVE_Zn_INDEX:
|
||||
case AARCH64_OPND_SME_Zn_INDEX1_16:
|
||||
case AARCH64_OPND_SME_Zn_INDEX2_15:
|
||||
case AARCH64_OPND_SME_Zn_INDEX2_16:
|
||||
case AARCH64_OPND_SME_Zn_INDEX3_14:
|
||||
case AARCH64_OPND_SME_Zn_INDEX3_15:
|
||||
case AARCH64_OPND_SME_Zn_INDEX4_14:
|
||||
snprintf (buf, size, "%s[%s]",
|
||||
style_reg (styler, "z%d.%s", opnd->reglane.regno,
|
||||
aarch64_get_qualifier_name (opnd->qualifier)),
|
||||
(opnd->qualifier == AARCH64_OPND_QLF_NIL
|
||||
? style_reg (styler, "z%d", opnd->reglane.regno)
|
||||
: style_reg (styler, "z%d.%s", opnd->reglane.regno,
|
||||
aarch64_get_qualifier_name (opnd->qualifier))),
|
||||
style_imm (styler, "%" PRIi64, opnd->reglane.index));
|
||||
break;
|
||||
|
||||
@ -4450,6 +4492,19 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
|
||||
snprintf (buf, size, "%s", style_sub_mnem (styler, "csync"));
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_SME_ZT0:
|
||||
snprintf (buf, size, "%s", style_reg (styler, "zt0"));
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_SME_ZT0_INDEX:
|
||||
snprintf (buf, size, "%s[%s]", style_reg (styler, "zt0"),
|
||||
style_imm (styler, "%d", (int) opnd->imm.value));
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_SME_ZT0_LIST:
|
||||
snprintf (buf, size, "{%s}", style_reg (styler, "zt0"));
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_BTI_TARGET:
|
||||
if ((HINT_FLAG (opnd->hint_option->value) & HINT_OPD_F_NOPRINT) == 0)
|
||||
snprintf (buf, size, "%s",
|
||||
|
||||
@ -70,6 +70,7 @@ enum aarch64_field_kind
|
||||
FLD_SME_Zt3,
|
||||
FLD_SME_Zt2,
|
||||
FLD_SME_i1,
|
||||
FLD_SME_size_12,
|
||||
FLD_SME_size_22,
|
||||
FLD_SME_tszh,
|
||||
FLD_SME_tszl,
|
||||
@ -139,14 +140,21 @@ enum aarch64_field_kind
|
||||
FLD_defgh,
|
||||
FLD_hw,
|
||||
FLD_imm1_8,
|
||||
FLD_imm1_16,
|
||||
FLD_imm2_8,
|
||||
FLD_imm2_15,
|
||||
FLD_imm2_16,
|
||||
FLD_imm3_0,
|
||||
FLD_imm3_5,
|
||||
FLD_imm3_10,
|
||||
FLD_imm3_12,
|
||||
FLD_imm3_14,
|
||||
FLD_imm3_15,
|
||||
FLD_imm4_0,
|
||||
FLD_imm4_5,
|
||||
FLD_imm4_10,
|
||||
FLD_imm4_11,
|
||||
FLD_imm4_14,
|
||||
FLD_imm5,
|
||||
FLD_imm6_10,
|
||||
FLD_imm6_15,
|
||||
@ -242,7 +250,10 @@ verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma,
|
||||
#define OPD_F_OD_MASK 0x000001e0 /* Operand-dependent data. */
|
||||
#define OPD_F_OD_LSB 5
|
||||
#define OPD_F_NO_ZR 0x00000200 /* ZR index not allowed. */
|
||||
#define OPD_F_SHIFT_BY_4 0x00000400 /* Need to left shift the field
|
||||
#define OPD_F_SHIFT_BY_3 0x00000400 /* Need to left shift the field
|
||||
value by 3 to get the value
|
||||
of an immediate operand. */
|
||||
#define OPD_F_SHIFT_BY_4 0x00000800 /* Need to left shift the field
|
||||
value by 4 to get the value
|
||||
of an immediate operand. */
|
||||
|
||||
@ -329,6 +340,12 @@ operand_need_shift_by_two (const aarch64_operand *operand)
|
||||
return (operand->flags & OPD_F_SHIFT_BY_2) != 0;
|
||||
}
|
||||
|
||||
static inline bool
|
||||
operand_need_shift_by_three (const aarch64_operand *operand)
|
||||
{
|
||||
return (operand->flags & OPD_F_SHIFT_BY_3) != 0;
|
||||
}
|
||||
|
||||
static inline bool
|
||||
operand_need_shift_by_four (const aarch64_operand *operand)
|
||||
{
|
||||
|
||||
@ -1755,6 +1755,10 @@
|
||||
{ \
|
||||
QLF3(NIL,NIL,S_S), \
|
||||
}
|
||||
#define OP_SVE_UX \
|
||||
{ \
|
||||
QLF2(NIL,X), \
|
||||
}
|
||||
#define OP_SVE_VMR_BHSD \
|
||||
{ \
|
||||
QLF3(S_B,P_M,W), \
|
||||
@ -1905,6 +1909,12 @@
|
||||
QLF3(S_S,NIL,W), \
|
||||
QLF3(S_D,NIL,X), \
|
||||
}
|
||||
#define OP_SVE_VUU_BHS \
|
||||
{ \
|
||||
QLF3(S_B,NIL,NIL), \
|
||||
QLF3(S_H,NIL,NIL), \
|
||||
QLF3(S_S,NIL,NIL), \
|
||||
}
|
||||
#define OP_SVE_VUU_BHSD \
|
||||
{ \
|
||||
QLF3(S_B,NIL,NIL), \
|
||||
@ -1919,6 +1929,11 @@
|
||||
QLF4(S_S,NIL,S_S,S_S), \
|
||||
QLF4(S_D,NIL,S_D,S_D), \
|
||||
}
|
||||
#define OP_SVE_VUU_HS \
|
||||
{ \
|
||||
QLF3(S_H,NIL,NIL), \
|
||||
QLF3(S_S,NIL,NIL), \
|
||||
}
|
||||
#define OP_SVE_VUVV_HSD \
|
||||
{ \
|
||||
QLF4(S_H,NIL,S_H,S_H), \
|
||||
@ -5375,6 +5390,13 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
||||
SME2_INSN ("ldnt1w", 0xa000c001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0),
|
||||
SME2_INSN ("ldnt1w", 0xa1004008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0),
|
||||
SME2_INSN ("ldnt1w", 0xa100c008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0),
|
||||
SME2_INSN ("ldr", 0xe11f8000, 0xfffffc1f, sme_misc, 0, OP2 (SME_ZT0, SIMD_ADDR_SIMPLE), {}, 0, 0),
|
||||
SME2_INSN ("luti2", 0xc0cc0000, 0xfffc0c00, sme_size_12_bhs, 0, OP3 (SVE_Zd, SME_ZT0, SME_Zn_INDEX4_14), OP_SVE_VUU_BHS, 0, 0),
|
||||
SME2_INSN ("luti2", 0xc08c4000, 0xfffc4c01, sme_size_12_bhs, 0, OP3 (SME_Zdnx2, SME_ZT0, SME_Zn_INDEX3_15), OP_SVE_VUU_BHS, 0, 0),
|
||||
SME2_INSN ("luti2", 0xc08c8000, 0xfffccc03, sme_size_12_bhs, 0, OP3 (SME_Zdnx4, SME_ZT0, SME_Zn_INDEX2_16), OP_SVE_VUU_BHS, 0, 0),
|
||||
SME2_INSN ("luti4", 0xc0ca0000, 0xfffe0c00, sme_size_12_bhs, 0, OP3 (SVE_Zd, SME_ZT0, SME_Zn_INDEX3_14), OP_SVE_VUU_BHS, 0, 0),
|
||||
SME2_INSN ("luti4", 0xc08a4000, 0xfffe4c01, sme_size_12_bhs, 0, OP3 (SME_Zdnx2, SME_ZT0, SME_Zn_INDEX2_15), OP_SVE_VUU_BHS, 0, 0),
|
||||
SME2_INSN ("luti4", 0xc08a8000, 0xfffecc03, sme_size_12_hs, 0, OP3 (SME_Zdnx4, SME_ZT0, SME_Zn_INDEX1_16), OP_SVE_VUU_HS, 0, 0),
|
||||
SME2_INSN ("mov", 0xc0060800, 0xffff9f01, sme2_mov, 0, OP2 (SME_Zdnx2, SME_ZA_array_off3_5), OP_SVE_VV_BHSD, F_OD (2), 0),
|
||||
SME2_INSN ("mov", 0xc0060c00, 0xffff9f03, sme2_mov, 0, OP2 (SME_Zdnx4, SME_ZA_array_off3_5), OP_SVE_VV_BHSD, F_OD (4), 0),
|
||||
SME2_INSN ("mov", 0xc0060000, 0xff3f1f01, sme_size_22, 0, OP2 (SME_Zdnx2, SME_ZA_HV_idx_srcxN), OP_SVE_VV_BHSDQ, F_OD (2), 0),
|
||||
@ -5391,6 +5413,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
||||
SME2_INSN ("mova", 0xc0040c00, 0xffff9c78, sme2_mov, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VV_BHSD, F_OD (4), 0),
|
||||
SME2_INSN ("mova", 0xc0040000, 0xff3f1c38, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx2), OP_SVE_VV_BHSDQ, F_OD (2), 0),
|
||||
SME2_INSN ("mova", 0xc0040400, 0xff3f1c78, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx4), OP_SVE_VV_BHSDQ, F_OD (4), 0),
|
||||
SME2_INSN ("movt", 0xc04e03e0, 0xffff8fe0, sme_misc, 0, OP2 (SME_ZT0_INDEX, Rt), OP_SVE_UX, 0, 0),
|
||||
SME2_INSN ("movt", 0xc04c03e0, 0xffff8fe0, sme_misc, 0, OP2 (Rt, SME_ZT0_INDEX), OP_SVE_XU, 0, 0),
|
||||
SME2_INSN ("pext", 0x25207010, 0xff3ffc10, sme_size_22, 0, OP2 (SVE_Pd, SME_PNn3_INDEX2), OP_SVE_VU_BHSD, 0, 0),
|
||||
SME2_INSN ("pext", 0x25207410, 0xff3ffe10, sme_size_22, 0, OP2 (SME_PdxN, SME_PNn3_INDEX1), OP_SVE_VU_BHSD, F_OD (2), 0),
|
||||
SME2_INSN ("ptrue", 0x25207810, 0xff3ffff8, sme_size_22, 0, OP1 (SME_PNd3), OP_SVE_V_BHSD, 0, 0),
|
||||
@ -5460,6 +5484,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
||||
SME2_INSN ("stnt1w", 0xa020c001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
|
||||
SME2_INSN ("stnt1w", 0xa1204008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
|
||||
SME2_INSN ("stnt1w", 0xa120c008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
|
||||
SME2_INSN ("str", 0xe13f8000, 0xfffffc1f, sme_misc, 0, OP2 (SME_ZT0, SIMD_ADDR_SIMPLE), {}, 0, 0),
|
||||
SME2_INSN ("whilege", 0x25204010, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
|
||||
SME2_INSN ("whilegt", 0x25204018, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
|
||||
SME2_INSN ("whilehi", 0x25204818, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
|
||||
@ -5468,6 +5493,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
||||
SME2_INSN ("whilelo", 0x25204c10, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
|
||||
SME2_INSN ("whilels", 0x25204c18, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
|
||||
SME2_INSN ("whilelt", 0x25204410, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
|
||||
SME2_INSN ("zero", 0xc0480001, 0xffffffff, sme_misc, 0, OP1 (SME_ZT0_LIST), {}, 0, 0),
|
||||
|
||||
/* SIMD Dot Product (optional in v8.2-A). */
|
||||
DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),
|
||||
@ -6178,10 +6204,26 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
||||
Y(SVE_REG, sme_pred_reg_with_index, "SME_PnT_Wm_imm", 0, \
|
||||
F(FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl), \
|
||||
"Source scalable predicate register with index ") \
|
||||
Y(SVE_REG, simple_index, "SME_Zn_INDEX1_16", 0, \
|
||||
F(FLD_SVE_Zn, FLD_imm1_16), "an indexed SVE vector register") \
|
||||
Y(SVE_REG, simple_index, "SME_Zn_INDEX2_15", 0, \
|
||||
F(FLD_SVE_Zn, FLD_imm2_15), "an indexed SVE vector register") \
|
||||
Y(SVE_REG, simple_index, "SME_Zn_INDEX2_16", 0, \
|
||||
F(FLD_SVE_Zn, FLD_imm2_16), "an indexed SVE vector register") \
|
||||
Y(SVE_REG, simple_index, "SME_Zn_INDEX3_14", 0, \
|
||||
F(FLD_SVE_Zn, FLD_imm3_14), "an indexed SVE vector register") \
|
||||
Y(SVE_REG, simple_index, "SME_Zn_INDEX3_15", 0, \
|
||||
F(FLD_SVE_Zn, FLD_imm3_15), "an indexed SVE vector register") \
|
||||
Y(SVE_REG, simple_index, "SME_Zn_INDEX4_14", 0, \
|
||||
F(FLD_SVE_Zn, FLD_imm4_14), "an indexed SVE vector register") \
|
||||
Y(IMMEDIATE, imm, "SME_VLxN_10", 0, F(FLD_SME_VL_10), \
|
||||
"VLx2 or VLx4") \
|
||||
Y(IMMEDIATE, imm, "SME_VLxN_13", 0, F(FLD_SME_VL_13), \
|
||||
"VLx2 or VLx4") \
|
||||
Y(SYSTEM, none, "SME_ZT0", 0, F (), "ZT0") \
|
||||
Y(IMMEDIATE, imm, "SME_ZT0_INDEX", OPD_F_SHIFT_BY_3, \
|
||||
F (FLD_imm3_12), "a ZT0 index") \
|
||||
Y(SYSTEM, none, "SME_ZT0_LIST", 0, F (), "{ ZT0 }") \
|
||||
Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD_imm16_5), \
|
||||
"a 16-bit unsigned immediate for TME tcancel") \
|
||||
Y(SIMD_ELEMENT, reglane, "SM3_IMM2", 0, F(FLD_SM3_imm2), \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user