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2006-11-14 Maxim Grigoriev <maxim@tensilica.com>
* NEWS: New port to Xtensa. * Makefile.in: Add dependencies for Xtensa files. * configure.tgt (xtensa*, xtensa*-*-elf*): New. * configure.host (xtensa*-*-elf*): New. * config/xtensa/xtensa.mt: New file. * xtensa-config.c: New file. * xtensa-tdep.h: New file. * xtensa-tdep.c: New file. 2006-11-14 Maxim Grigoriev <maxim@tensilica.com> * gdb.texinfo (Contributors): Add contributors of Xtensa port.
This commit is contained in:
Daniel Jacobowitz
parent
427c3a89d3
commit
ca3bf3bdbe
@ -1,3 +1,14 @@
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2006-11-14 Maxim Grigoriev <maxim@tensilica.com>
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* NEWS: New port to Xtensa.
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* Makefile.in: Add dependencies for Xtensa files.
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* configure.tgt (xtensa*, xtensa*-*-elf*): New.
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* configure.host (xtensa*-*-elf*): New.
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* config/xtensa/xtensa.mt: New file.
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* xtensa-config.c: New file.
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* xtensa-tdep.h: New file.
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* xtensa-tdep.c: New file.
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2006-11-14 Daniel Jacobowitz <dan@codesourcery.com>
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* remote.c (set_remote_cmd): Call help_list.
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@ -825,6 +825,7 @@ wince_stub_h = wince-stub.h
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wrapper_h = wrapper.h $(gdb_h)
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xcoffsolib_h = xcoffsolib.h
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xml_support_h = xml-support.h $(gdb_expat_h)
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xtensa_tdep_h = xtensa-tdep.h
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#
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# gdb/cli/ headers
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@ -1500,7 +1501,8 @@ ALLDEPFILES = \
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vax-nat.c vax-tdep.c vaxbsd-nat.c vaxnbsd-tdep.c \
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win32-nat.c \
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xcoffread.c xcoffsolib.c \
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xstormy16-tdep.c
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xstormy16-tdep.c \
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xtensa-tdep.c xtensa-config.c
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# Some files need explicit build rules (due to -Werror problems) or due
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# to sub-directory fun 'n' games.
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@ -2863,6 +2865,16 @@ xstormy16-tdep.o: xstormy16-tdep.c $(defs_h) $(frame_h) $(frame_base_h) \
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$(gdbcmd_h) $(gdbcore_h) $(value_h) $(dis_asm_h) $(inferior_h) \
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$(gdb_string_h) $(gdb_assert_h) $(arch_utils_h) $(floatformat_h) \
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$(regcache_h) $(doublest_h) $(osabi_h) $(objfiles_h)
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xtensa-linux-tdep.o: xtensa-linux-tdep.c $(defs_h) $(inferior_h) \
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$(gdbcore_h) $(regcache_h) $(osabi_h) $(gdb_string_h) \
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$(xtensa_tdep_h) $(xtensa_linux_tdep_h)
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xtensa-tdep.o: xtensa-tdep.c $(defs_h) $(doublest_h) $(frame_h) \
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$(frame_unwind_h) $(frame_base_h) $(inferior_h) $(symtab_h) \
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$(value_h) $(gdbcmd_h) $(gdbcore_h) $(dis_asm_h) $(symfile_h) \
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$(objfiles_h) $(gdb_string_h) $(linespec_h) $(regcache_h) \
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$(reggroups_h) $(arch_utils_h) $(osabi_h) $(block_h) $(gdb_assert_h) \
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$(elf_bfd_h) $(xtensa_tdep_h) $(dwarf2_frame_h)
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xtensa-config.o: $(defs_h) $(xtensa_tdep_h)
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#
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# gdb/cli/ dependencies
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4
gdb/NEWS
4
gdb/NEWS
@ -3,6 +3,10 @@
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*** Changes since GDB 6.5
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* New targets
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Xtensa xtensa-elf
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* GDB can now be configured as a cross-debugger targeting native Windows
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(mingw32) or Cygwin. It can communicate with a remote debugging stub
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running on a Windows system over TCP/IP to debug Windows programs.
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2
gdb/config/xtensa/xtensa.mt
Normal file
2
gdb/config/xtensa/xtensa.mt
Normal file
@ -0,0 +1,2 @@
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# Target: Tensilica Xtensa processors
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TDEPFILES= xtensa-tdep.o xtensa-config.o
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@ -28,6 +28,7 @@ sh*) gdb_host_cpu=sh ;;
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x86_64*) gdb_host_cpu=i386 ;;
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xscale*) gdb_host_cpu=arm ;;
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m32r*) gdb_host_cpu=m32r ;;
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xtensa*) gdb_host_cpu=xtensa ;;
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*) gdb_host_cpu=$host_cpu ;;
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esac
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@ -156,6 +157,8 @@ x86_64-*-openbsd*) gdb_host=obsd64 ;;
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m32r*-*-linux*) gdb_host=linux ;;
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xtensa*-*-linux*) gdb_host=linux ;;
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esac
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@ -28,6 +28,7 @@ sh*) gdb_target_cpu=sh ;;
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strongarm*) gdb_target_cpu=arm ;;
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xscale*) gdb_target_cpu=arm ;;
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x86_64*) gdb_target_cpu=i386 ;;
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xtensa*) gdb_target_cpu=xtensa ;;
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*) gdb_target_cpu=$target_cpu ;;
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esac
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@ -224,6 +225,8 @@ x86_64-*-netbsd* | x86_64-*-knetbsd*-gnu)
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gdb_target=nbsd64 ;;
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x86_64-*-openbsd*) gdb_target=obsd64 ;;
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xtensa*) gdb_target=xtensa ;;
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esac
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# map target onto default OS ABI
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@ -1,3 +1,7 @@
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2006-11-14 Maxim Grigoriev <maxim@tensilica.com>
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* gdb.texinfo (Contributors): Add contributors of Xtensa port.
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2006-11-14 Daniel Jacobowitz <dan@codesourcery.com>
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* gdb.texinfo (Remote configuration): Rewrite documentation for
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@ -497,6 +497,11 @@ Jacobowitz, Jeff Johnston, Mark Kettenis, Theodore A. Roth, Kei
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Sakamoto, Yoshinori Sato, Michael Snyder, Corinna Vinschen, and Ulrich
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Weigand.
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Christian Zankel, Ross Morley, Bob Wilson, and Maxim Grigoriev from
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Tensilica, Inc.@: contributed support for Xtensa processors. Others
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who have worked on the Xtensa port of @value{GDBN} in the past include
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Steve Tjiang, John Newlin, and Scott Foehner.
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@node Sample Session
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@chapter A Sample @value{GDBN} Session
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563
gdb/xtensa-config.c
Normal file
563
gdb/xtensa-config.c
Normal file
@ -0,0 +1,563 @@
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/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
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Copyright (C) 2003, 2005, 2006 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor,
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Boston, MA 02110-1301, USA. */
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#include "xtensa-config.h"
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#include "defs.h"
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#include "gdbarch.h"
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#include "xtensa-tdep.h"
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#include "gdbtypes.h"
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/* Check version of configuration file. */
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#define XTENSA_CONFIG_VERSION 0x60
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#if XTENSA_TDEP_VERSION != XTENSA_CONFIG_VERSION
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#warning "xtensa-config.c version mismatch!"
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#endif
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/* Return the byte order from the configuration.
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We need this function, because the byte order is needed even
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before the target structure (tdep) has been set up. */
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int
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xtensa_config_byte_order (void)
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{
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return XCHAL_HAVE_BE ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
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}
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/* This routine returns the predefined architecture-dependent
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parameter structure (tdep) and register map. */
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struct gdbarch_tdep xtensa_tdep;
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struct gdbarch_tdep *
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xtensa_config_tdep (struct gdbarch_info *info)
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{
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return &xtensa_tdep;
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}
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/* Masked registers. */
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const int mask0[] = { 1, 96, 0, 4 };
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const int mask1[] = { 1, 96, 5, 1 };
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const int mask2[] = { 1, 96, 18, 1 };
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const int mask3[] = { 1, 96, 6, 2 };
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const int mask4[] = { 1, 96, 4, 1 };
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const int mask5[] = { 1, 96, 16, 2 };
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const int mask6[] = { 1, 96, 8, 4 };
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const int mask7[] = { 1, 95, 12, 20 };
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const int mask8[] = { 1, 95, 0, 1 };
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const int mask9[] = { 1, 108, 8, 4 };
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const int mask10[] = { 1, 109, 24, 8 };
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const int mask11[] = { 1, 109, 16, 8 };
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const int mask12[] = { 1, 109, 8, 8 };
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const int mask13[] = { 1, 110, 16, 2 };
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const int mask14[] = { 1, 111, 16, 2 };
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const int mask15[] = { 1, 67, 22, 10 };
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/* Register map. */
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xtensa_register_t rmap[] =
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{
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{ /* 0000 */ "ar0", 0, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x00000100, 0x0006, 0,
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0, 0 },
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{ /* 0001 */ "ar1", 4, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x00000101, 0x0006, 0,
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0, 0 },
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{ /* 0002 */ "ar2", 8, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x00000102, 0x0006, 0,
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0, 0 },
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{ /* 0003 */ "ar3", 12, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x00000103, 0x0006, 0,
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0, 0 },
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{ /* 0004 */ "ar4", 16, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x00000104, 0x0006, 0,
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0, 0 },
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{ /* 0005 */ "ar5", 20, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x00000105, 0x0006, 0,
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0, 0 },
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{ /* 0006 */ "ar6", 24, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x00000106, 0x0006, 0,
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0, 0 },
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{ /* 0007 */ "ar7", 28, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x00000107, 0x0006, 0,
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0, 0 },
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{ /* 0008 */ "ar8", 32, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x00000108, 0x0006, 0,
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0, 0 },
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{ /* 0009 */ "ar9", 36, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x00000109, 0x0006, 0,
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0, 0 },
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{ /* 0010 */ "ar10", 40, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x0000010a, 0x0006, 0,
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0, 0 },
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{ /* 0011 */ "ar11", 44, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x0000010b, 0x0006, 0,
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0, 0 },
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{ /* 0012 */ "ar12", 48, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x0000010c, 0x0006, 0,
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0, 0 },
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{ /* 0013 */ "ar13", 52, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x0000010d, 0x0006, 0,
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0, 0 },
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{ /* 0014 */ "ar14", 56, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x0000010e, 0x0006, 0,
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0, 0 },
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{ /* 0015 */ "ar15", 60, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x0000010f, 0x0006, 0,
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0, 0 },
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{ /* 0016 */ "ar16", 64, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x00000110, 0x0006, 0,
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0, 0 },
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{ /* 0017 */ "ar17", 68, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x00000111, 0x0006, 0,
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0, 0 },
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{ /* 0018 */ "ar18", 72, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x00000112, 0x0006, 0,
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0, 0 },
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{ /* 0019 */ "ar19", 76, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x00000113, 0x0006, 0,
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0, 0 },
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{ /* 0020 */ "ar20", 80, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x00000114, 0x0006, 0,
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0, 0 },
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{ /* 0021 */ "ar21", 84, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x00000115, 0x0006, 0,
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0, 0 },
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{ /* 0022 */ "ar22", 88, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x00000116, 0x0006, 0,
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0, 0 },
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{ /* 0023 */ "ar23", 92, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x00000117, 0x0006, 0,
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0, 0 },
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{ /* 0024 */ "ar24", 96, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x00000118, 0x0006, 0,
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0, 0 },
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{ /* 0025 */ "ar25", 100, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x00000119, 0x0006, 0,
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0, 0 },
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{ /* 0026 */ "ar26", 104, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x0000011a, 0x0006, 0,
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0, 0 },
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{ /* 0027 */ "ar27", 108, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x0000011b, 0x0006, 0,
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0, 0 },
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{ /* 0028 */ "ar28", 112, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x0000011c, 0x0006, 0,
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0, 0 },
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{ /* 0029 */ "ar29", 116, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x0000011d, 0x0006, 0,
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0, 0 },
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{ /* 0030 */ "ar30", 120, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x0000011e, 0x0006, 0,
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0, 0 },
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{ /* 0031 */ "ar31", 124, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x0000011f, 0x0006, 0,
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0, 0 },
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{ /* 0032 */ "ar32", 128, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x00000120, 0x0006, 0,
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0, 0 },
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{ /* 0033 */ "ar33", 132, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x00000121, 0x0006, 0,
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0, 0 },
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{ /* 0034 */ "ar34", 136, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x00000122, 0x0006, 0,
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0, 0 },
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{ /* 0035 */ "ar35", 140, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x00000123, 0x0006, 0,
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0, 0 },
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{ /* 0036 */ "ar36", 144, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x00000124, 0x0006, 0,
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0, 0 },
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{ /* 0037 */ "ar37", 148, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x00000125, 0x0006, 0,
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0, 0 },
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{ /* 0038 */ "ar38", 152, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x00000126, 0x0006, 0,
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0, 0 },
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{ /* 0039 */ "ar39", 156, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x00000127, 0x0006, 0,
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0, 0 },
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{ /* 0040 */ "ar40", 160, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x00000128, 0x0006, 0,
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0, 0 },
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{ /* 0041 */ "ar41", 164, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x00000129, 0x0006, 0,
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0, 0 },
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{ /* 0042 */ "ar42", 168, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x0000012a, 0x0006, 0,
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0, 0 },
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{ /* 0043 */ "ar43", 172, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x0000012b, 0x0006, 0,
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0, 0 },
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{ /* 0044 */ "ar44", 176, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x0000012c, 0x0006, 0,
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0, 0 },
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{ /* 0045 */ "ar45", 180, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x0000012d, 0x0006, 0,
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0, 0 },
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{ /* 0046 */ "ar46", 184, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x0000012e, 0x0006, 0,
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0, 0 },
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{ /* 0047 */ "ar47", 188, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x0000012f, 0x0006, 0,
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0, 0 },
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{ /* 0048 */ "ar48", 192, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x00000130, 0x0006, 0,
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0, 0 },
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{ /* 0049 */ "ar49", 196, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x00000131, 0x0006, 0,
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0, 0 },
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{ /* 0050 */ "ar50", 200, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x00000132, 0x0006, 0,
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0, 0 },
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{ /* 0051 */ "ar51", 204, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x00000133, 0x0006, 0,
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0, 0 },
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{ /* 0052 */ "ar52", 208, xtRegisterTypeArRegfile, 0x2, 0,
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32, 4, 4, 0x00000134, 0x0006, 0,
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0, 0 },
|
||||
{ /* 0053 */ "ar53", 212, xtRegisterTypeArRegfile, 0x2, 0,
|
||||
32, 4, 4, 0x00000135, 0x0006, 0,
|
||||
0, 0 },
|
||||
{ /* 0054 */ "ar54", 216, xtRegisterTypeArRegfile, 0x2, 0,
|
||||
32, 4, 4, 0x00000136, 0x0006, 0,
|
||||
0, 0 },
|
||||
{ /* 0055 */ "ar55", 220, xtRegisterTypeArRegfile, 0x2, 0,
|
||||
32, 4, 4, 0x00000137, 0x0006, 0,
|
||||
0, 0 },
|
||||
{ /* 0056 */ "ar56", 224, xtRegisterTypeArRegfile, 0x2, 0,
|
||||
32, 4, 4, 0x00000138, 0x0006, 0,
|
||||
0, 0 },
|
||||
{ /* 0057 */ "ar57", 228, xtRegisterTypeArRegfile, 0x2, 0,
|
||||
32, 4, 4, 0x00000139, 0x0006, 0,
|
||||
0, 0 },
|
||||
{ /* 0058 */ "ar58", 232, xtRegisterTypeArRegfile, 0x2, 0,
|
||||
32, 4, 4, 0x0000013a, 0x0006, 0,
|
||||
0, 0 },
|
||||
{ /* 0059 */ "ar59", 236, xtRegisterTypeArRegfile, 0x2, 0,
|
||||
32, 4, 4, 0x0000013b, 0x0006, 0,
|
||||
0, 0 },
|
||||
{ /* 0060 */ "ar60", 240, xtRegisterTypeArRegfile, 0x2, 0,
|
||||
32, 4, 4, 0x0000013c, 0x0006, 0,
|
||||
0, 0 },
|
||||
{ /* 0061 */ "ar61", 244, xtRegisterTypeArRegfile, 0x2, 0,
|
||||
32, 4, 4, 0x0000013d, 0x0006, 0,
|
||||
0, 0 },
|
||||
{ /* 0062 */ "ar62", 248, xtRegisterTypeArRegfile, 0x2, 0,
|
||||
32, 4, 4, 0x0000013e, 0x0006, 0,
|
||||
0, 0 },
|
||||
{ /* 0063 */ "ar63", 252, xtRegisterTypeArRegfile, 0x2, 0,
|
||||
32, 4, 4, 0x0000013f, 0x0006, 0,
|
||||
0, 0 },
|
||||
{ /* 0064 */ "lbeg", 256, xtRegisterTypeSpecialReg, 0x1100, 0,
|
||||
32, 4, 4, 0x00000200, 0x0006, 0,
|
||||
0, 0 },
|
||||
{ /* 0065 */ "lend", 260, xtRegisterTypeSpecialReg, 0x1100, 0,
|
||||
32, 4, 4, 0x00000201, 0x0006, 0,
|
||||
0, 0 },
|
||||
{ /* 0066 */ "lcount", 264, xtRegisterTypeSpecialReg, 0x1100, 0,
|
||||
32, 4, 4, 0x00000202, 0x0006, 0,
|
||||
0, 0 },
|
||||
{ /* 0067 */ "ptevaddr", 268, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
32, 4, 4, 0x00000253, 0x0007, 0,
|
||||
0, 0 },
|
||||
{ /* 0068 */ "ddr", 272, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
32, 4, 4, 0x00000268, 0x0007, 0,
|
||||
0, 0 },
|
||||
{ /* 0069 */ "interrupt", 276, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
17, 4, 4, 0x000002e2, 0x000b, 0,
|
||||
0, 0 },
|
||||
{ /* 0070 */ "intset", 280, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
17, 4, 4, 0x000002e2, 0x000d, 0,
|
||||
0, 0 },
|
||||
{ /* 0071 */ "intclear", 284, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
17, 4, 4, 0x000002e3, 0x000d, 0,
|
||||
0, 0 },
|
||||
{ /* 0072 */ "ccount", 288, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
32, 4, 4, 0x000002ea, 0x000f, 0,
|
||||
0, 0 },
|
||||
{ /* 0073 */ "prid", 292, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
32, 4, 4, 0x000002eb, 0x0003, 0,
|
||||
0, 0 },
|
||||
{ /* 0074 */ "icount", 296, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
32, 4, 4, 0x000002ec, 0x000f, 0,
|
||||
0, 0 },
|
||||
{ /* 0075 */ "ccompare0", 300, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
32, 4, 4, 0x000002f0, 0x000f, 0,
|
||||
0, 0 },
|
||||
{ /* 0076 */ "ccompare1", 304, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
32, 4, 4, 0x000002f1, 0x000f, 0,
|
||||
0, 0 },
|
||||
{ /* 0077 */ "ccompare2", 308, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
32, 4, 4, 0x000002f2, 0x000f, 0,
|
||||
0, 0 },
|
||||
{ /* 0078 */ "epc1", 312, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
32, 4, 4, 0x000002b1, 0x0007, 0,
|
||||
0, 0 },
|
||||
{ /* 0079 */ "epc2", 316, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
32, 4, 4, 0x000002b2, 0x0007, 0,
|
||||
0, 0 },
|
||||
{ /* 0080 */ "epc3", 320, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
32, 4, 4, 0x000002b3, 0x0007, 0,
|
||||
0, 0 },
|
||||
{ /* 0081 */ "epc4", 324, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
32, 4, 4, 0x000002b4, 0x0007, 0,
|
||||
0, 0 },
|
||||
{ /* 0082 */ "excsave1", 328, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
32, 4, 4, 0x000002d1, 0x0007, 0,
|
||||
0, 0 },
|
||||
{ /* 0083 */ "excsave2", 332, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
32, 4, 4, 0x000002d2, 0x0007, 0,
|
||||
0, 0 },
|
||||
{ /* 0084 */ "excsave3", 336, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
32, 4, 4, 0x000002d3, 0x0007, 0,
|
||||
0, 0 },
|
||||
{ /* 0085 */ "excsave4", 340, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
32, 4, 4, 0x000002d4, 0x0007, 0,
|
||||
0, 0 },
|
||||
{ /* 0086 */ "eps2", 344, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
19, 4, 4, 0x000002c2, 0x0007, 0,
|
||||
0, 0 },
|
||||
{ /* 0087 */ "eps3", 348, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
19, 4, 4, 0x000002c3, 0x0007, 0,
|
||||
0, 0 },
|
||||
{ /* 0088 */ "eps4", 352, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
19, 4, 4, 0x000002c4, 0x0007, 0,
|
||||
0, 0 },
|
||||
{ /* 0089 */ "exccause", 356, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
6, 4, 4, 0x000002e8, 0x0007, 0,
|
||||
0, 0 },
|
||||
{ /* 0090 */ "depc", 360, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
32, 4, 4, 0x000002c0, 0x0007, 0,
|
||||
0, 0 },
|
||||
{ /* 0091 */ "excvaddr", 364, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
32, 4, 4, 0x000002ee, 0x0007, 0,
|
||||
0, 0 },
|
||||
{ /* 0092 */ "windowbase", 368, xtRegisterTypeSpecialReg, 0x1002, 0,
|
||||
4, 4, 4, 0x00000248, 0x0007, 0,
|
||||
0, 0 },
|
||||
{ /* 0093 */ "windowstart", 372, xtRegisterTypeSpecialReg, 0x1002, 0,
|
||||
16, 4, 4, 0x00000249, 0x0007, 0,
|
||||
0, 0 },
|
||||
{ /* 0094 */ "sar", 376, xtRegisterTypeSpecialReg, 0x1100, 0,
|
||||
6, 4, 4, 0x00000203, 0x0006, 0,
|
||||
0, 0 },
|
||||
{ /* 0095 */ "litbase", 380, xtRegisterTypeSpecialReg, 0x1100, 0,
|
||||
32, 4, 4, 0x00000205, 0x0006, 0,
|
||||
0, 0 },
|
||||
{ /* 0096 */ "ps", 384, xtRegisterTypeSpecialReg, 0x1100, 0,
|
||||
19, 4, 4, 0x000002e6, 0x0007, 0,
|
||||
0, 0 },
|
||||
{ /* 0097 */ "misc0", 388, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
32, 4, 4, 0x000002f4, 0x0007, 0,
|
||||
0, 0 },
|
||||
{ /* 0098 */ "misc1", 392, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
32, 4, 4, 0x000002f5, 0x0007, 0,
|
||||
0, 0 },
|
||||
{ /* 0099 */ "intenable", 396, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
17, 4, 4, 0x000002e4, 0x0007, 0,
|
||||
0, 0 },
|
||||
{ /* 0100 */ "dbreaka0", 400, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
32, 4, 4, 0x00000290, 0x0007, 0,
|
||||
0, 0 },
|
||||
{ /* 0101 */ "dbreakc0", 404, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
32, 4, 4, 0x000002a0, 0x0007, 0,
|
||||
0, 0 },
|
||||
{ /* 0102 */ "dbreaka1", 408, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
32, 4, 4, 0x00000291, 0x0007, 0,
|
||||
0, 0 },
|
||||
{ /* 0103 */ "dbreakc1", 412, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
32, 4, 4, 0x000002a1, 0x0007, 0,
|
||||
0, 0 },
|
||||
{ /* 0104 */ "ibreaka0", 416, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
32, 4, 4, 0x00000280, 0x0007, 0,
|
||||
0, 0 },
|
||||
{ /* 0105 */ "ibreaka1", 420, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
32, 4, 4, 0x00000281, 0x0007, 0,
|
||||
0, 0 },
|
||||
{ /* 0106 */ "ibreakenable", 424, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
2, 4, 4, 0x00000260, 0x0007, 0,
|
||||
0, 0 },
|
||||
{ /* 0107 */ "icountlevel", 428, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
4, 4, 4, 0x000002ed, 0x0007, 0,
|
||||
0, 0 },
|
||||
{ /* 0108 */ "debugcause", 432, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
12, 4, 4, 0x000002e9, 0x0003, 0,
|
||||
0, 0 },
|
||||
{ /* 0109 */ "rasid", 436, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
32, 4, 4, 0x0000025a, 0x0007, 0,
|
||||
0, 0 },
|
||||
{ /* 0110 */ "itlbcfg", 440, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
18, 4, 4, 0x0000025b, 0x0007, 0,
|
||||
0, 0 },
|
||||
{ /* 0111 */ "dtlbcfg", 444, xtRegisterTypeSpecialReg, 0x1000, 0,
|
||||
18, 4, 4, 0x0000025c, 0x0007, 0,
|
||||
0, 0 },
|
||||
{ /* 0112 */ "threadptr", 448, xtRegisterTypeUserReg, 0x110, 0,
|
||||
32, 4, 4, 0x000003e7, 0x0006, 0,
|
||||
0, 0 },
|
||||
{ /* 0113 */ "pc", 452, xtRegisterTypeVirtual, 0x100, 0,
|
||||
32, 4, 4, 0x00000020, 0x0006, 0,
|
||||
0, 0 },
|
||||
{ /* 0114 */ "a0", 456, xtRegisterTypeWindow, 0x100, 0,
|
||||
32, 4, 4, 0x00000000, 0x0006, 0,
|
||||
0, 0 },
|
||||
{ /* 0115 */ "a1", 460, xtRegisterTypeWindow, 0x100, 0,
|
||||
32, 4, 4, 0x00000001, 0x0006, 0,
|
||||
0, 0 },
|
||||
{ /* 0116 */ "a2", 464, xtRegisterTypeWindow, 0x100, 0,
|
||||
32, 4, 4, 0x00000002, 0x0006, 0,
|
||||
0, 0 },
|
||||
{ /* 0117 */ "a3", 468, xtRegisterTypeWindow, 0x100, 0,
|
||||
32, 4, 4, 0x00000003, 0x0006, 0,
|
||||
0, 0 },
|
||||
{ /* 0118 */ "a4", 472, xtRegisterTypeWindow, 0x100, 0,
|
||||
32, 4, 4, 0x00000004, 0x0006, 0,
|
||||
0, 0 },
|
||||
{ /* 0119 */ "a5", 476, xtRegisterTypeWindow, 0x100, 0,
|
||||
32, 4, 4, 0x00000005, 0x0006, 0,
|
||||
0, 0 },
|
||||
{ /* 0120 */ "a6", 480, xtRegisterTypeWindow, 0x100, 0,
|
||||
32, 4, 4, 0x00000006, 0x0006, 0,
|
||||
0, 0 },
|
||||
{ /* 0121 */ "a7", 484, xtRegisterTypeWindow, 0x100, 0,
|
||||
32, 4, 4, 0x00000007, 0x0006, 0,
|
||||
0, 0 },
|
||||
{ /* 0122 */ "a8", 488, xtRegisterTypeWindow, 0x100, 0,
|
||||
32, 4, 4, 0x00000008, 0x0006, 0,
|
||||
0, 0 },
|
||||
{ /* 0123 */ "a9", 492, xtRegisterTypeWindow, 0x100, 0,
|
||||
32, 4, 4, 0x00000009, 0x0006, 0,
|
||||
0, 0 },
|
||||
{ /* 0124 */ "a10", 496, xtRegisterTypeWindow, 0x100, 0,
|
||||
32, 4, 4, 0x0000000a, 0x0006, 0,
|
||||
0, 0 },
|
||||
{ /* 0125 */ "a11", 500, xtRegisterTypeWindow, 0x100, 0,
|
||||
32, 4, 4, 0x0000000b, 0x0006, 0,
|
||||
0, 0 },
|
||||
{ /* 0126 */ "a12", 504, xtRegisterTypeWindow, 0x100, 0,
|
||||
32, 4, 4, 0x0000000c, 0x0006, 0,
|
||||
0, 0 },
|
||||
{ /* 0127 */ "a13", 508, xtRegisterTypeWindow, 0x100, 0,
|
||||
32, 4, 4, 0x0000000d, 0x0006, 0,
|
||||
0, 0 },
|
||||
{ /* 0128 */ "a14", 512, xtRegisterTypeWindow, 0x100, 0,
|
||||
32, 4, 4, 0x0000000e, 0x0006, 0,
|
||||
0, 0 },
|
||||
{ /* 0129 */ "a15", 516, xtRegisterTypeWindow, 0x100, 0,
|
||||
32, 4, 4, 0x0000000f, 0x0006, 0,
|
||||
0, 0 },
|
||||
{ /* 0130 */ "psintlevel", 520, xtRegisterTypeMapped, 0x1010, 0,
|
||||
4, 4, 4, 0x00002004, 0x0006, (xtensa_mask_t *) mask0,
|
||||
0, 0 },
|
||||
{ /* 0131 */ "psum", 524, xtRegisterTypeMapped, 0x1010, 0,
|
||||
1, 4, 4, 0x00002005, 0x0006, (xtensa_mask_t *) mask1,
|
||||
0, 0 },
|
||||
{ /* 0132 */ "pswoe", 528, xtRegisterTypeMapped, 0x1010, 0,
|
||||
1, 4, 4, 0x00002006, 0x0006, (xtensa_mask_t *) mask2,
|
||||
0, 0 },
|
||||
{ /* 0133 */ "psring", 532, xtRegisterTypeMapped, 0x1010, 0,
|
||||
2, 4, 4, 0x00002007, 0x0006, (xtensa_mask_t *) mask3,
|
||||
0, 0 },
|
||||
{ /* 0134 */ "psexcm", 536, xtRegisterTypeMapped, 0x1010, 0,
|
||||
1, 4, 4, 0x00002008, 0x0006, (xtensa_mask_t *) mask4,
|
||||
0, 0 },
|
||||
{ /* 0135 */ "pscallinc", 540, xtRegisterTypeMapped, 0x1010, 0,
|
||||
2, 4, 4, 0x00002009, 0x0006, (xtensa_mask_t *) mask5,
|
||||
0, 0 },
|
||||
{ /* 0136 */ "psowb", 544, xtRegisterTypeMapped, 0x1010, 0,
|
||||
4, 4, 4, 0x0000200a, 0x0006, (xtensa_mask_t *) mask6,
|
||||
0, 0 },
|
||||
{ /* 0137 */ "litbaddr", 548, xtRegisterTypeMapped, 0x1010, 0,
|
||||
20, 4, 4, 0x0000200b, 0x0006, (xtensa_mask_t *) mask7,
|
||||
0, 0 },
|
||||
{ /* 0138 */ "litben", 552, xtRegisterTypeMapped, 0x1010, 0,
|
||||
1, 4, 4, 0x0000200c, 0x0006, (xtensa_mask_t *) mask8,
|
||||
0, 0 },
|
||||
{ /* 0139 */ "dbnum", 556, xtRegisterTypeMapped, 0x1010, 0,
|
||||
4, 4, 4, 0x00002011, 0x0006, (xtensa_mask_t *) mask9,
|
||||
0, 0 },
|
||||
{ /* 0140 */ "asid3", 560, xtRegisterTypeMapped, 0x1010, 0,
|
||||
8, 4, 4, 0x00002012, 0x0006, (xtensa_mask_t *) mask10,
|
||||
0, 0 },
|
||||
{ /* 0141 */ "asid2", 564, xtRegisterTypeMapped, 0x1010, 0,
|
||||
8, 4, 4, 0x00002013, 0x0006, (xtensa_mask_t *) mask11,
|
||||
0, 0 },
|
||||
{ /* 0142 */ "asid1", 568, xtRegisterTypeMapped, 0x1010, 0,
|
||||
8, 4, 4, 0x00002014, 0x0006, (xtensa_mask_t *) mask12,
|
||||
0, 0 },
|
||||
{ /* 0143 */ "instpgszid4", 572, xtRegisterTypeMapped, 0x1010, 0,
|
||||
2, 4, 4, 0x00002015, 0x0006, (xtensa_mask_t *) mask13,
|
||||
0, 0 },
|
||||
{ /* 0144 */ "datapgszid4", 576, xtRegisterTypeMapped, 0x1010, 0,
|
||||
2, 4, 4, 0x00002016, 0x0006, (xtensa_mask_t *) mask14,
|
||||
0, 0 },
|
||||
{ /* 0145 */ "ptbase", 580, xtRegisterTypeMapped, 0x1010, 0,
|
||||
10, 4, 4, 0x00002017, 0x0006, (xtensa_mask_t *) mask15,
|
||||
0, 0 },
|
||||
};
|
||||
|
||||
|
||||
struct gdbarch_tdep xtensa_tdep =
|
||||
{
|
||||
/* target_flags */ 0,
|
||||
/* spill_location */ -1,
|
||||
/* spill_size */ 0,
|
||||
/* unused */ 0,
|
||||
/* call_abi */ 0,
|
||||
/* debug_interrupt_level */ XCHAL_DEBUGLEVEL,
|
||||
/* icache_line_bytes */ XCHAL_ICACHE_LINESIZE,
|
||||
/* dcache_line_bytes */ XCHAL_DCACHE_LINESIZE,
|
||||
/* dcache_writeback */ XCHAL_DCACHE_IS_WRITEBACK,
|
||||
/* isa_use_windowed_registers */ XCHAL_HAVE_WINDOWED,
|
||||
/* isa_use_density_instructions */ XCHAL_HAVE_DENSITY,
|
||||
/* isa_use_exceptions */ 1,
|
||||
/* isa_use_ext_l32r */ 0 /* XCHAL_USE_ABSOLUTE_LITERALS */,
|
||||
/* isa_max_insn_size */ 3,
|
||||
/* debug_num_ibreaks */ XCHAL_NUM_IBREAK,
|
||||
/* debug_num_dbreaks */ XCHAL_NUM_DBREAK,
|
||||
/* rmap */ rmap,
|
||||
/* num_regs */ 114,
|
||||
/* num_pseudo_regs */ 32,
|
||||
/* num_aregs */ 64,
|
||||
/* num_contexts */ 0,
|
||||
/* ar_base */ 0,
|
||||
/* a0_base */ 114,
|
||||
/* wb_regnum */ 92,
|
||||
/* ws_regnum */ 93,
|
||||
/* pc_regnum */ 113,
|
||||
/* ps_regnum */ 96,
|
||||
/* lbeg_regnum */ 64,
|
||||
/* lend_regnum */ 65,
|
||||
/* lcount_regnum */ 66,
|
||||
/* sar_regnum */ 94,
|
||||
/* litbase_regnum */ 0,
|
||||
/* debugcause_regnum */ 108,
|
||||
/* exccause_regnum */ 89,
|
||||
/* excvaddr_regnum */ 91,
|
||||
/* max_register_raw_size */ 4,
|
||||
/* max_register_virtual_size */ 4,
|
||||
/* fp_layout */ 0,
|
||||
/* fp_layout_bytes */ 0,
|
||||
/* gregmap */ 0
|
||||
};
|
||||
1739
gdb/xtensa-tdep.c
Normal file
1739
gdb/xtensa-tdep.c
Normal file
File diff suppressed because it is too large
Load Diff
298
gdb/xtensa-tdep.h
Normal file
298
gdb/xtensa-tdep.h
Normal file
@ -0,0 +1,298 @@
|
||||
/* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
|
||||
|
||||
Copyright (C) 2003, 2005, 2006 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of GDB.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 51 Franklin Street, Fifth Floor,
|
||||
Boston, MA 02110-1301, USA. */
|
||||
|
||||
|
||||
/* XTENSA_TDEP_VERSION can/should be changed along with XTENSA_CONFIG_VERSION
|
||||
whenever the "tdep" structure changes in an incompatible way. */
|
||||
|
||||
#define XTENSA_TDEP_VERSION 0x60
|
||||
|
||||
/* Xtensa register type. */
|
||||
|
||||
typedef enum
|
||||
{
|
||||
xtRegisterTypeArRegfile = 1, /* Register File ar0..arXX. */
|
||||
xtRegisterTypeSpecialReg, /* CPU states, such as PS, Booleans, (rsr). */
|
||||
xtRegisterTypeUserReg, /* User defined registers (rur). */
|
||||
xtRegisterTypeTieRegfile, /* User define register files. */
|
||||
xtRegisterTypeTieState, /* TIE States (mapped on user regs). */
|
||||
xtRegisterTypeMapped, /* Mapped on Special Registers. */
|
||||
xtRegisterTypeUnmapped, /* Special case of masked registers. */
|
||||
xtRegisterTypeWindow, /* Live window registers (a0..a15). */
|
||||
xtRegisterTypeVirtual, /* PC, FP. */
|
||||
xtRegisterTypeUnknown
|
||||
} xtensa_register_type_t;
|
||||
|
||||
|
||||
/* Xtensa register group. */
|
||||
|
||||
typedef enum
|
||||
{
|
||||
xtRegisterGroupUnknown = 0,
|
||||
xtRegisterGroupRegFile = 0x0001, /* Register files without ARx. */
|
||||
xtRegisterGroupAddrReg = 0x0002, /* ARx. */
|
||||
xtRegisterGroupSpecialReg = 0x0004, /* SRxx. */
|
||||
xtRegisterGroupUserReg = 0x0008, /* URxx. */
|
||||
xtRegisterGroupState = 0x0010, /* States. */
|
||||
|
||||
xtRegisterGroupGeneral = 0x0100, /* General registers, Ax, SR. */
|
||||
xtRegisterGroupUser = 0x0200, /* User registers. */
|
||||
xtRegisterGroupFloat = 0x0400, /* Floating Point. */
|
||||
xtRegisterGroupVectra = 0x0800, /* Vectra. */
|
||||
xtRegisterGroupSystem = 0x1000, /* System. */
|
||||
} xtensa_register_group_t;
|
||||
|
||||
|
||||
/* Xtensa target flags. */
|
||||
|
||||
typedef enum
|
||||
{
|
||||
xtTargetFlagsNonVisibleRegs = 0x0001,
|
||||
xtTargetFlagsUseFetchStore = 0x0002,
|
||||
} xtensa_target_flags_t;
|
||||
|
||||
|
||||
/* Xtensa ELF core file register set representation ('.reg' section).
|
||||
Copied from target-side ELF header <xtensa/elf.h>. */
|
||||
|
||||
typedef unsigned long xtensa_elf_greg_t;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
xtensa_elf_greg_t xchal_config_id0;
|
||||
xtensa_elf_greg_t xchal_config_id1;
|
||||
xtensa_elf_greg_t cpux;
|
||||
xtensa_elf_greg_t cpuy;
|
||||
xtensa_elf_greg_t pc;
|
||||
xtensa_elf_greg_t ps;
|
||||
xtensa_elf_greg_t exccause;
|
||||
xtensa_elf_greg_t excvaddr;
|
||||
xtensa_elf_greg_t windowbase;
|
||||
xtensa_elf_greg_t windowstart;
|
||||
xtensa_elf_greg_t lbeg;
|
||||
xtensa_elf_greg_t lend;
|
||||
xtensa_elf_greg_t lcount;
|
||||
xtensa_elf_greg_t sar;
|
||||
xtensa_elf_greg_t syscall;
|
||||
xtensa_elf_greg_t ar[0]; /* variable size (per config). */
|
||||
} xtensa_elf_gregset_t;
|
||||
|
||||
#define SIZEOF_GREGSET (sizeof (xtensa_elf_gregset_t) + NUM_AREGS * 4)
|
||||
#define XTENSA_ELF_NGREG (SIZEOF_GREGSET / sizeof(xtensa_elf_greg_t))
|
||||
|
||||
|
||||
/* Mask. */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
int count;
|
||||
struct
|
||||
{
|
||||
int reg_num;
|
||||
int bit_start;
|
||||
int bit_size;
|
||||
} mask[0];
|
||||
} xtensa_mask_t;
|
||||
|
||||
|
||||
/* Xtensa register representation. */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
char* name; /* Register name. */
|
||||
int offset; /* Offset. */
|
||||
xtensa_register_type_t type; /* Register type. */
|
||||
xtensa_register_group_t group;/* Register group. */
|
||||
struct type* ctype; /* C-type. */
|
||||
int bit_size; /* The actual bit size in the target. */
|
||||
int byte_size; /* Actual space allocated in registers[]. */
|
||||
int align; /* Alignment for this register. */
|
||||
|
||||
unsigned int target_number; /* Register target number. */
|
||||
|
||||
int flags; /* Flags. */
|
||||
|
||||
const xtensa_mask_t *mask; /* Register is a compilation of other regs. */
|
||||
const char *fetch; /* Instruction sequence to fetch register. */
|
||||
const char *store; /* Instruction sequence to store register. */
|
||||
} xtensa_register_t;
|
||||
|
||||
|
||||
#define XTENSA_REGISTER_FLAGS_PRIVILEDGED 0x0001
|
||||
#define XTENSA_REGISTER_FLAGS_READABLE 0x0002
|
||||
#define XTENSA_REGISTER_FLAGS_WRITABLE 0x0004
|
||||
#define XTENSA_REGISTER_FLAGS_VOLATILE 0x0008
|
||||
|
||||
|
||||
/* Call-ABI for stack frame. */
|
||||
|
||||
typedef enum
|
||||
{
|
||||
CallAbiDefault = 0, /* Any 'callX' instructions; default stack. */
|
||||
CallAbiCall0Only, /* Only 'call0' instructions; flat stack. */
|
||||
} call_abi_t;
|
||||
|
||||
|
||||
/* Xtensa-specific target dependencies. */
|
||||
|
||||
struct gdbarch_tdep
|
||||
{
|
||||
unsigned int target_flags;
|
||||
|
||||
/* Spill location for TIE register files under ocd. */
|
||||
|
||||
unsigned int spill_location;
|
||||
unsigned int spill_size;
|
||||
|
||||
char *unused; /* Placeholder for compatibility. */
|
||||
call_abi_t call_abi; /* Calling convention. */
|
||||
|
||||
/* CPU configuration. */
|
||||
|
||||
unsigned int debug_interrupt_level;
|
||||
|
||||
unsigned int icache_line_bytes;
|
||||
unsigned int dcache_line_bytes;
|
||||
unsigned int dcache_writeback;
|
||||
|
||||
unsigned int isa_use_windowed_registers;
|
||||
unsigned int isa_use_density_instructions;
|
||||
unsigned int isa_use_exceptions;
|
||||
unsigned int isa_use_ext_l32r;
|
||||
unsigned int isa_max_insn_size; /* Maximum instruction length. */
|
||||
unsigned int debug_num_ibreaks; /* Number of IBREAKs. */
|
||||
unsigned int debug_num_dbreaks;
|
||||
|
||||
/* Register map. */
|
||||
|
||||
xtensa_register_t* regmap;
|
||||
|
||||
unsigned int num_regs; /* Number of registers in regmap. */
|
||||
unsigned int num_pseudo_regs; /* Number of pseudo registers. */
|
||||
unsigned int num_aregs; /* Size of register file. */
|
||||
unsigned int num_contexts;
|
||||
|
||||
int ar_base; /* Register number for AR0. */
|
||||
int a0_base; /* Register number for A0 (pseudo). */
|
||||
int wb_regnum; /* Register number for WB. */
|
||||
int ws_regnum; /* Register number for WS. */
|
||||
int pc_regnum; /* Register number for PC. */
|
||||
int ps_regnum; /* Register number for PS. */
|
||||
int lbeg_regnum; /* Register numbers for count regs. */
|
||||
int lend_regnum;
|
||||
int lcount_regnum;
|
||||
int sar_regnum; /* Register number of SAR. */
|
||||
int litbase_regnum; /* Register number of LITBASE. */
|
||||
|
||||
int interrupt_regnum; /* Register number for interrupt. */
|
||||
int interrupt2_regnum; /* Register number for interrupt2. */
|
||||
int cpenable_regnum; /* Register number for cpenable. */
|
||||
int debugcause_regnum; /* Register number for debugcause. */
|
||||
int exccause_regnum; /* Register number for exccause. */
|
||||
int excvaddr_regnum; /* Register number for excvaddr. */
|
||||
|
||||
int max_register_raw_size;
|
||||
int max_register_virtual_size;
|
||||
unsigned long *fp_layout; /* Layout of custom/TIE regs in 'FP' area. */
|
||||
unsigned int fp_layout_bytes; /* Size of layout information (in bytes). */
|
||||
unsigned long *gregmap;
|
||||
};
|
||||
|
||||
|
||||
/* Define macros to access some of the gdbarch entries. */
|
||||
#define XTENSA_TARGET_FLAGS \
|
||||
(gdbarch_tdep (current_gdbarch)->target_flags)
|
||||
#define SPILL_LOCATION \
|
||||
(gdbarch_tdep (current_gdbarch)->spill_location)
|
||||
#define SPILL_SIZE \
|
||||
(gdbarch_tdep (current_gdbarch)->spill_size)
|
||||
#define CALL_ABI \
|
||||
(gdbarch_tdep (current_gdbarch)->call_abi)
|
||||
#define ISA_USE_WINDOWED_REGISTERS \
|
||||
(gdbarch_tdep (current_gdbarch)->isa_use_windowed_registers)
|
||||
#define ISA_USE_DENSITY_INSTRUCTIONS \
|
||||
(gdbarch_tdep (current_gdbarch)->isa_use_density_instructions)
|
||||
#define ISA_USE_EXCEPTIONS \
|
||||
(gdbarch_tdep (current_gdbarch)->isa_use_exceptions)
|
||||
#define ISA_USE_EXT_L32R \
|
||||
(gdbarch_tdep (current_gdbarch)->isa_use_ext_l32r)
|
||||
#define DEBUG_DATA_VADDR_TRAP_COUNT \
|
||||
(gdbarch_tdep (current_gdbarch)->debug_data_vaddr_trap_count)
|
||||
#define DEBUG_INST_VADDR_TRAP_COUNT \
|
||||
(gdbarch_tdep (current_gdbarch)->debug_inst_vaddr_trap_count)
|
||||
#define ISA_MAX_INSN_SIZE \
|
||||
(gdbarch_tdep (current_gdbarch)->isa_max_insn_size)
|
||||
#define DEBUG_NUM_IBREAKS \
|
||||
(gdbarch_tdep (current_gdbarch)->debug_num_ibreaks)
|
||||
#define DEBUG_NUM_DBREAKS \
|
||||
(gdbarch_tdep (current_gdbarch)->debug_num_dbreaks)
|
||||
|
||||
#define NUM_AREGS (gdbarch_tdep (current_gdbarch)->num_aregs)
|
||||
#define WB_REGNUM (gdbarch_tdep (current_gdbarch)->wb_regnum)
|
||||
#define WS_REGNUM (gdbarch_tdep (current_gdbarch)->ws_regnum)
|
||||
#define LBEG_REGNUM (gdbarch_tdep (current_gdbarch)->lbeg_regnum)
|
||||
#define LEND_REGNUM (gdbarch_tdep (current_gdbarch)->lend_regnum)
|
||||
#define LCOUNT_REGNUM (gdbarch_tdep (current_gdbarch)->lcount_regnum)
|
||||
#define SAR_REGNUM (gdbarch_tdep (current_gdbarch)->sar_regnum)
|
||||
#define REGMAP (gdbarch_tdep (current_gdbarch)->regmap)
|
||||
|
||||
#define LITBASE_REGNUM (gdbarch_tdep (current_gdbarch)->litbase_regnum)
|
||||
#define DEBUGCAUSE_REGNUM (gdbarch_tdep (current_gdbarch)->debugcause_regnum)
|
||||
#define EXCCAUSE_REGNUM (gdbarch_tdep (current_gdbarch)->exccause_regnum)
|
||||
#define EXCVADDR_REGNUM (gdbarch_tdep (current_gdbarch)->excvaddr_regnum)
|
||||
#define NUM_IBREAKS (gdbarch_tdep (current_gdbarch)->num_ibreaks)
|
||||
#define REGMAP_BYTES (gdbarch_tdep (current_gdbarch)->regmap_bytes)
|
||||
#define A0_BASE (gdbarch_tdep (current_gdbarch)->a0_base)
|
||||
#define AR_BASE (gdbarch_tdep (current_gdbarch)->ar_base)
|
||||
#define FP_ALIAS (NUM_REGS + NUM_PSEUDO_REGS)
|
||||
#define CALL_ABI (gdbarch_tdep (current_gdbarch)->call_abi)
|
||||
#define NUM_CONTEXTS (gdbarch_tdep (current_gdbarch)->num_contexts)
|
||||
|
||||
#define FP_LAYOUT (gdbarch_tdep (current_gdbarch)->fp_layout)
|
||||
#define FP_LAYOUT_BYTES (gdbarch_tdep (current_gdbarch)->fp_layout_bytes)
|
||||
#define GREGMAP (gdbarch_tdep (current_gdbarch)->gregmap)
|
||||
|
||||
#define AREGS_MASK (NUM_AREGS - 1)
|
||||
#define WB_MASK (AREGS_MASK >> 2)
|
||||
#define WB_SHIFT 2
|
||||
|
||||
/* We assign fixed numbers to the registers of the "current" window
|
||||
(i.e., relative to WB). The registers get remapped via the reg_map
|
||||
data structure to their corresponding register in the AR register
|
||||
file (see xtensa-tdep.c). */
|
||||
|
||||
#define A0_REGNUM (A0_BASE + 0)
|
||||
#define A1_REGNUM (A0_BASE + 1)
|
||||
#define A2_REGNUM (A0_BASE + 2)
|
||||
#define A3_REGNUM (A0_BASE + 3)
|
||||
#define A4_REGNUM (A0_BASE + 4)
|
||||
#define A5_REGNUM (A0_BASE + 5)
|
||||
#define A6_REGNUM (A0_BASE + 6)
|
||||
#define A7_REGNUM (A0_BASE + 7)
|
||||
#define A8_REGNUM (A0_BASE + 8)
|
||||
#define A9_REGNUM (A0_BASE + 9)
|
||||
#define A10_REGNUM (A0_BASE + 10)
|
||||
#define A11_REGNUM (A0_BASE + 11)
|
||||
#define A12_REGNUM (A0_BASE + 12)
|
||||
#define A13_REGNUM (A0_BASE + 13)
|
||||
#define A14_REGNUM (A0_BASE + 14)
|
||||
#define A15_REGNUM (A0_BASE + 15)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user