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x86: correct handling of LAR and LSL

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Both uniformly only ever take 16-bit memory operands while at the same
time requiring matching (in size) register operands, which then also
should disassemble that way. This in particular requires splitting each
of the templates for the assembler and separating decode of the
register and memory forms in the disassembler.
This commit is contained in:
Jan Beulich 2022-11-24 09:34:52 +01:00
parent bde9f9d7e9
commit c9f5b96bda
9 changed files with 116 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
gas/config/tc-i386-intel.c
View File

@ -697,7 +697,9 @@ i386_intel_operand (char *operand_string, int got_a_float)
i.types[this_operand].bitfield.word = 1;
if (got_a_float == 2) /* "fi..." */
suffix = SHORT_MNEM_SUFFIX;
else
else if ((current_templates->start->base_opcode | 1) != 0x03
|| (current_templates->start->opcode_modifier.opcodespace
!= SPACE_0F)) /* lar, lsl */
suffix = WORD_MNEM_SUFFIX;
break;

46
gas/testsuite/gas/i386/intel-intel.d
View File

@ -232,8 +232,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: e5 90 + in eax,0x90
[ ]*[a-f0-9]+: e6 90 + out 0x90,al
[ ]*[a-f0-9]+: e7 90 + out 0x90,eax
[ ]*[a-f0-9]+: e8 90 90 90 90 + call 90909373 <barn\+0x90908831>
[ ]*[a-f0-9]+: e9 90 90 90 90 + jmp 90909378 <barn\+0x90908836>
[ ]*[a-f0-9]+: e8 90 90 90 90 + call 90909... <barn\+0x90908...>
[ ]*[a-f0-9]+: e9 90 90 90 90 + jmp 90909... <barn\+0x90908...>
[ ]*[a-f0-9]+: ea 90 90 90 90 90 90 jmp 0x9090:0x90909090
[ ]*[a-f0-9]+: eb 90 + jmp 281 <foo\+0x281>
[ ]*[a-f0-9]+: ec + in al,dx
@ -308,22 +308,22 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 77 + emms
[ ]*[a-f0-9]+: 0f 7e 90 90 90 90 90 movd DWORD PTR \[eax-0x6f6f6f70\],mm2
[ ]*[a-f0-9]+: 0f 7f 90 90 90 90 90 movq QWORD PTR \[eax-0x6f6f6f70\],mm2
[ ]*[a-f0-9]+: 0f 80 90 90 90 90 + jo 909094e6 <barn\+0x909089a4>
[ ]*[a-f0-9]+: 0f 81 90 90 90 90 + jno 909094ec <barn\+0x909089aa>
[ ]*[a-f0-9]+: 0f 82 90 90 90 90 + jb 909094f2 <barn\+0x909089b0>
[ ]*[a-f0-9]+: 0f 83 90 90 90 90 + jae 909094f8 <barn\+0x909089b6>
[ ]*[a-f0-9]+: 0f 84 90 90 90 90 + je 909094fe <barn\+0x909089bc>
[ ]*[a-f0-9]+: 0f 85 90 90 90 90 + jne 90909504 <barn\+0x909089c2>
[ ]*[a-f0-9]+: 0f 86 90 90 90 90 + jbe 9090950a <barn\+0x909089c8>
[ ]*[a-f0-9]+: 0f 87 90 90 90 90 + ja 90909510 <barn\+0x909089ce>
[ ]*[a-f0-9]+: 0f 88 90 90 90 90 + js 90909516 <barn\+0x909089d4>
[ ]*[a-f0-9]+: 0f 89 90 90 90 90 + jns 9090951c <barn\+0x909089da>
[ ]*[a-f0-9]+: 0f 8a 90 90 90 90 + jp 90909522 <barn\+0x909089e0>
[ ]*[a-f0-9]+: 0f 8b 90 90 90 90 + jnp 90909528 <barn\+0x909089e6>
[ ]*[a-f0-9]+: 0f 8c 90 90 90 90 + jl 9090952e <barn\+0x909089ec>
[ ]*[a-f0-9]+: 0f 8d 90 90 90 90 + jge 90909534 <barn\+0x909089f2>
[ ]*[a-f0-9]+: 0f 8e 90 90 90 90 + jle 9090953a <barn\+0x909089f8>
[ ]*[a-f0-9]+: 0f 8f 90 90 90 90 + jg 90909540 <barn\+0x909089fe>
[ ]*[a-f0-9]+: 0f 80 90 90 90 90 + jo 90909... <barn\+0x90908...>
[ ]*[a-f0-9]+: 0f 81 90 90 90 90 + jno 90909... <barn\+0x90908...>
[ ]*[a-f0-9]+: 0f 82 90 90 90 90 + jb 90909... <barn\+0x90908...>
[ ]*[a-f0-9]+: 0f 83 90 90 90 90 + jae 90909... <barn\+0x90908...>
[ ]*[a-f0-9]+: 0f 84 90 90 90 90 + je 90909... <barn\+0x90908...>
[ ]*[a-f0-9]+: 0f 85 90 90 90 90 + jne 90909... <barn\+0x90908...>
[ ]*[a-f0-9]+: 0f 86 90 90 90 90 + jbe 90909... <barn\+0x90908...>
[ ]*[a-f0-9]+: 0f 87 90 90 90 90 + ja 90909... <barn\+0x90908...>
[ ]*[a-f0-9]+: 0f 88 90 90 90 90 + js 90909... <barn\+0x90908...>
[ ]*[a-f0-9]+: 0f 89 90 90 90 90 + jns 90909... <barn\+0x90908...>
[ ]*[a-f0-9]+: 0f 8a 90 90 90 90 + jp 90909... <barn\+0x90908...>
[ ]*[a-f0-9]+: 0f 8b 90 90 90 90 + jnp 90909... <barn\+0x90908...>
[ ]*[a-f0-9]+: 0f 8c 90 90 90 90 + jl 90909... <barn\+0x90908...>
[ ]*[a-f0-9]+: 0f 8d 90 90 90 90 + jge 90909... <barn\+0x90908...>
[ ]*[a-f0-9]+: 0f 8e 90 90 90 90 + jle 90909... <barn\+0x90908...>
[ ]*[a-f0-9]+: 0f 8f 90 90 90 90 + jg 90909... <barn\+0x90908...>
[ ]*[a-f0-9]+: 0f 90 80 90 90 90 90 seto BYTE PTR \[eax-0x6f6f6f70\]
[ ]*[a-f0-9]+: 0f 91 80 90 90 90 90 setno BYTE PTR \[eax-0x6f6f6f70\]
[ ]*[a-f0-9]+: 0f 92 80 90 90 90 90 setb BYTE PTR \[eax-0x6f6f6f70\]
@ -532,7 +532,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 d3 90 90 90 90 90 rcl WORD PTR \[eax-0x6f6f6f70\],cl
[ ]*[a-f0-9]+: 66 e5 90 + in ax,0x90
[ ]*[a-f0-9]+: 66 e7 90 + out 0x90,ax
[ ]*[a-f0-9]+: 66 e8 8f 90 + callw 9922 <barn\+0x8de0>
[ ]*[a-f0-9]+: 66 e8 8f 90 + callw 9... <barn\+0x8...>
[ ]*[a-f0-9]+: 66 ea 90 90 90 90 + jmp 0x9090:0x9090
[ ]*[a-f0-9]+: 66 ed + in ax,dx
[ ]*[a-f0-9]+: 66 ef + out dx,ax
@ -699,6 +699,14 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 4b 90 90 90 90 90 cmovnp edx,DWORD PTR \[eax-0x6f6f6f70\]
[ ]*[a-f0-9]+: 66 0f 4a 90 90 90 90 90 cmovp dx,WORD PTR \[eax-0x6f6f6f70\]
[ ]*[a-f0-9]+: 66 0f 4b 90 90 90 90 90 cmovnp dx,WORD PTR \[eax-0x6f6f6f70\]
[ ]*[a-f0-9]+: 0f 02 c0 + lar eax,eax
[ ]*[a-f0-9]+: 66 0f 02 c0 + lar ax,ax
[ ]*[a-f0-9]+: 0f 02 00 + lar eax,WORD PTR \[eax\]
[ ]*[a-f0-9]+: 66 0f 02 00 + lar ax,WORD PTR \[eax\]
[ ]*[a-f0-9]+: 0f 03 c0 + lsl eax,eax
[ ]*[a-f0-9]+: 66 0f 03 c0 + lsl ax,ax
[ ]*[a-f0-9]+: 0f 03 00 + lsl eax,WORD PTR \[eax\]
[ ]*[a-f0-9]+: 66 0f 03 00 + lsl ax,WORD PTR \[eax\]
[ ]*[a-f0-9]+: 8b 04 04 + mov eax,DWORD PTR \[esp\+eax\*1\]
[ ]*[a-f0-9]+: 8b 04 20 + mov eax,DWORD PTR \[eax\+eiz\*1\]
[ ]*[a-f0-9]+: c4 e2 69 92 04 08 + vgatherdps xmm0,DWORD PTR \[eax\+xmm1\*1\],xmm2

8
gas/testsuite/gas/i386/intel.d
View File

@ -698,6 +698,14 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 4b 90 90 90 90 90 cmovnp -0x6f6f6f70\(%eax\),%edx
[ ]*[a-f0-9]+: 66 0f 4a 90 90 90 90 90 cmovp -0x6f6f6f70\(%eax\),%dx
[ ]*[a-f0-9]+: 66 0f 4b 90 90 90 90 90 cmovnp -0x6f6f6f70\(%eax\),%dx
[ ]*[a-f0-9]+: 0f 02 c0 lar %eax,%eax
[ ]*[a-f0-9]+: 66 0f 02 c0 lar %ax,%ax
[ ]*[a-f0-9]+: 0f 02 00 lar \(%eax\),%eax
[ ]*[a-f0-9]+: 66 0f 02 00 lar \(%eax\),%ax
[ ]*[a-f0-9]+: 0f 03 c0 lsl %eax,%eax
[ ]*[a-f0-9]+: 66 0f 03 c0 lsl %ax,%ax
[ ]*[a-f0-9]+: 0f 03 00 lsl \(%eax\),%eax
[ ]*[a-f0-9]+: 66 0f 03 00 lsl \(%eax\),%ax
[ ]*[a-f0-9]+: 8b 04 04 mov \(%esp,%eax(,1)?\),%eax
[ ]*[a-f0-9]+: 8b 04 20 mov \(%eax(,%eiz)?(,1)?\),%eax
[ ]*[a-f0-9]+: c4 e2 69 92 04 08 vgatherdps %xmm2,\(%eax,%xmm1(,1)?\),%xmm0

10
gas/testsuite/gas/i386/intel.s
View File

@ -699,6 +699,16 @@ fidivr dword ptr [ebx]
cmovpe dx, 0x90909090[eax]
cmovpo dx, 0x90909090[eax]
lar eax, eax
lar ax, ax
lar eax, word ptr [eax]
lar ax, word ptr [eax]
lsl eax, eax
lsl ax, ax
lsl eax, word ptr [eax]
lsl ax, word ptr [eax]
# Check base/index swapping
.allow_index_reg
mov eax, [eax+esp]

8
gas/testsuite/gas/i386/intelbad.l
View File

@ -161,3 +161,11 @@
.*:181: Error: .*
.*:183: Error: .*
.*:184: Error: .*
.*:186: Error: .*
.*:187: Error: .*
.*:188: Error: .*
.*:189: Error: .*
.*:191: Error: .*
.*:192: Error: .*
.*:193: Error: .*
.*:194: Error: .*

10
gas/testsuite/gas/i386/intelbad.s
View File

@ -182,3 +182,13 @@ start:
fild far ptr [ebx]
fist near ptr [ebx]
lar eax, ax
lar ax, eax
lar eax, dword ptr [eax]
lar ax, dword ptr [eax]
lsl eax, ax
lsl ax, eax
lsl eax, dword ptr [eax]
lsl ax, dword ptr [eax]

16
opcodes/i386-dis.c
View File

@ -833,6 +833,8 @@ enum
MOD_0F01_REG_3,
MOD_0F01_REG_5,
MOD_0F01_REG_7,
MOD_0F02,
MOD_0F03,
MOD_0F12_PREFIX_0,
MOD_0F12_PREFIX_2,
MOD_0F13,
@ -2115,8 +2117,8 @@ static const struct dis386 dis386_twobyte[] = {
/* 00 */
{ REG_TABLE (REG_0F00 ) },
{ REG_TABLE (REG_0F01 ) },
{ "larS", { Gv, Ew }, 0 },
{ "lslS", { Gv, Ew }, 0 },
{ MOD_TABLE (MOD_0F02) },
{ MOD_TABLE (MOD_0F03) },
{ Bad_Opcode },
{ "syscall", { XX }, 0 },
{ "clts", { XX }, 0 },
@ -8197,6 +8199,16 @@ static const struct dis386 mod_table[][2] = {
{ "invlpg", { Mb }, 0 },
{ RM_TABLE (RM_0F01_REG_7_MOD_3) },
},
{
/* MOD_0F02 */
{ "larS", { Gv, Mw }, 0 },
{ "larS", { Gv, Ev }, 0 },
},
{
/* MOD_0F03 */
{ "lslS", { Gv, Mw }, 0 },
{ "lslS", { Gv, Ev }, 0 },
},
{
/* MOD_0F12_PREFIX_0 */
{ "movlpX", { XM, EXq }, 0 },

6
opcodes/i386-opc.tbl
View File

@ -574,14 +574,16 @@ nop, 0x90, None, 0, NoSuf|RepPrefixOk, {}
// Protection control.
arpl, 0x63, None, Cpu286|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16, Reg16|Word|Unspecified|BaseIndex }
lar, 0xf02, None, Cpu286, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
lar, 0xf02, None, Cpu286, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 }
lar, 0xf02, None, Cpu286, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Word|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
lgdt, 0xf01, 2, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Fword|Unspecified|BaseIndex }
lgdt, 0xf01, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
lidt, 0xf01, 3, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Fword|Unspecified|BaseIndex }
lidt, 0xf01, 3, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
lldt, 0xf00, 2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex }
lmsw, 0xf01, 6, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex }
lsl, 0xf03, None, Cpu286, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
lsl, 0xf03, None, Cpu286, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 }
lsl, 0xf03, None, Cpu286, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Word|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
ltr, 0xf00, 3, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex }
sgdt, 0xf01, 0, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Fword|Unspecified|BaseIndex }

34
opcodes/i386-tbl.h
View File

@ -5363,6 +5363,21 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0 } },
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0,
0, 0, 0, 0, 1, 0 } } } },
{ "lar", 0x02, 2, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0 },
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0,
0, 0, 0, 0, 0, 0 } },
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0,
0, 0, 0, 0, 0, 0 } } } },
{ "lar", 0x02, 2, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -5374,7 +5389,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 1, 1, 0, 1, 0,
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0,
0, 0, 0, 0, 1, 0 } },
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0,
0, 0, 0, 0, 0, 0 } } } },
@ -5456,6 +5471,21 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0,
0, 0, 0, 0, 1, 0 } } } },
{ "lsl", 0x03, 2, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0 },
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0,
0, 0, 0, 0, 0, 0 } },
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0,
0, 0, 0, 0, 0, 0 } } } },
{ "lsl", 0x03, 2, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@ -5467,7 +5497,7 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 1, 1, 0, 1, 0,
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0,
0, 0, 0, 0, 1, 0 } },
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0,
0, 0, 0, 0, 0, 0 } } } },