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x86/APX: optimize {nf}-form rotate-by-width-less-1
Unlike for the legacy forms, where there's a difference in the resulting EFLAGS.CF, for the NF variants the immediate can be got rid of in that case by switching to a 1-bit rotate in the opposite direction.
This commit is contained in:
Jan Beulich
parent
0868b8999b
commit
c7eae03eab
@ -4927,6 +4927,7 @@ optimize_encoding (void)
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}
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else if (!optimize_for_space
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&& i.tm.base_opcode == 0xd0
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&& i.tm.extension_opcode == 4
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&& (i.tm.opcode_space == SPACE_BASE
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|| i.tm.opcode_space == SPACE_EVEXMAP4)
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&& !i.mem_operands)
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@ -4942,7 +4943,6 @@ optimize_encoding (void)
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shll $1, %rN, %rM -> addl %rN, %rN, %rM
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shlq $1, %rN, %rM -> addq %rN, %rN, %rM
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*/
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gas_assert (i.tm.extension_opcode == 4);
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i.tm.base_opcode = 0x00;
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i.tm.extension_opcode = None;
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if (i.operands >= 2)
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@ -5403,6 +5403,26 @@ optimize_nf_encoding (void)
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i.imm_operands = 0;
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--i.operands;
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}
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else if (i.tm.base_opcode == 0xc0
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&& i.op[0].imms->X_op == O_constant
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&& i.op[0].imms->X_add_number
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== (i.types[i.operands - 1].bitfield.byte
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|| i.suffix == BYTE_MNEM_SUFFIX
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? 7 : i.types[i.operands - 1].bitfield.word
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|| i.suffix == WORD_MNEM_SUFFIX
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? 15 : 63 >> (i.types[i.operands - 1].bitfield.dword
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|| i.suffix == LONG_MNEM_SUFFIX)))
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{
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/* Optimize: -O:
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{nf} rol $osz-1, ... -> {nf} ror $1, ...
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{nf} ror $osz-1, ... -> {nf} rol $1, ...
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*/
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gas_assert (i.tm.extension_opcode <= 1);
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i.tm.extension_opcode ^= 1;
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i.tm.base_opcode = 0xd0;
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i.tm.operand_types[0].bitfield.imm1 = 1;
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i.imm_operands = 0;
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}
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}
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static void
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@ -1480,4 +1480,36 @@ Disassembly of section \.text:
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[ ]*[a-f0-9]+:[ ]*62 f4 74 1c ff 00[ ]+\{nf\} inc \(%rax\),%ecx
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[ ]*[a-f0-9]+:[ ]*62 f4 fc 0c ff 00[ ]+\{nf\} incq \(%rax\)
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[ ]*[a-f0-9]+:[ ]*62 f4 b4 1c ff 00[ ]+\{nf\} inc \(%rax\),%r9
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[ ]*[a-f0-9]+:[ ]*62 f4 7c 0c d0 ca[ ]+\{nf\} ror \$1,%dl
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[ ]*[a-f0-9]+:[ ]*62 f4 7c 1c d0 ca[ ]+\{nf\} ror \$1,%dl,%al
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[ ]*[a-f0-9]+:[ ]*62 f4 7d 0c d1 ca[ ]+\{nf\} ror \$1,%dx
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[ ]*[a-f0-9]+:[ ]*62 f4 7d 1c d1 ca[ ]+\{nf\} ror \$1,%dx,%ax
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[ ]*[a-f0-9]+:[ ]*62 f4 7c 0c d1 ca[ ]+\{nf\} ror \$1,%edx
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[ ]*[a-f0-9]+:[ ]*62 f4 7c 1c d1 ca[ ]+\{nf\} ror \$1,%edx,%eax
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[ ]*[a-f0-9]+:[ ]*62 f4 fc 0c d1 ca[ ]+\{nf\} ror \$1,%rdx
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[ ]*[a-f0-9]+:[ ]*62 f4 fc 1c d1 ca[ ]+\{nf\} ror \$1,%rdx,%rax
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[ ]*[a-f0-9]+:[ ]*62 f4 7c 0c d0 0a[ ]+\{nf\} rorb \$1,\(%rdx\)
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[ ]*[a-f0-9]+:[ ]*62 f4 7c 1c d0 0a[ ]+\{nf\} ror \$1,\(%rdx\),%al
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[ ]*[a-f0-9]+:[ ]*62 f4 7d 0c d1 0a[ ]+\{nf\} rorw \$1,\(%rdx\)
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[ ]*[a-f0-9]+:[ ]*62 f4 7d 1c d1 0a[ ]+\{nf\} ror \$1,\(%rdx\),%ax
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[ ]*[a-f0-9]+:[ ]*62 f4 7c 0c d1 0a[ ]+\{nf\} rorl \$1,\(%rdx\)
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[ ]*[a-f0-9]+:[ ]*62 f4 7c 1c d1 0a[ ]+\{nf\} ror \$1,\(%rdx\),%eax
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[ ]*[a-f0-9]+:[ ]*62 f4 fc 0c d1 0a[ ]+\{nf\} rorq \$1,\(%rdx\)
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[ ]*[a-f0-9]+:[ ]*62 f4 fc 1c d1 0a[ ]+\{nf\} ror \$1,\(%rdx\),%rax
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[ ]*[a-f0-9]+:[ ]*62 f4 7c 0c d0 c2[ ]+\{nf\} rol \$1,%dl
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[ ]*[a-f0-9]+:[ ]*62 f4 7c 1c d0 c2[ ]+\{nf\} rol \$1,%dl,%al
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[ ]*[a-f0-9]+:[ ]*62 f4 7d 0c d1 c2[ ]+\{nf\} rol \$1,%dx
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[ ]*[a-f0-9]+:[ ]*62 f4 7d 1c d1 c2[ ]+\{nf\} rol \$1,%dx,%ax
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[ ]*[a-f0-9]+:[ ]*62 f4 7c 0c d1 c2[ ]+\{nf\} rol \$1,%edx
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[ ]*[a-f0-9]+:[ ]*62 f4 7c 1c d1 c2[ ]+\{nf\} rol \$1,%edx,%eax
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[ ]*[a-f0-9]+:[ ]*62 f4 fc 0c d1 c2[ ]+\{nf\} rol \$1,%rdx
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[ ]*[a-f0-9]+:[ ]*62 f4 fc 1c d1 c2[ ]+\{nf\} rol \$1,%rdx,%rax
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[ ]*[a-f0-9]+:[ ]*62 f4 7c 0c d0 02[ ]+\{nf\} rolb \$1,\(%rdx\)
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[ ]*[a-f0-9]+:[ ]*62 f4 7c 1c d0 02[ ]+\{nf\} rol \$1,\(%rdx\),%al
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[ ]*[a-f0-9]+:[ ]*62 f4 7d 0c d1 02[ ]+\{nf\} rolw \$1,\(%rdx\)
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[ ]*[a-f0-9]+:[ ]*62 f4 7d 1c d1 02[ ]+\{nf\} rol \$1,\(%rdx\),%ax
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[ ]*[a-f0-9]+:[ ]*62 f4 7c 0c d1 02[ ]+\{nf\} roll \$1,\(%rdx\)
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[ ]*[a-f0-9]+:[ ]*62 f4 7c 1c d1 02[ ]+\{nf\} rol \$1,\(%rdx\),%eax
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[ ]*[a-f0-9]+:[ ]*62 f4 fc 0c d1 02[ ]+\{nf\} rolq \$1,\(%rdx\)
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[ ]*[a-f0-9]+:[ ]*62 f4 fc 1c d1 02[ ]+\{nf\} rol \$1,\(%rdx\),%rax
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#pass
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@ -1433,3 +1433,23 @@ optimize:
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{nf} \op\()q $-1, (%rax)
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{nf} \op $-1, (%rax), %r9
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.endr
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.irp dir, l, r
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{nf} ro\dir $7, %dl
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{nf} ro\dir $7, %dl, %al
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{nf} ro\dir $15, %dx
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{nf} ro\dir $15, %dx, %ax
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{nf} ro\dir $31, %edx
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{nf} ro\dir $31, %edx, %eax
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{nf} ro\dir $63, %rdx
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{nf} ro\dir $63, %rdx, %rax
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{nf} ro\dir\()b $7, (%rdx)
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{nf} ro\dir $7, (%rdx), %al
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{nf} ro\dir\()w $15, (%rdx)
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{nf} ro\dir $15, (%rdx), %ax
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{nf} ro\dir\()l $31, (%rdx)
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{nf} ro\dir $31, (%rdx), %eax
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{nf} ro\dir\()q $63, (%rdx)
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{nf} ro\dir $63, (%rdx), %rax
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.endr
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@ -446,22 +446,22 @@ imulzu, 0x69, APX_F, Modrm|No_bSuf|No_sSuf|RegKludge|EVexMap4|NF/*|ZU*/, { Imm16
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<div>
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<sr:opc:imm8:opt1:nf, +
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rol:0:Imm8|Imm8S::NF, +
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ror:1:Imm8|Imm8S::NF, +
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rcl:2:Imm8::, +
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rcr:3:Imm8::, +
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sal:4:Imm8:Optimize:NF, +
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shl:4:Imm8:Optimize:NF, +
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shr:5:Imm8::NF, +
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sar:7:Imm8::NF>
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<sr:opc:imm8:opt1:opti:nf, +
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rol:0:Imm8|Imm8S::Optimize:NF, +
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ror:1:Imm8|Imm8S::Optimize:NF, +
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rcl:2:Imm8:::, +
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rcr:3:Imm8:::, +
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sal:4:Imm8:Optimize::NF, +
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shl:4:Imm8:Optimize::NF, +
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shr:5:Imm8:::NF, +
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sar:7:Imm8:::NF>
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<sr>, 0xd0/<sr:opc>, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|<sr:opt1>|<sr:nf>, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
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<sr>, 0xd0/<sr:opc>, 0, W|Modrm|No_sSuf|<sr:opt1>, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
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<sr>, 0xd0/<sr:opc>, APX_F, W|Modrm|No_sSuf|EVexMap4|<sr:opt1>|<sr:nf>, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
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<sr>, 0xc0/<sr:opc>, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|<sr:nf>, { <sr:imm8>, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
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<sr>, 0xc0/<sr:opc>, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|<sr:opti>|<sr:nf>, { <sr:imm8>, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
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<sr>, 0xc0/<sr:opc>, i186, W|Modrm|No_sSuf, { <sr:imm8>, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
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<sr>, 0xc0/<sr:opc>, APX_F, W|Modrm|No_sSuf|EVexMap4|<sr:nf>, { <sr:imm8>, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
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<sr>, 0xc0/<sr:opc>, APX_F, W|Modrm|No_sSuf|EVexMap4|<sr:opti>|<sr:nf>, { <sr:imm8>, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
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<sr>, 0xd2/<sr:opc>, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|<sr:nf>, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
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<sr>, 0xd2/<sr:opc>, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
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<sr>, 0xd2/<sr:opc>, APX_F, W|Modrm|No_sSuf|EVexMap4|<sr:nf>, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
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@ -3652,7 +3652,7 @@ static const insn_template i386_optab[] =
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0, 0, 0, 0, 1, 0 } } } },
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{ MN_rol, 0xc0, 3, SPACE_EVEXMAP4, 0,
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{ 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 3, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 3, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
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1, 0 },
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{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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@ -3674,7 +3674,7 @@ static const insn_template i386_optab[] =
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0, 0, 0, 0, 1, 0 } } } },
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{ MN_rol, 0xc0, 2, SPACE_EVEXMAP4, 0,
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{ 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
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1, 0 },
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{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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@ -3756,7 +3756,7 @@ static const insn_template i386_optab[] =
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0, 0, 0, 0, 1, 0 } } } },
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{ MN_ror, 0xc0, 3, SPACE_EVEXMAP4, 1,
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{ 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 3, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 3, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
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1, 0 },
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{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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@ -3778,7 +3778,7 @@ static const insn_template i386_optab[] =
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0, 0, 0, 0, 1, 0 } } } },
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{ MN_ror, 0xc0, 2, SPACE_EVEXMAP4, 1,
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{ 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
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1, 0 },
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{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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