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* m32c.cpu (Imm-8-s4n, Imm-12-s4n): New.
(arith-jnz16-imm4-dst-defn, arith-jnz32-imm4-dst-defn, arith-jnz-imm4-dst-mach, arith-jnz-imm4-dst): Keep track of which imm operand is needed. (adjnz, sbjnz): Pass the right operands. (unary-insn-defn, unary16-defn, unary32-defn, unary-insn-mach, unary-insn): Add -g variants for opcodes that need to support :G. (not.BW:G, push.BW:G): Call it. (stzx16-imm8-imm8-dsp8sb, stzx16-imm8-imm8-dsp8fb, stzx16-imm8-imm8-abs16): Fix operand typos. * m32c.opc (m32c_asm_hash): Support bnCND. (parse_signed4n, print_signed4n): New. * m32c-asm.c: Regenerate. * m32c-desc.c: Regenerate. * m32c-desc.h: Regenerate. * m32c-dis.c: Regenerate. * m32c-ibld.c: Regenerate. * m32c-opc.c: Regenerate. * m32c-opc.h: Regenerate.
This commit is contained in:
DJ Delorie
parent
53dfbcc78f
commit
c6552317c1
@ -1,3 +1,18 @@
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2005-10-27 DJ Delorie <dj@redhat.com>
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* m32c.cpu (Imm-8-s4n, Imm-12-s4n): New.
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(arith-jnz16-imm4-dst-defn, arith-jnz32-imm4-dst-defn,
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arith-jnz-imm4-dst-mach, arith-jnz-imm4-dst): Keep track of which
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imm operand is needed.
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(adjnz, sbjnz): Pass the right operands.
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(unary-insn-defn, unary16-defn, unary32-defn, unary-insn-mach,
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unary-insn): Add -g variants for opcodes that need to support :G.
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(not.BW:G, push.BW:G): Call it.
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(stzx16-imm8-imm8-dsp8sb, stzx16-imm8-imm8-dsp8fb,
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stzx16-imm8-imm8-abs16): Fix operand typos.
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* m32c.opc (m32c_asm_hash): Support bnCND.
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(parse_signed4n, print_signed4n): New.
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2005-10-26 DJ Delorie <dj@redhat.com>
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* m32c.cpu (f-dsp-8-s24, Dsp-8-s24): New.
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132
cpu/m32c.cpu
132
cpu/m32c.cpu
@ -1894,6 +1894,10 @@
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h-sint DFLT f-imm-8-s4
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((parse "signed4")) () ()
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)
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(define-full-operand Imm-8-s4n "negated 4 bit immediate at offset 8 bits" (all-isas)
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h-sint DFLT f-imm-8-s4
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((parse "signed4n")) () ()
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)
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(define-full-operand Imm-sh-8-s4 "signed 4 bit shift immediate at offset 8 bits" (all-isas)
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h-shimm DFLT f-imm-8-s4
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() () ()
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@ -1910,6 +1914,10 @@
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h-sint DFLT f-imm-12-s4
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((parse "signed4")) () ()
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)
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(define-full-operand Imm-12-s4n "negated 4 bit immediate at offset 12 bits" (all-isas)
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h-sint DFLT f-imm-12-s4
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((parse "signed4n") (print "signed4n")) () ()
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)
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(define-full-operand Imm-sh-12-s4 "signed 4 bit shift immediate at offset 12 bits" (all-isas)
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h-shimm DFLT f-imm-12-s4
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() () ()
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@ -5848,24 +5856,31 @@
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; Unary insn macros
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;-------------------------------------------------------------
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(define-pmacro (unary-insn-defn mach group mode wstr op encoding sem)
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(define-pmacro (unary-insn-defn-g mach group mode wstr op encoding sem opg)
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(dni (.sym op mach wstr - group)
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(.str op wstr " dst" mach "-" group "-" mode)
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(.str op wstr opg " dst" mach "-" group "-" mode)
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((machine mach))
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(.str op wstr " ${dst" mach "-" group "-" mode "}")
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(.str op wstr opg " ${dst" mach "-" group "-" mode "}")
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encoding
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(sem mode (.sym dst mach - group - mode))
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())
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)
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(define-pmacro (unary16-defn mode wstr wbit op opc1 opc2 opc3 sem)
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(unary-insn-defn 16 16 mode wstr op
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(+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16- mode))
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sem)
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(define-pmacro (unary-insn-defn mach group mode wstr op encoding sem)
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(unary-insn-defn-g mach group mode wstr op encoding sem "")
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)
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(define-pmacro (unary32-defn mode wstr wbit op opc1 opc2 opc3 sem)
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(define-pmacro (unary16-defn-g mode wstr wbit op opc1 opc2 opc3 sem opg)
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(unary-insn-defn-g 16 16 mode wstr op
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(+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16- mode))
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sem opg)
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)
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(define-pmacro (unary16-defn mode wstr wbit op opc1 opc2 opc3 sem)
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(unary-16-defn-g mode wstr wbit op opc1 opc2 opc3 sem "")
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)
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(define-pmacro (unary32-defn-g mode wstr wbit op opc1 opc2 opc3 sem opg)
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(begin
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; Multi insns are tried for assembly in the reverse order in which they appear here, so
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; define the absolute-indirect insns first in order to prevent them from being selected
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@ -5873,26 +5888,39 @@
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; (unary-insn-defn 32 24-absolute-indirect mode wstr op
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; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (.sym dst32-24-absolute-indirect- mode) (f-18-2 opc2) (f-20-4 opc3))
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; sem)
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(unary-insn-defn 32 16-Unprefixed mode wstr op
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(+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3))
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sem)
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(unary-insn-defn-g 32 16-Unprefixed mode wstr op
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(+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3))
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sem opg)
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; (unary-insn-defn 32 24-indirect mode wstr op
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; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (.sym dst32-24-indirect- mode) (f-18-2 opc2) (f-20-4 opc3))
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; sem)
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)
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)
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(define-pmacro (unary32-defn mode wstr wbit op opc1 opc2 opc3 sem)
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(unary32-defn-g mode wstr wbit op opc1 opc2 opc3 sem "")
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)
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(define-pmacro (unary-insn-mach mach op opc1 opc2 opc3 sem)
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(define-pmacro (unary-insn-mach-g mach op opc1 opc2 opc3 sem opg)
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(begin
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(.apply (.sym unary mach -defn) (QI .b 0 op opc1 opc2 opc3 sem))
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(.apply (.sym unary mach -defn) (HI .w 1 op opc1 opc2 opc3 sem))
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(.apply (.sym unary mach -defn-g) (QI .b 0 op opc1 opc2 opc3 sem opg))
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(.apply (.sym unary mach -defn-g) (HI .w 1 op opc1 opc2 opc3 sem opg))
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)
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)
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(define-pmacro (unary-insn-mach mach op opc1 opc2 opc3 sem)
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(unary-insn-mach-g mach op opc1 opc2 opc3 sem "")
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)
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(define-pmacro (unary-insn op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
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(begin
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(unary-insn-mach 16 op opc16-1 opc16-2 opc16-3 sem)
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(unary-insn-mach 32 op opc32-1 opc32-2 opc32-3 sem)
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(unary-insn-mach-g 16 op opc16-1 opc16-2 opc16-3 sem "")
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(unary-insn-mach-g 32 op opc32-1 opc32-2 opc32-3 sem "")
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)
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)
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(define-pmacro (unary-insn-g op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
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(begin
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(unary-insn-mach-g 16 op opc16-1 opc16-2 opc16-3 sem "$G")
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(unary-insn-mach-g 32 op opc32-1 opc32-2 opc32-3 sem "$G")
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)
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)
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@ -6555,49 +6583,49 @@
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)
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; m16c variants
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(define-pmacro (arith-jnz16-imm4-dst-defn mode wstr wbit op opc1 opc2 sem)
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(define-pmacro (arith-jnz16-imm4-dst-defn mode wstr wbit op i4n opc1 opc2 sem)
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(begin
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(arith-jnz-imm4-dst-defn 16 Imm-8-s4 basic Lab-16-8 mode wstr op
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(+ opc1 opc2 (f-7-1 wbit) Imm-8-s4 (.sym dst16-basic- mode) Lab-16-8)
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(arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) basic Lab-16-8 mode wstr op
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(+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-basic- mode) Lab-16-8)
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sem)
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(arith-jnz-imm4-dst-defn 16 Imm-8-s4 16-16 Lab-32-8 mode wstr op
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(+ opc1 opc2 (f-7-1 wbit) Imm-8-s4 (.sym dst16-16-16- mode) Lab-16-8)
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(arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) 16-16 Lab-32-8 mode wstr op
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(+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-16- mode) Lab-16-8)
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sem)
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(arith-jnz-imm4-dst-defn 16 Imm-8-s4 16-8 Lab-24-8 mode wstr op
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(+ opc1 opc2 (f-7-1 wbit) Imm-8-s4 (.sym dst16-16-8- mode) Lab-16-8)
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(arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) 16-8 Lab-24-8 mode wstr op
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(+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-8- mode) Lab-16-8)
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sem)
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)
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)
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; m32c variants
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(define-pmacro (arith-jnz32-imm4-dst-defn mode wstr wbit op opc1 opc2 sem)
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(define-pmacro (arith-jnz32-imm4-dst-defn mode wstr wbit op i4n opc1 opc2 sem)
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(begin
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(arith-jnz-imm4-dst-defn 32 Imm-12-s4 basic-Unprefixed Lab-16-8 mode wstr op
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(+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) Imm-12-s4 Lab-16-8)
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(arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) basic-Unprefixed Lab-16-8 mode wstr op
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(+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-16-8)
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sem)
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(arith-jnz-imm4-dst-defn 32 Imm-12-s4 16-24-Unprefixed Lab-40-8 mode wstr op
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(+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) Imm-12-s4 Lab-40-8)
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(arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) 16-24-Unprefixed Lab-40-8 mode wstr op
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(+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-40-8)
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sem)
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(arith-jnz-imm4-dst-defn 32 Imm-12-s4 16-16-Unprefixed Lab-32-8 mode wstr op
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(+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) Imm-12-s4 Lab-32-8)
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(arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) 16-16-Unprefixed Lab-32-8 mode wstr op
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(+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-32-8)
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sem)
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(arith-jnz-imm4-dst-defn 32 Imm-12-s4 16-8-Unprefixed Lab-24-8 mode wstr op
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(+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) Imm-12-s4 Lab-24-8)
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(arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) 16-8-Unprefixed Lab-24-8 mode wstr op
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(+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-24-8)
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sem)
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)
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)
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(define-pmacro (arith-jnz-imm4-dst-mach mach op opc1 opc2 sem)
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(define-pmacro (arith-jnz-imm4-dst-mach mach op i4n opc1 opc2 sem)
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(begin
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(.apply (.sym arith-jnz mach -imm4-dst-defn) (QI .b 0 op opc1 opc2 sem))
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(.apply (.sym arith-jnz mach -imm4-dst-defn) (HI .w 1 op opc1 opc2 sem))
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(.apply (.sym arith-jnz mach -imm4-dst-defn) (QI .b 0 op i4n opc1 opc2 sem))
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(.apply (.sym arith-jnz mach -imm4-dst-defn) (HI .w 1 op i4n opc1 opc2 sem))
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)
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)
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(define-pmacro (arith-jnz-imm4-dst op opc16-1 opc16-2 opc32-1 opc32-2 sem)
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(define-pmacro (arith-jnz-imm4-dst op i4n opc16-1 opc16-2 opc32-1 opc32-2 sem)
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(begin
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(arith-jnz-imm4-dst-mach 16 op opc16-1 opc16-2 sem)
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(arith-jnz-imm4-dst-mach 32 op opc32-1 opc32-2 sem)
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(arith-jnz-imm4-dst-mach 16 op i4n opc16-1 opc16-2 sem)
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(arith-jnz-imm4-dst-mach 32 op i4n opc32-1 opc32-2 sem)
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)
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)
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@ -7294,7 +7322,7 @@
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)
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; adjnz.size #imm4,dst,label
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(arith-jnz-imm4-dst adjnz (f-0-4 #xF) (f-4-3 4) #xf #x1 arith-jnz-sem)
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(arith-jnz-imm4-dst adjnz s4 (f-0-4 #xF) (f-4-3 4) #xf #x1 arith-jnz-sem)
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;-------------------------------------------------------------
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; and - binary and
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@ -8928,7 +8956,15 @@
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)
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; not.BW:G
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(unary-insn not (f-0-4 7) (f-4-3 2) (f-8-4 #x7) #xA #x1 #xE not-sem)
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(unary-insn-g not (f-0-4 7) (f-4-3 2) (f-8-4 #x7) #xA #x1 #xE not-sem)
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(dni not16.b.s
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"not.b:s Dst16-3-S-8"
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((machine 16))
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"not.b:s ${Dst16-3-S-8}"
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(+ (f-0-4 #xb) (f-4-1 #x1) Dst16-3-S-8)
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(not-sem QI Dst16-3-S-8)
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())
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;-------------------------------------------------------------
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; nop
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@ -9317,7 +9353,7 @@
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())
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; push.BW:G src (m16 #2)
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(unary-insn-mach 16 push (f-0-4 7) (f-4-3 2) (f-8-4 #x4) push-sem16)
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(unary-insn-mach-g 16 push (f-0-4 7) (f-4-3 2) (f-8-4 #x4) push-sem16 $G)
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; push.BW:G src (m32 #2)
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(unary-insn-mach 32 push #xC #x0 #xE push-sem32)
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@ -9613,7 +9649,7 @@
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)
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; sbjnz.size #imm4,dst,label
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(arith-jnz-imm4-dst sbjnz (f-0-4 #xF) (f-4-3 4) #xf #x1 sub-jnz-sem)
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(arith-jnz-imm4-dst sbjnz s4n (f-0-4 #xF) (f-4-3 4) #xf #x1 sub-jnz-sem)
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;-------------------------------------------------------------
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; sccnd - store condition on condition (m32)
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@ -10143,17 +10179,17 @@
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(stzx-sem QI Imm-8-QI Imm-16-QI (reg h-r0l))
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())
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(dni stzx16-imm8-imm8-dsp8sb "stzx #Imm8,#Imm8,dsp8[sb]" ((machine 16))
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("stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u8[sb]")
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("stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-u8}[sb]")
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(+ (f-0-4 #xD) (f-4-4 #xD) Imm-8-QI Dsp-16-u8 Imm-24-QI)
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(stzx-sem QI Imm-8-QI Imm-16-QI (mem16 QI (add (reg h-sb) Dsp-24-u8)))
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())
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(dni stzx16-imm8-imm8-dsp8fb "stzx #Imm8,#Imm8,dsp8[fb]" ((machine 16))
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("stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u8[fb]")
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(+ (f-0-4 #xD) (f-4-4 #xE) Imm-8-QI Dsp-16-u8 Imm-24-QI)
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(stzx-sem QI Imm-8-QI Imm-16-QI (mem16 QI (add (reg h-fb) Dsp-24-u8)))
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("stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-s8}[fb]")
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(+ (f-0-4 #xD) (f-4-4 #xE) Imm-8-QI Dsp-16-s8 Imm-24-QI)
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(stzx-sem QI Imm-8-QI Imm-24-QI (mem16 QI (add (reg h-fb) Dsp-16-s8)))
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())
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(dni stzx16-imm8-imm8-abs16 "stzx #Imm8,#Imm8,abs16" ((machine 16))
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("stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u16")
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("stzx #${Imm-8-QI},#${Imm-32-QI},${Dsp-16-u16}")
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(+ (f-0-4 #xD) (f-4-4 #xE) Imm-8-QI Dsp-16-u16 Imm-32-QI)
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(stzx-sem QI Imm-8-QI Imm-32-QI (mem16 QI Dsp-16-u16))
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())
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42
cpu/m32c.opc
42
cpu/m32c.opc
@ -69,6 +69,10 @@ m32c_asm_hash (const char *mnem)
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if (mnem[0] == 's' && mnem[1] == 'c')
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return 's';
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/* Don't hash bmCND */
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if (mnem[0] == 'b' && mnem[1] == 'm')
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return 'b';
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|
||||
for (h = 0; *mnem && *mnem != ' ' && *mnem != ':'; ++mnem)
|
||||
h += *mnem;
|
||||
return h % CGEN_ASM_HASH_SIZE;
|
||||
@ -217,6 +221,31 @@ parse_signed4 (CGEN_CPU_DESC cd, const char **strp,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const char *
|
||||
parse_signed4n (CGEN_CPU_DESC cd, const char **strp,
|
||||
int opindex, signed long *valuep)
|
||||
{
|
||||
const char *errmsg = 0;
|
||||
signed long value;
|
||||
long have_zero = 0;
|
||||
|
||||
if (strncmp (*strp, "0x0", 3) == 0
|
||||
|| (**strp == '0' && *(*strp + 1) != 'x'))
|
||||
have_zero = 1;
|
||||
|
||||
PARSE_SIGNED;
|
||||
|
||||
if (value < -7 || value > 8)
|
||||
return _("Immediate is out of range -7 to 8");
|
||||
|
||||
/* If this field may require a relocation then use larger dsp16. */
|
||||
if (! have_zero && value == 0)
|
||||
return _("Immediate is out of range -7 to 8");
|
||||
|
||||
*valuep = -value;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const char *
|
||||
parse_signed8 (CGEN_CPU_DESC cd, const char **strp,
|
||||
int opindex, signed long *valuep)
|
||||
@ -1092,3 +1121,16 @@ print_push_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
{
|
||||
print_regset (cd, dis_info, value, attrs, pc, length, PUSH);
|
||||
}
|
||||
|
||||
static void
|
||||
print_signed4n (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
void * dis_info,
|
||||
signed long value,
|
||||
unsigned int attrs ATTRIBUTE_UNUSED,
|
||||
bfd_vma pc ATTRIBUTE_UNUSED,
|
||||
int length ATTRIBUTE_UNUSED)
|
||||
{
|
||||
disassemble_info *info = dis_info;
|
||||
|
||||
(*info->fprintf_func) (info->stream, "%ld", -value);
|
||||
}
|
||||
|
||||
@ -1,3 +1,13 @@
|
||||
2005-10-27 DJ Delorie <dj@redhat.com>
|
||||
|
||||
* m32c-asm.c: Regenerate.
|
||||
* m32c-desc.c: Regenerate.
|
||||
* m32c-desc.h: Regenerate.
|
||||
* m32c-dis.c: Regenerate.
|
||||
* m32c-ibld.c: Regenerate.
|
||||
* m32c-opc.c: Regenerate.
|
||||
* m32c-opc.h: Regenerate.
|
||||
|
||||
2005-10-26 DJ Delorie <dj@redhat.com>
|
||||
|
||||
* m32c-asm.c: Regenerate.
|
||||
|
||||
@ -191,6 +191,31 @@ parse_signed4 (CGEN_CPU_DESC cd, const char **strp,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const char *
|
||||
parse_signed4n (CGEN_CPU_DESC cd, const char **strp,
|
||||
int opindex, signed long *valuep)
|
||||
{
|
||||
const char *errmsg = 0;
|
||||
signed long value;
|
||||
long have_zero = 0;
|
||||
|
||||
if (strncmp (*strp, "0x0", 3) == 0
|
||||
|| (**strp == '0' && *(*strp + 1) != 'x'))
|
||||
have_zero = 1;
|
||||
|
||||
PARSE_SIGNED;
|
||||
|
||||
if (value < -7 || value > 8)
|
||||
return _("Immediate is out of range -7 to 8");
|
||||
|
||||
/* If this field may require a relocation then use larger dsp16. */
|
||||
if (! have_zero && value == 0)
|
||||
return _("Immediate is out of range -7 to 8");
|
||||
|
||||
*valuep = -value;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const char *
|
||||
parse_signed8 (CGEN_CPU_DESC cd, const char **strp,
|
||||
int opindex, signed long *valuep)
|
||||
@ -1172,6 +1197,9 @@ m32c_cgen_parse_operand (CGEN_CPU_DESC cd,
|
||||
case M32C_OPERAND_IMM_12_S4 :
|
||||
errmsg = parse_signed4 (cd, strp, M32C_OPERAND_IMM_12_S4, (long *) (& fields->f_imm_12_s4));
|
||||
break;
|
||||
case M32C_OPERAND_IMM_12_S4N :
|
||||
errmsg = parse_signed4n (cd, strp, M32C_OPERAND_IMM_12_S4N, (long *) (& fields->f_imm_12_s4));
|
||||
break;
|
||||
case M32C_OPERAND_IMM_13_U3 :
|
||||
errmsg = parse_signed4 (cd, strp, M32C_OPERAND_IMM_13_U3, (long *) (& fields->f_imm_13_u3));
|
||||
break;
|
||||
@ -1241,6 +1269,9 @@ m32c_cgen_parse_operand (CGEN_CPU_DESC cd,
|
||||
case M32C_OPERAND_IMM_8_S4 :
|
||||
errmsg = parse_signed4 (cd, strp, M32C_OPERAND_IMM_8_S4, (long *) (& fields->f_imm_8_s4));
|
||||
break;
|
||||
case M32C_OPERAND_IMM_8_S4N :
|
||||
errmsg = parse_signed4n (cd, strp, M32C_OPERAND_IMM_8_S4N, (long *) (& fields->f_imm_8_s4));
|
||||
break;
|
||||
case M32C_OPERAND_IMM_SH_12_S4 :
|
||||
errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_shimm, & fields->f_imm_12_s4);
|
||||
break;
|
||||
|
||||
@ -1599,6 +1599,10 @@ const CGEN_OPERAND m32c_cgen_operand_table[] =
|
||||
{ "Imm-8-s4", M32C_OPERAND_IMM_8_S4, HW_H_SINT, 8, 4,
|
||||
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_8_S4] } },
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
|
||||
/* Imm-8-s4n: negated 4 bit immediate at offset 8 bits */
|
||||
{ "Imm-8-s4n", M32C_OPERAND_IMM_8_S4N, HW_H_SINT, 8, 4,
|
||||
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_8_S4] } },
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
|
||||
/* Imm-sh-8-s4: signed 4 bit shift immediate at offset 8 bits */
|
||||
{ "Imm-sh-8-s4", M32C_OPERAND_IMM_SH_8_S4, HW_H_SHIMM, 8, 4,
|
||||
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_8_S4] } },
|
||||
@ -1615,6 +1619,10 @@ const CGEN_OPERAND m32c_cgen_operand_table[] =
|
||||
{ "Imm-12-s4", M32C_OPERAND_IMM_12_S4, HW_H_SINT, 12, 4,
|
||||
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_12_S4] } },
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
|
||||
/* Imm-12-s4n: negated 4 bit immediate at offset 12 bits */
|
||||
{ "Imm-12-s4n", M32C_OPERAND_IMM_12_S4N, HW_H_SINT, 12, 4,
|
||||
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_12_S4] } },
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
|
||||
/* Imm-sh-12-s4: signed 4 bit shift immediate at offset 12 bits */
|
||||
{ "Imm-sh-12-s4", M32C_OPERAND_IMM_SH_12_S4, HW_H_SHIMM, 12, 4,
|
||||
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_12_S4] } },
|
||||
@ -12632,212 +12640,212 @@ static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] =
|
||||
M32C_INSN_SCCND_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sccnd-dst32-16-24-absolute-Unprefixed-HI", "sc", 40,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* sbjnz.w #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
|
||||
/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "sbjnz.w", 32,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* sbjnz.w #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
|
||||
/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "sbjnz.w", 32,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* sbjnz.w #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
|
||||
/* sbjnz.w #${Imm-12-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "sbjnz.w", 32,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* sbjnz.w #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
|
||||
/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "sbjnz.w", 40,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* sbjnz.w #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
|
||||
/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "sbjnz.w", 40,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* sbjnz.w #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */
|
||||
/* sbjnz.w #${Imm-12-s4n},${Dsp-16-s16}[fb],${Lab-32-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "sbjnz.w", 40,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* sbjnz.w #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */
|
||||
/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u16},${Lab-32-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "sbjnz.w", 40,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* sbjnz.w #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
|
||||
/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "sbjnz.w", 48,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* sbjnz.w #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */
|
||||
/* sbjnz.w #${Imm-12-s4n},${Dsp-16-u24},${Lab-40-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "sbjnz.w", 48,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* sbjnz.w #${Imm-12-s4},$Dst32RnUnprefixedHI,${Lab-16-8} */
|
||||
/* sbjnz.w #${Imm-12-s4n},$Dst32RnUnprefixedHI,${Lab-16-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "sbjnz32.w-imm4-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "sbjnz.w", 24,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* sbjnz.w #${Imm-12-s4},$Dst32AnUnprefixedHI,${Lab-16-8} */
|
||||
/* sbjnz.w #${Imm-12-s4n},$Dst32AnUnprefixedHI,${Lab-16-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "sbjnz32.w-imm4-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "sbjnz.w", 24,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* sbjnz.w #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */
|
||||
/* sbjnz.w #${Imm-12-s4n},[$Dst32AnUnprefixed],${Lab-16-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "sbjnz32.w-imm4-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "sbjnz.w", 24,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* sbjnz.b #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
|
||||
/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "sbjnz.b", 32,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* sbjnz.b #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
|
||||
/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "sbjnz.b", 32,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* sbjnz.b #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
|
||||
/* sbjnz.b #${Imm-12-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "sbjnz.b", 32,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* sbjnz.b #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
|
||||
/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "sbjnz.b", 40,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* sbjnz.b #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
|
||||
/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "sbjnz.b", 40,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* sbjnz.b #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */
|
||||
/* sbjnz.b #${Imm-12-s4n},${Dsp-16-s16}[fb],${Lab-32-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "sbjnz.b", 40,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* sbjnz.b #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */
|
||||
/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u16},${Lab-32-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "sbjnz.b", 40,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* sbjnz.b #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
|
||||
/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "sbjnz.b", 48,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* sbjnz.b #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */
|
||||
/* sbjnz.b #${Imm-12-s4n},${Dsp-16-u24},${Lab-40-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "sbjnz.b", 48,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* sbjnz.b #${Imm-12-s4},$Dst32RnUnprefixedQI,${Lab-16-8} */
|
||||
/* sbjnz.b #${Imm-12-s4n},$Dst32RnUnprefixedQI,${Lab-16-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "sbjnz32.b-imm4-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "sbjnz.b", 24,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* sbjnz.b #${Imm-12-s4},$Dst32AnUnprefixedQI,${Lab-16-8} */
|
||||
/* sbjnz.b #${Imm-12-s4n},$Dst32AnUnprefixedQI,${Lab-16-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "sbjnz32.b-imm4-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "sbjnz.b", 24,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* sbjnz.b #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */
|
||||
/* sbjnz.b #${Imm-12-s4n},[$Dst32AnUnprefixed],${Lab-16-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "sbjnz32.b-imm4-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "sbjnz.b", 24,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* sbjnz.w #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
|
||||
/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ16_W_IMM4_16_8_DST16_16_8_AN_RELATIVE_HI, "sbjnz16.w-imm4-16-8-dst16-16-8-An-relative-HI", "sbjnz.w", 32,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* sbjnz.w #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
|
||||
/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ16_W_IMM4_16_8_DST16_16_8_SB_RELATIVE_HI, "sbjnz16.w-imm4-16-8-dst16-16-8-SB-relative-HI", "sbjnz.w", 32,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* sbjnz.w #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
|
||||
/* sbjnz.w #${Imm-8-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ16_W_IMM4_16_8_DST16_16_8_FB_RELATIVE_HI, "sbjnz16.w-imm4-16-8-dst16-16-8-FB-relative-HI", "sbjnz.w", 32,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* sbjnz.w #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
|
||||
/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ16_W_IMM4_16_16_DST16_16_16_AN_RELATIVE_HI, "sbjnz16.w-imm4-16-16-dst16-16-16-An-relative-HI", "sbjnz.w", 40,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* sbjnz.w #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
|
||||
/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ16_W_IMM4_16_16_DST16_16_16_SB_RELATIVE_HI, "sbjnz16.w-imm4-16-16-dst16-16-16-SB-relative-HI", "sbjnz.w", 40,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* sbjnz.w #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */
|
||||
/* sbjnz.w #${Imm-8-s4n},${Dsp-16-u16},${Lab-32-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ16_W_IMM4_16_16_DST16_16_16_ABSOLUTE_HI, "sbjnz16.w-imm4-16-16-dst16-16-16-absolute-HI", "sbjnz.w", 40,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* sbjnz.w #${Imm-8-s4},$Dst16RnHI,${Lab-16-8} */
|
||||
/* sbjnz.w #${Imm-8-s4n},$Dst16RnHI,${Lab-16-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ16_W_IMM4_BASIC_DST16_RN_DIRECT_HI, "sbjnz16.w-imm4-basic-dst16-Rn-direct-HI", "sbjnz.w", 24,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* sbjnz.w #${Imm-8-s4},$Dst16AnHI,${Lab-16-8} */
|
||||
/* sbjnz.w #${Imm-8-s4n},$Dst16AnHI,${Lab-16-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ16_W_IMM4_BASIC_DST16_AN_DIRECT_HI, "sbjnz16.w-imm4-basic-dst16-An-direct-HI", "sbjnz.w", 24,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* sbjnz.w #${Imm-8-s4},[$Dst16An],${Lab-16-8} */
|
||||
/* sbjnz.w #${Imm-8-s4n},[$Dst16An],${Lab-16-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ16_W_IMM4_BASIC_DST16_AN_INDIRECT_HI, "sbjnz16.w-imm4-basic-dst16-An-indirect-HI", "sbjnz.w", 24,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* sbjnz.b #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
|
||||
/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ16_B_IMM4_16_8_DST16_16_8_AN_RELATIVE_QI, "sbjnz16.b-imm4-16-8-dst16-16-8-An-relative-QI", "sbjnz.b", 32,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* sbjnz.b #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
|
||||
/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u8}[sb],${Lab-24-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ16_B_IMM4_16_8_DST16_16_8_SB_RELATIVE_QI, "sbjnz16.b-imm4-16-8-dst16-16-8-SB-relative-QI", "sbjnz.b", 32,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* sbjnz.b #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
|
||||
/* sbjnz.b #${Imm-8-s4n},${Dsp-16-s8}[fb],${Lab-24-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ16_B_IMM4_16_8_DST16_16_8_FB_RELATIVE_QI, "sbjnz16.b-imm4-16-8-dst16-16-8-FB-relative-QI", "sbjnz.b", 32,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* sbjnz.b #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
|
||||
/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ16_B_IMM4_16_16_DST16_16_16_AN_RELATIVE_QI, "sbjnz16.b-imm4-16-16-dst16-16-16-An-relative-QI", "sbjnz.b", 40,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* sbjnz.b #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
|
||||
/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u16}[sb],${Lab-32-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ16_B_IMM4_16_16_DST16_16_16_SB_RELATIVE_QI, "sbjnz16.b-imm4-16-16-dst16-16-16-SB-relative-QI", "sbjnz.b", 40,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* sbjnz.b #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */
|
||||
/* sbjnz.b #${Imm-8-s4n},${Dsp-16-u16},${Lab-32-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ16_B_IMM4_16_16_DST16_16_16_ABSOLUTE_QI, "sbjnz16.b-imm4-16-16-dst16-16-16-absolute-QI", "sbjnz.b", 40,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* sbjnz.b #${Imm-8-s4},$Dst16RnQI,${Lab-16-8} */
|
||||
/* sbjnz.b #${Imm-8-s4n},$Dst16RnQI,${Lab-16-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ16_B_IMM4_BASIC_DST16_RN_DIRECT_QI, "sbjnz16.b-imm4-basic-dst16-Rn-direct-QI", "sbjnz.b", 24,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* sbjnz.b #${Imm-8-s4},$Dst16AnQI,${Lab-16-8} */
|
||||
/* sbjnz.b #${Imm-8-s4n},$Dst16AnQI,${Lab-16-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ16_B_IMM4_BASIC_DST16_AN_DIRECT_QI, "sbjnz16.b-imm4-basic-dst16-An-direct-QI", "sbjnz.b", 24,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* sbjnz.b #${Imm-8-s4},[$Dst16An],${Lab-16-8} */
|
||||
/* sbjnz.b #${Imm-8-s4n},[$Dst16An],${Lab-16-8} */
|
||||
{
|
||||
M32C_INSN_SBJNZ16_B_IMM4_BASIC_DST16_AN_INDIRECT_QI, "sbjnz16.b-imm4-basic-dst16-An-indirect-QI", "sbjnz.b", 24,
|
||||
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
@ -16417,92 +16425,92 @@ static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] =
|
||||
M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "push.b", 40,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* push.w $Dst16RnHI */
|
||||
/* push.w${G} $Dst16RnHI */
|
||||
{
|
||||
M32C_INSN_PUSH16_W_16_DST16_RN_DIRECT_HI, "push16.w-16-dst16-Rn-direct-HI", "push.w", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* push.w $Dst16AnHI */
|
||||
/* push.w${G} $Dst16AnHI */
|
||||
{
|
||||
M32C_INSN_PUSH16_W_16_DST16_AN_DIRECT_HI, "push16.w-16-dst16-An-direct-HI", "push.w", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* push.w [$Dst16An] */
|
||||
/* push.w${G} [$Dst16An] */
|
||||
{
|
||||
M32C_INSN_PUSH16_W_16_DST16_AN_INDIRECT_HI, "push16.w-16-dst16-An-indirect-HI", "push.w", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* push.w ${Dsp-16-u8}[$Dst16An] */
|
||||
/* push.w${G} ${Dsp-16-u8}[$Dst16An] */
|
||||
{
|
||||
M32C_INSN_PUSH16_W_16_DST16_16_8_AN_RELATIVE_HI, "push16.w-16-dst16-16-8-An-relative-HI", "push.w", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* push.w ${Dsp-16-u16}[$Dst16An] */
|
||||
/* push.w${G} ${Dsp-16-u16}[$Dst16An] */
|
||||
{
|
||||
M32C_INSN_PUSH16_W_16_DST16_16_16_AN_RELATIVE_HI, "push16.w-16-dst16-16-16-An-relative-HI", "push.w", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* push.w ${Dsp-16-u8}[sb] */
|
||||
/* push.w${G} ${Dsp-16-u8}[sb] */
|
||||
{
|
||||
M32C_INSN_PUSH16_W_16_DST16_16_8_SB_RELATIVE_HI, "push16.w-16-dst16-16-8-SB-relative-HI", "push.w", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* push.w ${Dsp-16-u16}[sb] */
|
||||
/* push.w${G} ${Dsp-16-u16}[sb] */
|
||||
{
|
||||
M32C_INSN_PUSH16_W_16_DST16_16_16_SB_RELATIVE_HI, "push16.w-16-dst16-16-16-SB-relative-HI", "push.w", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* push.w ${Dsp-16-s8}[fb] */
|
||||
/* push.w${G} ${Dsp-16-s8}[fb] */
|
||||
{
|
||||
M32C_INSN_PUSH16_W_16_DST16_16_8_FB_RELATIVE_HI, "push16.w-16-dst16-16-8-FB-relative-HI", "push.w", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* push.w ${Dsp-16-u16} */
|
||||
/* push.w${G} ${Dsp-16-u16} */
|
||||
{
|
||||
M32C_INSN_PUSH16_W_16_DST16_16_16_ABSOLUTE_HI, "push16.w-16-dst16-16-16-absolute-HI", "push.w", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* push.b $Dst16RnQI */
|
||||
/* push.b${G} $Dst16RnQI */
|
||||
{
|
||||
M32C_INSN_PUSH16_B_16_DST16_RN_DIRECT_QI, "push16.b-16-dst16-Rn-direct-QI", "push.b", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* push.b $Dst16AnQI */
|
||||
/* push.b${G} $Dst16AnQI */
|
||||
{
|
||||
M32C_INSN_PUSH16_B_16_DST16_AN_DIRECT_QI, "push16.b-16-dst16-An-direct-QI", "push.b", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* push.b [$Dst16An] */
|
||||
/* push.b${G} [$Dst16An] */
|
||||
{
|
||||
M32C_INSN_PUSH16_B_16_DST16_AN_INDIRECT_QI, "push16.b-16-dst16-An-indirect-QI", "push.b", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* push.b ${Dsp-16-u8}[$Dst16An] */
|
||||
/* push.b${G} ${Dsp-16-u8}[$Dst16An] */
|
||||
{
|
||||
M32C_INSN_PUSH16_B_16_DST16_16_8_AN_RELATIVE_QI, "push16.b-16-dst16-16-8-An-relative-QI", "push.b", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* push.b ${Dsp-16-u16}[$Dst16An] */
|
||||
/* push.b${G} ${Dsp-16-u16}[$Dst16An] */
|
||||
{
|
||||
M32C_INSN_PUSH16_B_16_DST16_16_16_AN_RELATIVE_QI, "push16.b-16-dst16-16-16-An-relative-QI", "push.b", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* push.b ${Dsp-16-u8}[sb] */
|
||||
/* push.b${G} ${Dsp-16-u8}[sb] */
|
||||
{
|
||||
M32C_INSN_PUSH16_B_16_DST16_16_8_SB_RELATIVE_QI, "push16.b-16-dst16-16-8-SB-relative-QI", "push.b", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* push.b ${Dsp-16-u16}[sb] */
|
||||
/* push.b${G} ${Dsp-16-u16}[sb] */
|
||||
{
|
||||
M32C_INSN_PUSH16_B_16_DST16_16_16_SB_RELATIVE_QI, "push16.b-16-dst16-16-16-SB-relative-QI", "push.b", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* push.b ${Dsp-16-s8}[fb] */
|
||||
/* push.b${G} ${Dsp-16-s8}[fb] */
|
||||
{
|
||||
M32C_INSN_PUSH16_B_16_DST16_16_8_FB_RELATIVE_QI, "push16.b-16-dst16-16-8-FB-relative-QI", "push.b", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* push.b ${Dsp-16-u16} */
|
||||
/* push.b${G} ${Dsp-16-u16} */
|
||||
{
|
||||
M32C_INSN_PUSH16_B_16_DST16_16_16_ABSOLUTE_QI, "push16.b-16-dst16-16-16-absolute-QI", "push.b", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
@ -19252,212 +19260,237 @@ static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] =
|
||||
M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "or16.b-imm-G-16-16-dst16-16-16-absolute-QI", "or.b", 40,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* not.w $Dst32RnUnprefixedHI */
|
||||
/* not.b:s r0l */
|
||||
{
|
||||
M32C_INSN_NOT16_B_S_DST16_3_S_R0L_DIRECT_QI, "not16.b.s-dst16-3-S-R0l-direct-QI", "not.b:s", 8,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* not.b:s r0h */
|
||||
{
|
||||
M32C_INSN_NOT16_B_S_DST16_3_S_R0H_DIRECT_QI, "not16.b.s-dst16-3-S-R0h-direct-QI", "not.b:s", 8,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* not.b:s ${Dsp-8-u8}[sb] */
|
||||
{
|
||||
M32C_INSN_NOT16_B_S_DST16_3_S_8_8_SB_RELATIVE_QI, "not16.b.s-dst16-3-S-8-8-SB-relative-QI", "not.b:s", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* not.b:s ${Dsp-8-s8}[fb] */
|
||||
{
|
||||
M32C_INSN_NOT16_B_S_DST16_3_S_8_8_FB_RELATIVE_QI, "not16.b.s-dst16-3-S-8-8-FB-relative-QI", "not.b:s", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* not.b:s ${Dsp-8-u16} */
|
||||
{
|
||||
M32C_INSN_NOT16_B_S_DST16_3_S_8_16_ABSOLUTE_QI, "not16.b.s-dst16-3-S-8-16-absolute-QI", "not.b:s", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* not.w${G} $Dst32RnUnprefixedHI */
|
||||
{
|
||||
M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "not.w", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* not.w $Dst32AnUnprefixedHI */
|
||||
/* not.w${G} $Dst32AnUnprefixedHI */
|
||||
{
|
||||
M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "not.w", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* not.w [$Dst32AnUnprefixed] */
|
||||
/* not.w${G} [$Dst32AnUnprefixed] */
|
||||
{
|
||||
M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "not.w", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* not.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
||||
/* not.w${G} ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
||||
{
|
||||
M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "not.w", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* not.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
||||
/* not.w${G} ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
||||
{
|
||||
M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "not.w", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* not.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
||||
/* not.w${G} ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
||||
{
|
||||
M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "not.w", 40,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* not.w ${Dsp-16-u8}[sb] */
|
||||
/* not.w${G} ${Dsp-16-u8}[sb] */
|
||||
{
|
||||
M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "not.w", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* not.w ${Dsp-16-u16}[sb] */
|
||||
/* not.w${G} ${Dsp-16-u16}[sb] */
|
||||
{
|
||||
M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "not.w", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* not.w ${Dsp-16-s8}[fb] */
|
||||
/* not.w${G} ${Dsp-16-s8}[fb] */
|
||||
{
|
||||
M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "not.w", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* not.w ${Dsp-16-s16}[fb] */
|
||||
/* not.w${G} ${Dsp-16-s16}[fb] */
|
||||
{
|
||||
M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "not.w", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* not.w ${Dsp-16-u16} */
|
||||
/* not.w${G} ${Dsp-16-u16} */
|
||||
{
|
||||
M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "not.w", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* not.w ${Dsp-16-u24} */
|
||||
/* not.w${G} ${Dsp-16-u24} */
|
||||
{
|
||||
M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "not.w", 40,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* not.b $Dst32RnUnprefixedQI */
|
||||
/* not.b${G} $Dst32RnUnprefixedQI */
|
||||
{
|
||||
M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "not.b", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* not.b $Dst32AnUnprefixedQI */
|
||||
/* not.b${G} $Dst32AnUnprefixedQI */
|
||||
{
|
||||
M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "not.b", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* not.b [$Dst32AnUnprefixed] */
|
||||
/* not.b${G} [$Dst32AnUnprefixed] */
|
||||
{
|
||||
M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "not.b", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* not.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
||||
/* not.b${G} ${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
||||
{
|
||||
M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "not.b", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* not.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
||||
/* not.b${G} ${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
||||
{
|
||||
M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "not.b", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* not.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
||||
/* not.b${G} ${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
||||
{
|
||||
M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "not.b", 40,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* not.b ${Dsp-16-u8}[sb] */
|
||||
/* not.b${G} ${Dsp-16-u8}[sb] */
|
||||
{
|
||||
M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "not.b", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* not.b ${Dsp-16-u16}[sb] */
|
||||
/* not.b${G} ${Dsp-16-u16}[sb] */
|
||||
{
|
||||
M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "not.b", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* not.b ${Dsp-16-s8}[fb] */
|
||||
/* not.b${G} ${Dsp-16-s8}[fb] */
|
||||
{
|
||||
M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "not.b", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* not.b ${Dsp-16-s16}[fb] */
|
||||
/* not.b${G} ${Dsp-16-s16}[fb] */
|
||||
{
|
||||
M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "not.b", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* not.b ${Dsp-16-u16} */
|
||||
/* not.b${G} ${Dsp-16-u16} */
|
||||
{
|
||||
M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "not.b", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* not.b ${Dsp-16-u24} */
|
||||
/* not.b${G} ${Dsp-16-u24} */
|
||||
{
|
||||
M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "not.b", 40,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* not.w $Dst16RnHI */
|
||||
/* not.w${G} $Dst16RnHI */
|
||||
{
|
||||
M32C_INSN_NOT16_W_16_DST16_RN_DIRECT_HI, "not16.w-16-dst16-Rn-direct-HI", "not.w", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* not.w $Dst16AnHI */
|
||||
/* not.w${G} $Dst16AnHI */
|
||||
{
|
||||
M32C_INSN_NOT16_W_16_DST16_AN_DIRECT_HI, "not16.w-16-dst16-An-direct-HI", "not.w", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* not.w [$Dst16An] */
|
||||
/* not.w${G} [$Dst16An] */
|
||||
{
|
||||
M32C_INSN_NOT16_W_16_DST16_AN_INDIRECT_HI, "not16.w-16-dst16-An-indirect-HI", "not.w", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* not.w ${Dsp-16-u8}[$Dst16An] */
|
||||
/* not.w${G} ${Dsp-16-u8}[$Dst16An] */
|
||||
{
|
||||
M32C_INSN_NOT16_W_16_DST16_16_8_AN_RELATIVE_HI, "not16.w-16-dst16-16-8-An-relative-HI", "not.w", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* not.w ${Dsp-16-u16}[$Dst16An] */
|
||||
/* not.w${G} ${Dsp-16-u16}[$Dst16An] */
|
||||
{
|
||||
M32C_INSN_NOT16_W_16_DST16_16_16_AN_RELATIVE_HI, "not16.w-16-dst16-16-16-An-relative-HI", "not.w", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* not.w ${Dsp-16-u8}[sb] */
|
||||
/* not.w${G} ${Dsp-16-u8}[sb] */
|
||||
{
|
||||
M32C_INSN_NOT16_W_16_DST16_16_8_SB_RELATIVE_HI, "not16.w-16-dst16-16-8-SB-relative-HI", "not.w", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* not.w ${Dsp-16-u16}[sb] */
|
||||
/* not.w${G} ${Dsp-16-u16}[sb] */
|
||||
{
|
||||
M32C_INSN_NOT16_W_16_DST16_16_16_SB_RELATIVE_HI, "not16.w-16-dst16-16-16-SB-relative-HI", "not.w", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* not.w ${Dsp-16-s8}[fb] */
|
||||
/* not.w${G} ${Dsp-16-s8}[fb] */
|
||||
{
|
||||
M32C_INSN_NOT16_W_16_DST16_16_8_FB_RELATIVE_HI, "not16.w-16-dst16-16-8-FB-relative-HI", "not.w", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* not.w ${Dsp-16-u16} */
|
||||
/* not.w${G} ${Dsp-16-u16} */
|
||||
{
|
||||
M32C_INSN_NOT16_W_16_DST16_16_16_ABSOLUTE_HI, "not16.w-16-dst16-16-16-absolute-HI", "not.w", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* not.b $Dst16RnQI */
|
||||
/* not.b${G} $Dst16RnQI */
|
||||
{
|
||||
M32C_INSN_NOT16_B_16_DST16_RN_DIRECT_QI, "not16.b-16-dst16-Rn-direct-QI", "not.b", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* not.b $Dst16AnQI */
|
||||
/* not.b${G} $Dst16AnQI */
|
||||
{
|
||||
M32C_INSN_NOT16_B_16_DST16_AN_DIRECT_QI, "not16.b-16-dst16-An-direct-QI", "not.b", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* not.b [$Dst16An] */
|
||||
/* not.b${G} [$Dst16An] */
|
||||
{
|
||||
M32C_INSN_NOT16_B_16_DST16_AN_INDIRECT_QI, "not16.b-16-dst16-An-indirect-QI", "not.b", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* not.b ${Dsp-16-u8}[$Dst16An] */
|
||||
/* not.b${G} ${Dsp-16-u8}[$Dst16An] */
|
||||
{
|
||||
M32C_INSN_NOT16_B_16_DST16_16_8_AN_RELATIVE_QI, "not16.b-16-dst16-16-8-An-relative-QI", "not.b", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* not.b ${Dsp-16-u16}[$Dst16An] */
|
||||
/* not.b${G} ${Dsp-16-u16}[$Dst16An] */
|
||||
{
|
||||
M32C_INSN_NOT16_B_16_DST16_16_16_AN_RELATIVE_QI, "not16.b-16-dst16-16-16-An-relative-QI", "not.b", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* not.b ${Dsp-16-u8}[sb] */
|
||||
/* not.b${G} ${Dsp-16-u8}[sb] */
|
||||
{
|
||||
M32C_INSN_NOT16_B_16_DST16_16_8_SB_RELATIVE_QI, "not16.b-16-dst16-16-8-SB-relative-QI", "not.b", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* not.b ${Dsp-16-u16}[sb] */
|
||||
/* not.b${G} ${Dsp-16-u16}[sb] */
|
||||
{
|
||||
M32C_INSN_NOT16_B_16_DST16_16_16_SB_RELATIVE_QI, "not16.b-16-dst16-16-16-SB-relative-QI", "not.b", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* not.b ${Dsp-16-s8}[fb] */
|
||||
/* not.b${G} ${Dsp-16-s8}[fb] */
|
||||
{
|
||||
M32C_INSN_NOT16_B_16_DST16_16_8_FB_RELATIVE_QI, "not16.b-16-dst16-16-8-FB-relative-QI", "not.b", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* not.b ${Dsp-16-u16} */
|
||||
/* not.b${G} ${Dsp-16-u16} */
|
||||
{
|
||||
M32C_INSN_NOT16_B_16_DST16_16_16_ABSOLUTE_QI, "not16.b-16-dst16-16-16-absolute-QI", "not.b", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
@ -62577,17 +62610,17 @@ static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] =
|
||||
M32C_INSN_STZX16_IMM8_IMM8_R0L, "stzx16-imm8-imm8-r0l", "stzx", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u8[sb] */
|
||||
/* stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-u8}[sb] */
|
||||
{
|
||||
M32C_INSN_STZX16_IMM8_IMM8_DSP8SB, "stzx16-imm8-imm8-dsp8sb", "stzx", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u8[fb] */
|
||||
/* stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-s8}[fb] */
|
||||
{
|
||||
M32C_INSN_STZX16_IMM8_IMM8_DSP8FB, "stzx16-imm8-imm8-dsp8fb", "stzx", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u16 */
|
||||
/* stzx #${Imm-8-QI},#${Imm-32-QI},${Dsp-16-u16} */
|
||||
{
|
||||
M32C_INSN_STZX16_IMM8_IMM8_ABS16, "stzx16-imm8-imm8-abs16", "stzx", 40,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
|
||||
@ -50,7 +50,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
#define CGEN_INT_INSN_P 0
|
||||
|
||||
/* Maximum number of syntax elements in an instruction. */
|
||||
#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 26
|
||||
#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 21
|
||||
|
||||
/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
|
||||
e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
|
||||
@ -217,201 +217,202 @@ typedef enum cgen_operand_type {
|
||||
, M32C_OPERAND_DSP_32_U24, M32C_OPERAND_DSP_32_U20, M32C_OPERAND_DSP_32_S8, M32C_OPERAND_DSP_32_S16
|
||||
, M32C_OPERAND_DSP_40_U8, M32C_OPERAND_DSP_40_S8, M32C_OPERAND_DSP_40_U16, M32C_OPERAND_DSP_40_S16
|
||||
, M32C_OPERAND_DSP_40_U24, M32C_OPERAND_DSP_48_U8, M32C_OPERAND_DSP_48_S8, M32C_OPERAND_DSP_48_U16
|
||||
, M32C_OPERAND_DSP_48_S16, M32C_OPERAND_DSP_48_U24, M32C_OPERAND_IMM_8_S4, M32C_OPERAND_IMM_SH_8_S4
|
||||
, M32C_OPERAND_IMM_8_QI, M32C_OPERAND_IMM_8_HI, M32C_OPERAND_IMM_12_S4, M32C_OPERAND_IMM_SH_12_S4
|
||||
, M32C_OPERAND_IMM_13_U3, M32C_OPERAND_IMM_20_S4, M32C_OPERAND_IMM_SH_20_S4, M32C_OPERAND_IMM_16_QI
|
||||
, M32C_OPERAND_IMM_16_HI, M32C_OPERAND_IMM_16_SI, M32C_OPERAND_IMM_24_QI, M32C_OPERAND_IMM_24_HI
|
||||
, M32C_OPERAND_IMM_24_SI, M32C_OPERAND_IMM_32_QI, M32C_OPERAND_IMM_32_SI, M32C_OPERAND_IMM_32_HI
|
||||
, M32C_OPERAND_IMM_40_QI, M32C_OPERAND_IMM_40_HI, M32C_OPERAND_IMM_40_SI, M32C_OPERAND_IMM_48_QI
|
||||
, M32C_OPERAND_IMM_48_HI, M32C_OPERAND_IMM_48_SI, M32C_OPERAND_IMM_56_QI, M32C_OPERAND_IMM_56_HI
|
||||
, M32C_OPERAND_IMM_64_HI, M32C_OPERAND_IMM1_S, M32C_OPERAND_IMM3_S, M32C_OPERAND_BITNO16R
|
||||
, M32C_OPERAND_BITNO32PREFIXED, M32C_OPERAND_BITNO32UNPREFIXED, M32C_OPERAND_BITBASE16_16_U8, M32C_OPERAND_BITBASE16_16_S8
|
||||
, M32C_OPERAND_BITBASE16_16_U16, M32C_OPERAND_BITBASE16_8_U11_S, M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED, M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED
|
||||
, M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED, M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED, M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED, M32C_OPERAND_BITBASE32_24_U11_PREFIXED
|
||||
, M32C_OPERAND_BITBASE32_24_S11_PREFIXED, M32C_OPERAND_BITBASE32_24_U19_PREFIXED, M32C_OPERAND_BITBASE32_24_S19_PREFIXED, M32C_OPERAND_BITBASE32_24_U27_PREFIXED
|
||||
, M32C_OPERAND_LAB_5_3, M32C_OPERAND_LAB32_JMP_S, M32C_OPERAND_LAB_8_8, M32C_OPERAND_LAB_8_16
|
||||
, M32C_OPERAND_LAB_8_24, M32C_OPERAND_LAB_16_8, M32C_OPERAND_LAB_24_8, M32C_OPERAND_LAB_32_8
|
||||
, M32C_OPERAND_LAB_40_8, M32C_OPERAND_SBIT, M32C_OPERAND_OBIT, M32C_OPERAND_ZBIT
|
||||
, M32C_OPERAND_CBIT, M32C_OPERAND_UBIT, M32C_OPERAND_IBIT, M32C_OPERAND_BBIT
|
||||
, M32C_OPERAND_DBIT, M32C_OPERAND_COND16_16, M32C_OPERAND_COND16_24, M32C_OPERAND_COND16_32
|
||||
, M32C_OPERAND_COND32_16, M32C_OPERAND_COND32_24, M32C_OPERAND_COND32_32, M32C_OPERAND_COND32_40
|
||||
, M32C_OPERAND_COND16C, M32C_OPERAND_COND16J, M32C_OPERAND_COND16J5, M32C_OPERAND_COND32
|
||||
, M32C_OPERAND_COND32J, M32C_OPERAND_SCCOND32, M32C_OPERAND_FLAGS16, M32C_OPERAND_FLAGS32
|
||||
, M32C_OPERAND_CR16, M32C_OPERAND_CR1_UNPREFIXED_32, M32C_OPERAND_CR1_PREFIXED_32, M32C_OPERAND_CR2_32
|
||||
, M32C_OPERAND_CR3_UNPREFIXED_32, M32C_OPERAND_CR3_PREFIXED_32, M32C_OPERAND_Z, M32C_OPERAND_S
|
||||
, M32C_OPERAND_Q, M32C_OPERAND_G, M32C_OPERAND_X, M32C_OPERAND_SIZE
|
||||
, M32C_OPERAND_BITINDEX, M32C_OPERAND_SRCINDEX, M32C_OPERAND_DSTINDEX, M32C_OPERAND_NOREMAINDER
|
||||
, M32C_OPERAND_SRC16_RN_DIRECT_QI, M32C_OPERAND_SRC16_RN_DIRECT_HI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_QI
|
||||
, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_HI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_SI
|
||||
, M32C_OPERAND_SRC16_AN_DIRECT_QI, M32C_OPERAND_SRC16_AN_DIRECT_HI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_HI
|
||||
, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_HI, M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_SI
|
||||
, M32C_OPERAND_SRC16_AN_INDIRECT_QI, M32C_OPERAND_SRC16_AN_INDIRECT_HI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_QI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_HI
|
||||
, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_SI, M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_HI, M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_SI
|
||||
, M32C_OPERAND_SRC16_16_8_SB_RELATIVE_QI, M32C_OPERAND_SRC16_16_16_SB_RELATIVE_QI, M32C_OPERAND_SRC16_16_8_FB_RELATIVE_QI, M32C_OPERAND_SRC16_16_8_AN_RELATIVE_QI
|
||||
, M32C_OPERAND_SRC16_16_16_AN_RELATIVE_QI, M32C_OPERAND_SRC16_16_8_SB_RELATIVE_HI, M32C_OPERAND_SRC16_16_16_SB_RELATIVE_HI, M32C_OPERAND_SRC16_16_8_FB_RELATIVE_HI
|
||||
, M32C_OPERAND_SRC16_16_8_AN_RELATIVE_HI, M32C_OPERAND_SRC16_16_16_AN_RELATIVE_HI, M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_QI
|
||||
, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_QI
|
||||
, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_HI
|
||||
, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_HI
|
||||
, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_SI
|
||||
, M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_SI
|
||||
, M32C_OPERAND_SRC16_16_16_ABSOLUTE_QI, M32C_OPERAND_SRC16_16_16_ABSOLUTE_HI, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_HI
|
||||
, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_SRC16_2_S_8_SB_RELATIVE_QI, M32C_OPERAND_SRC16_2_S_8_FB_RELATIVE_QI
|
||||
, M32C_OPERAND_SRC16_2_S_16_ABSOLUTE_QI, M32C_OPERAND_SRC32_2_S_8_SB_RELATIVE_QI, M32C_OPERAND_SRC32_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_SRC32_2_S_16_ABSOLUTE_QI
|
||||
, M32C_OPERAND_SRC32_2_S_8_SB_RELATIVE_HI, M32C_OPERAND_SRC32_2_S_8_FB_RELATIVE_HI, M32C_OPERAND_SRC32_2_S_16_ABSOLUTE_HI, M32C_OPERAND_DST16_RN_DIRECT_QI
|
||||
, M32C_OPERAND_DST16_RN_DIRECT_HI, M32C_OPERAND_DST16_RN_DIRECT_SI, M32C_OPERAND_DST16_RN_DIRECT_EXT_QI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_QI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_HI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_SI, M32C_OPERAND_DST32_RN_DIRECT_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_RN_DIRECT_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_R3_DIRECT_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST16_AN_DIRECT_QI, M32C_OPERAND_DST16_AN_DIRECT_HI, M32C_OPERAND_DST16_AN_DIRECT_SI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_QI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_HI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_SI, M32C_OPERAND_DST16_AN_INDIRECT_QI, M32C_OPERAND_DST16_AN_INDIRECT_HI, M32C_OPERAND_DST16_AN_INDIRECT_SI
|
||||
, M32C_OPERAND_DST16_AN_INDIRECT_EXT_QI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_HI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_SI, M32C_OPERAND_DST32_AN_INDIRECT_EXTUNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_AN_INDIRECT_EXTUNPREFIXED_HI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_QI
|
||||
, M32C_OPERAND_DST16_16_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_QI
|
||||
, M32C_OPERAND_DST16_24_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_24_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_32_8_SB_RELATIVE_QI
|
||||
, M32C_OPERAND_DST16_32_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_32_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_32_16_AN_RELATIVE_QI
|
||||
, M32C_OPERAND_DST16_40_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_40_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_40_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_QI
|
||||
, M32C_OPERAND_DST16_40_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_48_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_48_8_FB_RELATIVE_QI
|
||||
, M32C_OPERAND_DST16_48_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_48_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_HI
|
||||
, M32C_OPERAND_DST16_16_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_HI
|
||||
, M32C_OPERAND_DST16_24_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_24_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_24_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_HI
|
||||
, M32C_OPERAND_DST16_32_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_32_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_32_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_HI
|
||||
, M32C_OPERAND_DST16_32_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_40_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_40_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_40_8_FB_RELATIVE_HI
|
||||
, M32C_OPERAND_DST16_40_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_40_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_48_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_HI
|
||||
, M32C_OPERAND_DST16_48_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_48_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_48_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_SI
|
||||
, M32C_OPERAND_DST16_16_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_SI
|
||||
, M32C_OPERAND_DST16_24_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_24_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_24_8_AN_RELATIVE_SI
|
||||
, M32C_OPERAND_DST16_24_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_32_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_32_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_32_8_FB_RELATIVE_SI
|
||||
, M32C_OPERAND_DST16_32_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_32_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_40_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_40_16_SB_RELATIVE_SI
|
||||
, M32C_OPERAND_DST16_40_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_40_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_48_8_SB_RELATIVE_SI
|
||||
, M32C_OPERAND_DST16_48_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_48_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_48_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_48_16_AN_RELATIVE_SI
|
||||
, M32C_OPERAND_DST16_16_8_SB_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_EXT_QI
|
||||
, M32C_OPERAND_DST16_16_16_AN_RELATIVE_EXT_QI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST16_16_16_ABSOLUTE_QI
|
||||
, M32C_OPERAND_DST16_24_16_ABSOLUTE_QI, M32C_OPERAND_DST16_32_16_ABSOLUTE_QI, M32C_OPERAND_DST16_40_16_ABSOLUTE_QI, M32C_OPERAND_DST16_48_16_ABSOLUTE_QI
|
||||
, M32C_OPERAND_DST16_16_16_ABSOLUTE_HI, M32C_OPERAND_DST16_24_16_ABSOLUTE_HI, M32C_OPERAND_DST16_32_16_ABSOLUTE_HI, M32C_OPERAND_DST16_40_16_ABSOLUTE_HI
|
||||
, M32C_OPERAND_DST16_48_16_ABSOLUTE_HI, M32C_OPERAND_DST16_16_16_ABSOLUTE_SI, M32C_OPERAND_DST16_24_16_ABSOLUTE_SI, M32C_OPERAND_DST16_32_16_ABSOLUTE_SI
|
||||
, M32C_OPERAND_DST16_40_16_ABSOLUTE_SI, M32C_OPERAND_DST16_48_16_ABSOLUTE_SI, M32C_OPERAND_DST16_16_16_ABSOLUTE_EXT_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_HI, M32C_OPERAND_BIT16_RN_DIRECT
|
||||
, M32C_OPERAND_BIT32_RN_DIRECT_UNPREFIXED, M32C_OPERAND_BIT32_RN_DIRECT_PREFIXED, M32C_OPERAND_BIT16_AN_DIRECT, M32C_OPERAND_BIT32_AN_DIRECT_UNPREFIXED
|
||||
, M32C_OPERAND_BIT32_AN_DIRECT_PREFIXED, M32C_OPERAND_BIT16_AN_INDIRECT, M32C_OPERAND_BIT32_AN_INDIRECT_UNPREFIXED, M32C_OPERAND_BIT32_AN_INDIRECT_PREFIXED
|
||||
, M32C_OPERAND_BIT16_16_8_SB_RELATIVE, M32C_OPERAND_BIT16_16_16_SB_RELATIVE, M32C_OPERAND_BIT16_16_8_FB_RELATIVE, M32C_OPERAND_BIT16_16_8_AN_RELATIVE
|
||||
, M32C_OPERAND_BIT16_16_16_AN_RELATIVE, M32C_OPERAND_BIT32_16_11_SB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_19_SB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_11_FB_RELATIVE_UNPREFIXED
|
||||
, M32C_OPERAND_BIT32_16_19_FB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_11_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_27_AN_RELATIVE_UNPREFIXED
|
||||
, M32C_OPERAND_BIT32_24_11_SB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_19_SB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_11_FB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_19_FB_RELATIVE_PREFIXED
|
||||
, M32C_OPERAND_BIT32_24_11_AN_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_19_AN_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_27_AN_RELATIVE_PREFIXED, M32C_OPERAND_BIT16_11_SB_RELATIVE_S
|
||||
, M32C_OPERAND_RN16_PUSH_S_DERIVED, M32C_OPERAND_AN16_PUSH_S_DERIVED, M32C_OPERAND_BIT16_16_16_ABSOLUTE, M32C_OPERAND_BIT32_16_19_ABSOLUTE_UNPREFIXED
|
||||
, M32C_OPERAND_BIT32_16_27_ABSOLUTE_UNPREFIXED, M32C_OPERAND_BIT32_24_19_ABSOLUTE_PREFIXED, M32C_OPERAND_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_OPERAND_DST16_3_S_R0L_DIRECT_QI
|
||||
, M32C_OPERAND_DST16_3_S_R0H_DIRECT_QI, M32C_OPERAND_DST16_3_S_8_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_8_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_8_16_ABSOLUTE_QI
|
||||
, M32C_OPERAND_DST16_3_S_16_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_16_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_16_16_ABSOLUTE_QI, M32C_OPERAND_SRCDST16_R0L_R0H_S_DERIVED
|
||||
, M32C_OPERAND_DST32_2_S_R0L_DIRECT_QI, M32C_OPERAND_DST32_2_S_R0_DIRECT_HI, M32C_OPERAND_DST32_1_S_A0_DIRECT_HI, M32C_OPERAND_DST32_1_S_A1_DIRECT_HI
|
||||
, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_QI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_DST32_2_S_16_ABSOLUTE_QI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_HI
|
||||
, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_HI, M32C_OPERAND_DST32_2_S_16_ABSOLUTE_HI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_SI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_SI
|
||||
, M32C_OPERAND_DST32_2_S_16_ABSOLUTE_SI, M32C_OPERAND_SRC16_BASIC_QI, M32C_OPERAND_SRC16_BASIC_HI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_QI
|
||||
, M32C_OPERAND_SRC32_BASIC_PREFIXED_QI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_HI, M32C_OPERAND_SRC32_BASIC_PREFIXED_HI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_SI
|
||||
, M32C_OPERAND_SRC32_BASIC_PREFIXED_SI, M32C_OPERAND_SRC32_BASIC_EXTPREFIXED_QI, M32C_OPERAND_SRC16_16_8_QI, M32C_OPERAND_SRC16_16_16_QI
|
||||
, M32C_OPERAND_SRC16_16_8_HI, M32C_OPERAND_SRC16_16_16_HI, M32C_OPERAND_SRC32_16_8_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_UNPREFIXED_QI
|
||||
, M32C_OPERAND_SRC32_16_24_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_HI
|
||||
, M32C_OPERAND_SRC32_16_8_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_8_PREFIXED_QI
|
||||
, M32C_OPERAND_SRC32_24_16_PREFIXED_QI, M32C_OPERAND_SRC32_24_24_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_PREFIXED_HI
|
||||
, M32C_OPERAND_SRC32_24_24_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_PREFIXED_SI
|
||||
, M32C_OPERAND_DST16_BASIC_QI, M32C_OPERAND_DST16_BASIC_HI, M32C_OPERAND_DST16_BASIC_SI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_BASIC_PREFIXED_QI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_HI, M32C_OPERAND_DST32_BASIC_PREFIXED_HI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_BASIC_PREFIXED_SI, M32C_OPERAND_DST16_16_QI, M32C_OPERAND_DST16_16_8_QI, M32C_OPERAND_DST16_16_16_QI
|
||||
, M32C_OPERAND_DST16_16_HI, M32C_OPERAND_DST16_16_8_HI, M32C_OPERAND_DST16_16_16_HI, M32C_OPERAND_DST16_16_SI
|
||||
, M32C_OPERAND_DST16_16_8_SI, M32C_OPERAND_DST16_16_16_SI, M32C_OPERAND_DST16_16_EXT_QI, M32C_OPERAND_DST16_AN_INDIRECT_MOVA_HI
|
||||
, M32C_OPERAND_DST16_16_8_AN_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_MOVA_HI
|
||||
, M32C_OPERAND_DST16_16_8_FB_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_16_ABSOLUTE_MOVA_HI, M32C_OPERAND_DST16_16_MOVA_HI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI
|
||||
, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI
|
||||
, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI
|
||||
, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_16_16_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_UNPREFIXED_QI, M32C_OPERAND_DST32_16_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_16_16_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_UNPREFIXED_HI, M32C_OPERAND_DST32_16_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_16_16_UNPREFIXED_SI, M32C_OPERAND_DST32_16_24_UNPREFIXED_SI, M32C_OPERAND_DST32_16_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_EXTUNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_16_UNPREFIXED_MULEX_HI, M32C_OPERAND_DST16_24_QI, M32C_OPERAND_DST16_24_HI, M32C_OPERAND_DST32_24_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_24_PREFIXED_QI, M32C_OPERAND_DST32_24_8_PREFIXED_QI, M32C_OPERAND_DST32_24_16_PREFIXED_QI, M32C_OPERAND_DST32_24_24_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_24_UNPREFIXED_HI, M32C_OPERAND_DST32_24_PREFIXED_HI, M32C_OPERAND_DST32_24_8_PREFIXED_HI, M32C_OPERAND_DST32_24_16_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_24_24_PREFIXED_HI, M32C_OPERAND_DST32_24_UNPREFIXED_SI, M32C_OPERAND_DST32_24_PREFIXED_SI, M32C_OPERAND_DST32_24_8_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_24_16_PREFIXED_SI, M32C_OPERAND_DST32_24_24_PREFIXED_SI, M32C_OPERAND_DST16_32_QI, M32C_OPERAND_DST16_32_HI
|
||||
, M32C_OPERAND_DST32_32_UNPREFIXED_QI, M32C_OPERAND_DST32_32_PREFIXED_QI, M32C_OPERAND_DST32_32_UNPREFIXED_HI, M32C_OPERAND_DST32_32_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_32_UNPREFIXED_SI, M32C_OPERAND_DST32_32_PREFIXED_SI, M32C_OPERAND_DST32_40_UNPREFIXED_QI, M32C_OPERAND_DST32_40_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_40_UNPREFIXED_HI, M32C_OPERAND_DST32_40_PREFIXED_HI, M32C_OPERAND_DST32_40_UNPREFIXED_SI, M32C_OPERAND_DST32_40_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_48_PREFIXED_QI, M32C_OPERAND_DST32_48_PREFIXED_HI, M32C_OPERAND_DST32_48_PREFIXED_SI, M32C_OPERAND_BIT16_16
|
||||
, M32C_OPERAND_BIT16_16_BASIC, M32C_OPERAND_BIT16_16_8, M32C_OPERAND_BIT16_16_16, M32C_OPERAND_BIT32_16_UNPREFIXED
|
||||
, M32C_OPERAND_BIT32_24_PREFIXED, M32C_OPERAND_BIT32_BASIC_UNPREFIXED, M32C_OPERAND_BIT32_16_8_UNPREFIXED, M32C_OPERAND_BIT32_16_16_UNPREFIXED
|
||||
, M32C_OPERAND_BIT32_16_24_UNPREFIXED, M32C_OPERAND_SRC16_2_S, M32C_OPERAND_SRC32_2_S_QI, M32C_OPERAND_SRC32_2_S_HI
|
||||
, M32C_OPERAND_DST16_3_S_8, M32C_OPERAND_DST16_3_S_16, M32C_OPERAND_SRCDST16_R0L_R0H_S, M32C_OPERAND_DST32_2_S_BASIC_QI
|
||||
, M32C_OPERAND_DST32_2_S_BASIC_HI, M32C_OPERAND_DST32_2_S_8_QI, M32C_OPERAND_DST32_2_S_16_QI, M32C_OPERAND_DST32_2_S_8_HI
|
||||
, M32C_OPERAND_DST32_2_S_16_HI, M32C_OPERAND_DST32_2_S_8_SI, M32C_OPERAND_DST32_2_S_16_SI, M32C_OPERAND_DST32_AN_S
|
||||
, M32C_OPERAND_BIT16_11_S, M32C_OPERAND_RN16_PUSH_S_ANYOF, M32C_OPERAND_AN16_PUSH_S_ANYOF, M32C_OPERAND_MAX
|
||||
, M32C_OPERAND_DSP_48_S16, M32C_OPERAND_DSP_48_U24, M32C_OPERAND_IMM_8_S4, M32C_OPERAND_IMM_8_S4N
|
||||
, M32C_OPERAND_IMM_SH_8_S4, M32C_OPERAND_IMM_8_QI, M32C_OPERAND_IMM_8_HI, M32C_OPERAND_IMM_12_S4
|
||||
, M32C_OPERAND_IMM_12_S4N, M32C_OPERAND_IMM_SH_12_S4, M32C_OPERAND_IMM_13_U3, M32C_OPERAND_IMM_20_S4
|
||||
, M32C_OPERAND_IMM_SH_20_S4, M32C_OPERAND_IMM_16_QI, M32C_OPERAND_IMM_16_HI, M32C_OPERAND_IMM_16_SI
|
||||
, M32C_OPERAND_IMM_24_QI, M32C_OPERAND_IMM_24_HI, M32C_OPERAND_IMM_24_SI, M32C_OPERAND_IMM_32_QI
|
||||
, M32C_OPERAND_IMM_32_SI, M32C_OPERAND_IMM_32_HI, M32C_OPERAND_IMM_40_QI, M32C_OPERAND_IMM_40_HI
|
||||
, M32C_OPERAND_IMM_40_SI, M32C_OPERAND_IMM_48_QI, M32C_OPERAND_IMM_48_HI, M32C_OPERAND_IMM_48_SI
|
||||
, M32C_OPERAND_IMM_56_QI, M32C_OPERAND_IMM_56_HI, M32C_OPERAND_IMM_64_HI, M32C_OPERAND_IMM1_S
|
||||
, M32C_OPERAND_IMM3_S, M32C_OPERAND_BITNO16R, M32C_OPERAND_BITNO32PREFIXED, M32C_OPERAND_BITNO32UNPREFIXED
|
||||
, M32C_OPERAND_BITBASE16_16_U8, M32C_OPERAND_BITBASE16_16_S8, M32C_OPERAND_BITBASE16_16_U16, M32C_OPERAND_BITBASE16_8_U11_S
|
||||
, M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED, M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED, M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED, M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED
|
||||
, M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED, M32C_OPERAND_BITBASE32_24_U11_PREFIXED, M32C_OPERAND_BITBASE32_24_S11_PREFIXED, M32C_OPERAND_BITBASE32_24_U19_PREFIXED
|
||||
, M32C_OPERAND_BITBASE32_24_S19_PREFIXED, M32C_OPERAND_BITBASE32_24_U27_PREFIXED, M32C_OPERAND_LAB_5_3, M32C_OPERAND_LAB32_JMP_S
|
||||
, M32C_OPERAND_LAB_8_8, M32C_OPERAND_LAB_8_16, M32C_OPERAND_LAB_8_24, M32C_OPERAND_LAB_16_8
|
||||
, M32C_OPERAND_LAB_24_8, M32C_OPERAND_LAB_32_8, M32C_OPERAND_LAB_40_8, M32C_OPERAND_SBIT
|
||||
, M32C_OPERAND_OBIT, M32C_OPERAND_ZBIT, M32C_OPERAND_CBIT, M32C_OPERAND_UBIT
|
||||
, M32C_OPERAND_IBIT, M32C_OPERAND_BBIT, M32C_OPERAND_DBIT, M32C_OPERAND_COND16_16
|
||||
, M32C_OPERAND_COND16_24, M32C_OPERAND_COND16_32, M32C_OPERAND_COND32_16, M32C_OPERAND_COND32_24
|
||||
, M32C_OPERAND_COND32_32, M32C_OPERAND_COND32_40, M32C_OPERAND_COND16C, M32C_OPERAND_COND16J
|
||||
, M32C_OPERAND_COND16J5, M32C_OPERAND_COND32, M32C_OPERAND_COND32J, M32C_OPERAND_SCCOND32
|
||||
, M32C_OPERAND_FLAGS16, M32C_OPERAND_FLAGS32, M32C_OPERAND_CR16, M32C_OPERAND_CR1_UNPREFIXED_32
|
||||
, M32C_OPERAND_CR1_PREFIXED_32, M32C_OPERAND_CR2_32, M32C_OPERAND_CR3_UNPREFIXED_32, M32C_OPERAND_CR3_PREFIXED_32
|
||||
, M32C_OPERAND_Z, M32C_OPERAND_S, M32C_OPERAND_Q, M32C_OPERAND_G
|
||||
, M32C_OPERAND_X, M32C_OPERAND_SIZE, M32C_OPERAND_BITINDEX, M32C_OPERAND_SRCINDEX
|
||||
, M32C_OPERAND_DSTINDEX, M32C_OPERAND_NOREMAINDER, M32C_OPERAND_SRC16_RN_DIRECT_QI, M32C_OPERAND_SRC16_RN_DIRECT_HI
|
||||
, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_HI
|
||||
, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_AN_DIRECT_QI, M32C_OPERAND_SRC16_AN_DIRECT_HI
|
||||
, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_QI
|
||||
, M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_HI, M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_AN_INDIRECT_QI, M32C_OPERAND_SRC16_AN_INDIRECT_HI
|
||||
, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_QI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_SI, M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_QI
|
||||
, M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_HI, M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_16_8_SB_RELATIVE_QI, M32C_OPERAND_SRC16_16_16_SB_RELATIVE_QI
|
||||
, M32C_OPERAND_SRC16_16_8_FB_RELATIVE_QI, M32C_OPERAND_SRC16_16_8_AN_RELATIVE_QI, M32C_OPERAND_SRC16_16_16_AN_RELATIVE_QI, M32C_OPERAND_SRC16_16_8_SB_RELATIVE_HI
|
||||
, M32C_OPERAND_SRC16_16_16_SB_RELATIVE_HI, M32C_OPERAND_SRC16_16_8_FB_RELATIVE_HI, M32C_OPERAND_SRC16_16_8_AN_RELATIVE_HI, M32C_OPERAND_SRC16_16_16_AN_RELATIVE_HI
|
||||
, M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_QI
|
||||
, M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_QI
|
||||
, M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_HI
|
||||
, M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_SI
|
||||
, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_SI
|
||||
, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC16_16_16_ABSOLUTE_QI, M32C_OPERAND_SRC16_16_16_ABSOLUTE_HI
|
||||
, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_QI
|
||||
, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_SI
|
||||
, M32C_OPERAND_SRC16_2_S_8_SB_RELATIVE_QI, M32C_OPERAND_SRC16_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_SRC16_2_S_16_ABSOLUTE_QI, M32C_OPERAND_SRC32_2_S_8_SB_RELATIVE_QI
|
||||
, M32C_OPERAND_SRC32_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_SRC32_2_S_16_ABSOLUTE_QI, M32C_OPERAND_SRC32_2_S_8_SB_RELATIVE_HI, M32C_OPERAND_SRC32_2_S_8_FB_RELATIVE_HI
|
||||
, M32C_OPERAND_SRC32_2_S_16_ABSOLUTE_HI, M32C_OPERAND_DST16_RN_DIRECT_QI, M32C_OPERAND_DST16_RN_DIRECT_HI, M32C_OPERAND_DST16_RN_DIRECT_SI
|
||||
, M32C_OPERAND_DST16_RN_DIRECT_EXT_QI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_QI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_HI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_SI, M32C_OPERAND_DST32_RN_DIRECT_EXTUNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_RN_DIRECT_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_R3_DIRECT_UNPREFIXED_HI, M32C_OPERAND_DST16_AN_DIRECT_QI, M32C_OPERAND_DST16_AN_DIRECT_HI
|
||||
, M32C_OPERAND_DST16_AN_DIRECT_SI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_QI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_HI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_SI, M32C_OPERAND_DST16_AN_INDIRECT_QI
|
||||
, M32C_OPERAND_DST16_AN_INDIRECT_HI, M32C_OPERAND_DST16_AN_INDIRECT_SI, M32C_OPERAND_DST16_AN_INDIRECT_EXT_QI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_HI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_SI, M32C_OPERAND_DST32_AN_INDIRECT_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_EXTUNPREFIXED_HI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_QI
|
||||
, M32C_OPERAND_DST16_16_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_QI
|
||||
, M32C_OPERAND_DST16_24_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_24_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_24_8_AN_RELATIVE_QI
|
||||
, M32C_OPERAND_DST16_24_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_32_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_32_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_32_8_FB_RELATIVE_QI
|
||||
, M32C_OPERAND_DST16_32_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_32_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_40_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_40_16_SB_RELATIVE_QI
|
||||
, M32C_OPERAND_DST16_40_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_40_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_48_8_SB_RELATIVE_QI
|
||||
, M32C_OPERAND_DST16_48_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_48_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_48_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_48_16_AN_RELATIVE_QI
|
||||
, M32C_OPERAND_DST16_16_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_HI
|
||||
, M32C_OPERAND_DST16_16_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_24_8_FB_RELATIVE_HI
|
||||
, M32C_OPERAND_DST16_24_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_32_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_32_16_SB_RELATIVE_HI
|
||||
, M32C_OPERAND_DST16_32_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_32_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_40_8_SB_RELATIVE_HI
|
||||
, M32C_OPERAND_DST16_40_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_40_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_40_16_AN_RELATIVE_HI
|
||||
, M32C_OPERAND_DST16_48_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_48_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_48_8_AN_RELATIVE_HI
|
||||
, M32C_OPERAND_DST16_48_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_SI
|
||||
, M32C_OPERAND_DST16_16_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_SI
|
||||
, M32C_OPERAND_DST16_24_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_24_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_32_8_SB_RELATIVE_SI
|
||||
, M32C_OPERAND_DST16_32_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_32_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_32_16_AN_RELATIVE_SI
|
||||
, M32C_OPERAND_DST16_40_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_40_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_40_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_SI
|
||||
, M32C_OPERAND_DST16_40_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_48_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_48_8_FB_RELATIVE_SI
|
||||
, M32C_OPERAND_DST16_48_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_48_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_EXT_QI
|
||||
, M32C_OPERAND_DST16_16_8_FB_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_EXT_QI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST16_16_16_ABSOLUTE_QI, M32C_OPERAND_DST16_24_16_ABSOLUTE_QI, M32C_OPERAND_DST16_32_16_ABSOLUTE_QI
|
||||
, M32C_OPERAND_DST16_40_16_ABSOLUTE_QI, M32C_OPERAND_DST16_48_16_ABSOLUTE_QI, M32C_OPERAND_DST16_16_16_ABSOLUTE_HI, M32C_OPERAND_DST16_24_16_ABSOLUTE_HI
|
||||
, M32C_OPERAND_DST16_32_16_ABSOLUTE_HI, M32C_OPERAND_DST16_40_16_ABSOLUTE_HI, M32C_OPERAND_DST16_48_16_ABSOLUTE_HI, M32C_OPERAND_DST16_16_16_ABSOLUTE_SI
|
||||
, M32C_OPERAND_DST16_24_16_ABSOLUTE_SI, M32C_OPERAND_DST16_32_16_ABSOLUTE_SI, M32C_OPERAND_DST16_40_16_ABSOLUTE_SI, M32C_OPERAND_DST16_48_16_ABSOLUTE_SI
|
||||
, M32C_OPERAND_DST16_16_16_ABSOLUTE_EXT_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_HI, M32C_OPERAND_BIT16_RN_DIRECT, M32C_OPERAND_BIT32_RN_DIRECT_UNPREFIXED, M32C_OPERAND_BIT32_RN_DIRECT_PREFIXED
|
||||
, M32C_OPERAND_BIT16_AN_DIRECT, M32C_OPERAND_BIT32_AN_DIRECT_UNPREFIXED, M32C_OPERAND_BIT32_AN_DIRECT_PREFIXED, M32C_OPERAND_BIT16_AN_INDIRECT
|
||||
, M32C_OPERAND_BIT32_AN_INDIRECT_UNPREFIXED, M32C_OPERAND_BIT32_AN_INDIRECT_PREFIXED, M32C_OPERAND_BIT16_16_8_SB_RELATIVE, M32C_OPERAND_BIT16_16_16_SB_RELATIVE
|
||||
, M32C_OPERAND_BIT16_16_8_FB_RELATIVE, M32C_OPERAND_BIT16_16_8_AN_RELATIVE, M32C_OPERAND_BIT16_16_16_AN_RELATIVE, M32C_OPERAND_BIT32_16_11_SB_RELATIVE_UNPREFIXED
|
||||
, M32C_OPERAND_BIT32_16_19_SB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_19_FB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_11_AN_RELATIVE_UNPREFIXED
|
||||
, M32C_OPERAND_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_27_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_24_11_SB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_19_SB_RELATIVE_PREFIXED
|
||||
, M32C_OPERAND_BIT32_24_11_FB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_19_FB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_11_AN_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_19_AN_RELATIVE_PREFIXED
|
||||
, M32C_OPERAND_BIT32_24_27_AN_RELATIVE_PREFIXED, M32C_OPERAND_BIT16_11_SB_RELATIVE_S, M32C_OPERAND_RN16_PUSH_S_DERIVED, M32C_OPERAND_AN16_PUSH_S_DERIVED
|
||||
, M32C_OPERAND_BIT16_16_16_ABSOLUTE, M32C_OPERAND_BIT32_16_19_ABSOLUTE_UNPREFIXED, M32C_OPERAND_BIT32_16_27_ABSOLUTE_UNPREFIXED, M32C_OPERAND_BIT32_24_19_ABSOLUTE_PREFIXED
|
||||
, M32C_OPERAND_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_OPERAND_DST16_3_S_R0L_DIRECT_QI, M32C_OPERAND_DST16_3_S_R0H_DIRECT_QI, M32C_OPERAND_DST16_3_S_8_8_SB_RELATIVE_QI
|
||||
, M32C_OPERAND_DST16_3_S_8_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_8_16_ABSOLUTE_QI, M32C_OPERAND_DST16_3_S_16_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_16_8_FB_RELATIVE_QI
|
||||
, M32C_OPERAND_DST16_3_S_16_16_ABSOLUTE_QI, M32C_OPERAND_SRCDST16_R0L_R0H_S_DERIVED, M32C_OPERAND_DST32_2_S_R0L_DIRECT_QI, M32C_OPERAND_DST32_2_S_R0_DIRECT_HI
|
||||
, M32C_OPERAND_DST32_1_S_A0_DIRECT_HI, M32C_OPERAND_DST32_1_S_A1_DIRECT_HI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_QI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_QI
|
||||
, M32C_OPERAND_DST32_2_S_16_ABSOLUTE_QI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_HI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_HI, M32C_OPERAND_DST32_2_S_16_ABSOLUTE_HI
|
||||
, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_SI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_SI, M32C_OPERAND_DST32_2_S_16_ABSOLUTE_SI, M32C_OPERAND_SRC16_BASIC_QI
|
||||
, M32C_OPERAND_SRC16_BASIC_HI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_QI, M32C_OPERAND_SRC32_BASIC_PREFIXED_QI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_HI
|
||||
, M32C_OPERAND_SRC32_BASIC_PREFIXED_HI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_SI, M32C_OPERAND_SRC32_BASIC_PREFIXED_SI, M32C_OPERAND_SRC32_BASIC_EXTPREFIXED_QI
|
||||
, M32C_OPERAND_SRC16_16_8_QI, M32C_OPERAND_SRC16_16_16_QI, M32C_OPERAND_SRC16_16_8_HI, M32C_OPERAND_SRC16_16_16_HI
|
||||
, M32C_OPERAND_SRC32_16_8_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_UNPREFIXED_HI
|
||||
, M32C_OPERAND_SRC32_16_16_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_UNPREFIXED_SI
|
||||
, M32C_OPERAND_SRC32_16_24_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_8_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_PREFIXED_QI, M32C_OPERAND_SRC32_24_24_PREFIXED_QI
|
||||
, M32C_OPERAND_SRC32_24_8_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_PREFIXED_SI
|
||||
, M32C_OPERAND_SRC32_24_16_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_PREFIXED_SI, M32C_OPERAND_DST16_BASIC_QI, M32C_OPERAND_DST16_BASIC_HI
|
||||
, M32C_OPERAND_DST16_BASIC_SI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_QI, M32C_OPERAND_DST32_BASIC_PREFIXED_QI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_BASIC_PREFIXED_HI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_SI, M32C_OPERAND_DST32_BASIC_PREFIXED_SI, M32C_OPERAND_DST16_16_QI
|
||||
, M32C_OPERAND_DST16_16_8_QI, M32C_OPERAND_DST16_16_16_QI, M32C_OPERAND_DST16_16_HI, M32C_OPERAND_DST16_16_8_HI
|
||||
, M32C_OPERAND_DST16_16_16_HI, M32C_OPERAND_DST16_16_SI, M32C_OPERAND_DST16_16_8_SI, M32C_OPERAND_DST16_16_16_SI
|
||||
, M32C_OPERAND_DST16_16_EXT_QI, M32C_OPERAND_DST16_AN_INDIRECT_MOVA_HI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_MOVA_HI
|
||||
, M32C_OPERAND_DST16_16_8_SB_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_16_ABSOLUTE_MOVA_HI
|
||||
, M32C_OPERAND_DST16_16_MOVA_HI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI
|
||||
, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI
|
||||
, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_UNPREFIXED_MOVA_SI
|
||||
, M32C_OPERAND_DST32_16_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_16_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_16_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_UNPREFIXED_SI, M32C_OPERAND_DST32_16_24_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_16_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_UNPREFIXED_MULEX_HI, M32C_OPERAND_DST16_24_QI
|
||||
, M32C_OPERAND_DST16_24_HI, M32C_OPERAND_DST32_24_UNPREFIXED_QI, M32C_OPERAND_DST32_24_PREFIXED_QI, M32C_OPERAND_DST32_24_8_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_24_16_PREFIXED_QI, M32C_OPERAND_DST32_24_24_PREFIXED_QI, M32C_OPERAND_DST32_24_UNPREFIXED_HI, M32C_OPERAND_DST32_24_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_24_8_PREFIXED_HI, M32C_OPERAND_DST32_24_16_PREFIXED_HI, M32C_OPERAND_DST32_24_24_PREFIXED_HI, M32C_OPERAND_DST32_24_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_24_PREFIXED_SI, M32C_OPERAND_DST32_24_8_PREFIXED_SI, M32C_OPERAND_DST32_24_16_PREFIXED_SI, M32C_OPERAND_DST32_24_24_PREFIXED_SI
|
||||
, M32C_OPERAND_DST16_32_QI, M32C_OPERAND_DST16_32_HI, M32C_OPERAND_DST32_32_UNPREFIXED_QI, M32C_OPERAND_DST32_32_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_32_UNPREFIXED_HI, M32C_OPERAND_DST32_32_PREFIXED_HI, M32C_OPERAND_DST32_32_UNPREFIXED_SI, M32C_OPERAND_DST32_32_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_40_UNPREFIXED_QI, M32C_OPERAND_DST32_40_PREFIXED_QI, M32C_OPERAND_DST32_40_UNPREFIXED_HI, M32C_OPERAND_DST32_40_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_40_UNPREFIXED_SI, M32C_OPERAND_DST32_40_PREFIXED_SI, M32C_OPERAND_DST32_48_PREFIXED_QI, M32C_OPERAND_DST32_48_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_48_PREFIXED_SI, M32C_OPERAND_BIT16_16, M32C_OPERAND_BIT16_16_BASIC, M32C_OPERAND_BIT16_16_8
|
||||
, M32C_OPERAND_BIT16_16_16, M32C_OPERAND_BIT32_16_UNPREFIXED, M32C_OPERAND_BIT32_24_PREFIXED, M32C_OPERAND_BIT32_BASIC_UNPREFIXED
|
||||
, M32C_OPERAND_BIT32_16_8_UNPREFIXED, M32C_OPERAND_BIT32_16_16_UNPREFIXED, M32C_OPERAND_BIT32_16_24_UNPREFIXED, M32C_OPERAND_SRC16_2_S
|
||||
, M32C_OPERAND_SRC32_2_S_QI, M32C_OPERAND_SRC32_2_S_HI, M32C_OPERAND_DST16_3_S_8, M32C_OPERAND_DST16_3_S_16
|
||||
, M32C_OPERAND_SRCDST16_R0L_R0H_S, M32C_OPERAND_DST32_2_S_BASIC_QI, M32C_OPERAND_DST32_2_S_BASIC_HI, M32C_OPERAND_DST32_2_S_8_QI
|
||||
, M32C_OPERAND_DST32_2_S_16_QI, M32C_OPERAND_DST32_2_S_8_HI, M32C_OPERAND_DST32_2_S_16_HI, M32C_OPERAND_DST32_2_S_8_SI
|
||||
, M32C_OPERAND_DST32_2_S_16_SI, M32C_OPERAND_DST32_AN_S, M32C_OPERAND_BIT16_11_S, M32C_OPERAND_RN16_PUSH_S_ANYOF
|
||||
, M32C_OPERAND_AN16_PUSH_S_ANYOF, M32C_OPERAND_MAX
|
||||
} CGEN_OPERAND_TYPE;
|
||||
|
||||
/* Number of operands types. */
|
||||
#define MAX_OPERANDS 871
|
||||
#define MAX_OPERANDS 873
|
||||
|
||||
/* Maximum number of operands referenced by any insn. */
|
||||
#define MAX_OPERAND_INSTANCES 8
|
||||
|
||||
@ -262,6 +262,19 @@ print_push_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
print_regset (cd, dis_info, value, attrs, pc, length, PUSH);
|
||||
}
|
||||
|
||||
static void
|
||||
print_signed4n (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
void * dis_info,
|
||||
signed long value,
|
||||
unsigned int attrs ATTRIBUTE_UNUSED,
|
||||
bfd_vma pc ATTRIBUTE_UNUSED,
|
||||
int length ATTRIBUTE_UNUSED)
|
||||
{
|
||||
disassemble_info *info = dis_info;
|
||||
|
||||
(*info->fprintf_func) (info->stream, "%ld", -value);
|
||||
}
|
||||
|
||||
void m32c_cgen_print_operand
|
||||
(CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
|
||||
|
||||
@ -572,6 +585,9 @@ m32c_cgen_print_operand (CGEN_CPU_DESC cd,
|
||||
case M32C_OPERAND_IMM_12_S4 :
|
||||
print_normal (cd, info, fields->f_imm_12_s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
|
||||
break;
|
||||
case M32C_OPERAND_IMM_12_S4N :
|
||||
print_signed4n (cd, info, fields->f_imm_12_s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
|
||||
break;
|
||||
case M32C_OPERAND_IMM_13_U3 :
|
||||
print_normal (cd, info, fields->f_imm_13_u3, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
|
||||
break;
|
||||
@ -641,6 +657,9 @@ m32c_cgen_print_operand (CGEN_CPU_DESC cd,
|
||||
case M32C_OPERAND_IMM_8_S4 :
|
||||
print_normal (cd, info, fields->f_imm_8_s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
|
||||
break;
|
||||
case M32C_OPERAND_IMM_8_S4N :
|
||||
print_normal (cd, info, fields->f_imm_8_s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
|
||||
break;
|
||||
case M32C_OPERAND_IMM_SH_12_S4 :
|
||||
print_keyword (cd, info, & m32c_cgen_opval_h_shimm, fields->f_imm_12_s4, 0);
|
||||
break;
|
||||
|
||||
@ -1174,6 +1174,9 @@ m32c_cgen_insert_operand (CGEN_CPU_DESC cd,
|
||||
case M32C_OPERAND_IMM_12_S4 :
|
||||
errmsg = insert_normal (cd, fields->f_imm_12_s4, 0|(1<<CGEN_IFLD_SIGNED), 0, 12, 4, 32, total_length, buffer);
|
||||
break;
|
||||
case M32C_OPERAND_IMM_12_S4N :
|
||||
errmsg = insert_normal (cd, fields->f_imm_12_s4, 0|(1<<CGEN_IFLD_SIGNED), 0, 12, 4, 32, total_length, buffer);
|
||||
break;
|
||||
case M32C_OPERAND_IMM_13_U3 :
|
||||
errmsg = insert_normal (cd, fields->f_imm_13_u3, 0, 0, 13, 3, 32, total_length, buffer);
|
||||
break;
|
||||
@ -1361,6 +1364,9 @@ m32c_cgen_insert_operand (CGEN_CPU_DESC cd,
|
||||
case M32C_OPERAND_IMM_8_S4 :
|
||||
errmsg = insert_normal (cd, fields->f_imm_8_s4, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 4, 32, total_length, buffer);
|
||||
break;
|
||||
case M32C_OPERAND_IMM_8_S4N :
|
||||
errmsg = insert_normal (cd, fields->f_imm_8_s4, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 4, 32, total_length, buffer);
|
||||
break;
|
||||
case M32C_OPERAND_IMM_SH_12_S4 :
|
||||
errmsg = insert_normal (cd, fields->f_imm_12_s4, 0|(1<<CGEN_IFLD_SIGNED), 0, 12, 4, 32, total_length, buffer);
|
||||
break;
|
||||
@ -2298,6 +2304,9 @@ m32c_cgen_extract_operand (CGEN_CPU_DESC cd,
|
||||
case M32C_OPERAND_IMM_12_S4 :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 12, 4, 32, total_length, pc, & fields->f_imm_12_s4);
|
||||
break;
|
||||
case M32C_OPERAND_IMM_12_S4N :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 12, 4, 32, total_length, pc, & fields->f_imm_12_s4);
|
||||
break;
|
||||
case M32C_OPERAND_IMM_13_U3 :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_imm_13_u3);
|
||||
break;
|
||||
@ -2480,6 +2489,9 @@ m32c_cgen_extract_operand (CGEN_CPU_DESC cd,
|
||||
case M32C_OPERAND_IMM_8_S4 :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 4, 32, total_length, pc, & fields->f_imm_8_s4);
|
||||
break;
|
||||
case M32C_OPERAND_IMM_8_S4N :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 4, 32, total_length, pc, & fields->f_imm_8_s4);
|
||||
break;
|
||||
case M32C_OPERAND_IMM_SH_12_S4 :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 12, 4, 32, total_length, pc, & fields->f_imm_12_s4);
|
||||
break;
|
||||
@ -3106,6 +3118,9 @@ m32c_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
case M32C_OPERAND_IMM_12_S4 :
|
||||
value = fields->f_imm_12_s4;
|
||||
break;
|
||||
case M32C_OPERAND_IMM_12_S4N :
|
||||
value = fields->f_imm_12_s4;
|
||||
break;
|
||||
case M32C_OPERAND_IMM_13_U3 :
|
||||
value = fields->f_imm_13_u3;
|
||||
break;
|
||||
@ -3175,6 +3190,9 @@ m32c_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
case M32C_OPERAND_IMM_8_S4 :
|
||||
value = fields->f_imm_8_s4;
|
||||
break;
|
||||
case M32C_OPERAND_IMM_8_S4N :
|
||||
value = fields->f_imm_8_s4;
|
||||
break;
|
||||
case M32C_OPERAND_IMM_SH_12_S4 :
|
||||
value = fields->f_imm_12_s4;
|
||||
break;
|
||||
@ -3690,6 +3708,9 @@ m32c_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
case M32C_OPERAND_IMM_12_S4 :
|
||||
value = fields->f_imm_12_s4;
|
||||
break;
|
||||
case M32C_OPERAND_IMM_12_S4N :
|
||||
value = fields->f_imm_12_s4;
|
||||
break;
|
||||
case M32C_OPERAND_IMM_13_U3 :
|
||||
value = fields->f_imm_13_u3;
|
||||
break;
|
||||
@ -3759,6 +3780,9 @@ m32c_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
case M32C_OPERAND_IMM_8_S4 :
|
||||
value = fields->f_imm_8_s4;
|
||||
break;
|
||||
case M32C_OPERAND_IMM_8_S4N :
|
||||
value = fields->f_imm_8_s4;
|
||||
break;
|
||||
case M32C_OPERAND_IMM_SH_12_S4 :
|
||||
value = fields->f_imm_12_s4;
|
||||
break;
|
||||
@ -4276,6 +4300,9 @@ m32c_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
case M32C_OPERAND_IMM_12_S4 :
|
||||
fields->f_imm_12_s4 = value;
|
||||
break;
|
||||
case M32C_OPERAND_IMM_12_S4N :
|
||||
fields->f_imm_12_s4 = value;
|
||||
break;
|
||||
case M32C_OPERAND_IMM_13_U3 :
|
||||
fields->f_imm_13_u3 = value;
|
||||
break;
|
||||
@ -4345,6 +4372,9 @@ m32c_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
case M32C_OPERAND_IMM_8_S4 :
|
||||
fields->f_imm_8_s4 = value;
|
||||
break;
|
||||
case M32C_OPERAND_IMM_8_S4N :
|
||||
fields->f_imm_8_s4 = value;
|
||||
break;
|
||||
case M32C_OPERAND_IMM_SH_12_S4 :
|
||||
fields->f_imm_12_s4 = value;
|
||||
break;
|
||||
@ -4838,6 +4868,9 @@ m32c_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
case M32C_OPERAND_IMM_12_S4 :
|
||||
fields->f_imm_12_s4 = value;
|
||||
break;
|
||||
case M32C_OPERAND_IMM_12_S4N :
|
||||
fields->f_imm_12_s4 = value;
|
||||
break;
|
||||
case M32C_OPERAND_IMM_13_U3 :
|
||||
fields->f_imm_13_u3 = value;
|
||||
break;
|
||||
@ -4907,6 +4940,9 @@ m32c_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
case M32C_OPERAND_IMM_8_S4 :
|
||||
fields->f_imm_8_s4 = value;
|
||||
break;
|
||||
case M32C_OPERAND_IMM_8_S4N :
|
||||
fields->f_imm_8_s4 = value;
|
||||
break;
|
||||
case M32C_OPERAND_IMM_SH_12_S4 :
|
||||
fields->f_imm_12_s4 = value;
|
||||
break;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
4341
opcodes/m32c-opc.h
4341
opcodes/m32c-opc.h
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user