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sim: rx: add missing break to memory write

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It doesn't seem like we want to keep executing the next block of code
after processing the request.
This commit is contained in:
Mike Frysinger 2023-12-21 01:36:40 -05:00
parent 4935610a57
commit c31d7253d2
1 changed files with 1 additions and 0 deletions
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sim/rx/mem.c
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@ -324,6 +324,7 @@ mem_put_byte (unsigned int address, unsigned char value)
halt_pipeline_stats ();
else
reset_pipeline_stats ();
break;
}
#endif