mirror/binutils-gdb
2
0
Fork 0
mirror of https://sourceware.org/git/binutils-gdb.git synced 2025-04-24 14:53:34 +08:00
Code Issues Packages Projects Releases Wiki Activity

cpu,opcodes,gas: fix neg and neg32 instructions in BPF

Browse Source 
This patch fixes the neg/neg32 BPF instructions, which have K (=0)
instead of X (=1) in their header source bit, despite operating on
registes.

cpu/ChangeLog:

2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf.cpu (define-alu-insn-un): The unary BPF instructions
	(neg and neg32) use OP_SRC_K even if they operate only in
	registers.

opcodes/ChangeLog:

2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf-opc.c: Regenerate.

gas/ChangeLog:

2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* testsuite/gas/bpf/alu.d: Update expected opcode for `neg'.
	* testsuite/gas/bpf/alu-be.d: Likewise.
	* testsuite/gas/bpf/alu32.d: Likewise for `neg32'.
	* testsuite/gas/bpf/alu32-be.d: Likewise.
This commit is contained in:
Jose E. Marchesi 2020-01-30 13:59:04 +01:00
parent aeab2b26db
commit bd434cc4d9
9 changed files with 26 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
cpu/ChangeLog
View File

@ -1,3 +1,9 @@
2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf.cpu (define-alu-insn-un): The unary BPF instructions
(neg and neg32) use OP_SRC_K even if they operate only in
registers.
2020-01-18 Nick Clifton <nickc@redhat.com>
Binutils 2.34 branch created.

2
cpu/bpf.cpu
View File

@ -373,7 +373,7 @@
((ISA (.sym ebpf x-endian)))
(.str x-basename x-suffix " $dst" x-endian)
(+ (f-imm32 0) (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian)
x-op-class OP_SRC_X x-op-code) () ()))
x-op-class OP_SRC_K x-op-code) () ()))
(define-pmacro (define-alu-insn-bin x-basename x-suffix x-op-class x-op-code x-endian)
(begin

7
gas/ChangeLog
View File

@ -1,3 +1,10 @@
2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/bpf/alu.d: Update expected opcode for `neg'.
* testsuite/gas/bpf/alu-be.d: Likewise.
* testsuite/gas/bpf/alu32.d: Likewise for `neg32'.
* testsuite/gas/bpf/alu32-be.d: Likewise.
2020-01-30 Jan Beulich <jbeulich@suse.com>
* testsuite/gas/i386/x86-64-branch-2.s,

2
gas/testsuite/gas/bpf/alu-be.d
View File

@ -56,4 +56,4 @@ Disassembly of section .text:
168: c7 30 00 00 ff ff fd 66 arsh %r3,-666
170: c7 40 00 00 7e ad be ef arsh %r4,0x7eadbeef
178: cf 56 00 00 00 00 00 00 arsh %r5,%r6
180: 8f 20 00 00 00 00 00 00 neg %r2
180: 87 20 00 00 00 00 00 00 neg %r2

2
gas/testsuite/gas/bpf/alu.d
View File

@ -55,4 +55,4 @@ Disassembly of section .text:
168: c7 03 00 00 66 fd ff ff arsh %r3,-666
170: c7 04 00 00 ef be ad 7e arsh %r4,0x7eadbeef
178: cf 65 00 00 00 00 00 00 arsh %r5,%r6
180: 8f 02 00 00 00 00 00 00 neg %r2
180: 87 02 00 00 00 00 00 00 neg %r2

2
gas/testsuite/gas/bpf/alu32-be.d
View File

@ -56,7 +56,7 @@ Disassembly of section .text:
168: c4 30 00 00 ff ff fd 66 arsh32 %r3,-666
170: c4 40 00 00 7e ad be ef arsh32 %r4,0x7eadbeef
178: cc 56 00 00 00 00 00 00 arsh32 %r5,%r6
180: 8c 20 00 00 00 00 00 00 neg32 %r2
180: 84 20 00 00 00 00 00 00 neg32 %r2
188: d4 90 00 00 00 00 00 10 endle %r9,16
190: d4 80 00 00 00 00 00 20 endle %r8,32
198: d4 70 00 00 00 00 00 40 endle %r7,64

2
gas/testsuite/gas/bpf/alu32.d
View File

@ -55,7 +55,7 @@ Disassembly of section .text:
168: c4 03 00 00 66 fd ff ff arsh32 %r3,-666
170: c4 04 00 00 ef be ad 7e arsh32 %r4,0x7eadbeef
178: cc 65 00 00 00 00 00 00 arsh32 %r5,%r6
180: 8c 02 00 00 00 00 00 00 neg32 %r2
180: 84 02 00 00 00 00 00 00 neg32 %r2
188: d4 09 00 00 10 00 00 00 endle %r9,16
190: d4 08 00 00 20 00 00 00 endle %r8,32
198: d4 07 00 00 40 00 00 00 endle %r7,64

4
opcodes/ChangeLog
View File

@ -1,3 +1,7 @@
2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-opc.c: Regenerate.
2020-01-30 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.

8
opcodes/bpf-opc.c
View File

@ -452,13 +452,13 @@ static const CGEN_OPCODE bpf_cgen_insn_opcode_table[MAX_INSNS] =
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSTLE), 0 } },
& ifmt_negle, { 0x8f }
& ifmt_negle, { 0x87 }
},
/* neg32 $dstle */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSTLE), 0 } },
& ifmt_negle, { 0x8c }
& ifmt_negle, { 0x84 }
},
/* add $dstbe,$imm32 */
{
@ -752,13 +752,13 @@ static const CGEN_OPCODE bpf_cgen_insn_opcode_table[MAX_INSNS] =
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSTBE), 0 } },
& ifmt_negbe, { 0x8f }
& ifmt_negbe, { 0x87 }
},
/* neg32 $dstbe */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DSTBE), 0 } },
& ifmt_negbe, { 0x8c }
& ifmt_negbe, { 0x84 }
},
/* endle $dstle,$endsize */
{