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ubsan: epiphany: left shift of negative value

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Two places in epiphany_cgen_extract_operand, "value" is a long.
        value = ((((value) << (1))) + (pc));

cpu/
	* epiphany.cpu (f-simm8, f-simm24): Use multiply rather than
	shift left to avoid UB on left shift of negative values.
opcodes/
	* epiphany-ibld.c: Regenerate.
This commit is contained in:
Alan Modra 2019-12-10 18:06:09 +10:30
parent 8ff23dba80
commit b8e61daa1a
4 changed files with 13 additions and 4 deletions
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5
cpu/ChangeLog
View File

@ -1,3 +1,8 @@
2019-12-11 Alan Modra <amodra@gmail.com>
* epiphany.cpu (f-simm8, f-simm24): Use multiply rather than
shift left to avoid UB on left shift of negative values.
2019-11-20 Jose E. Marchesi <jose.marchesi@oracle.com> 2019-11-20 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf.cpu: Fix comment describing the 128-bit instruction format. * bpf.cpu: Fix comment describing the 128-bit instruction format.

4
cpu/epiphany.cpu
View File

@ -149,11 +149,11 @@
(df f-simm8 "branch displacement" (PCREL-ADDR RELOC) 15 8 INT (df f-simm8 "branch displacement" (PCREL-ADDR RELOC) 15 8 INT
((value pc) (sra SI (sub SI value pc) 1)) ((value pc) (sra SI (sub SI value pc) 1))
((value pc) (add SI (sll SI value 1) pc))) ((value pc) (add SI (mul SI value 2) pc)))
(df f-simm24 "branch displacement" (PCREL-ADDR RELOC) 31 24 INT (df f-simm24 "branch displacement" (PCREL-ADDR RELOC) 31 24 INT
((value pc) (sra SI (sub SI value pc) 1)) ((value pc) (sra SI (sub SI value pc) 1))
((value pc) (add SI (sll SI value 1) pc))) ((value pc) (add SI (mul SI value 2) pc)))
(df f-sdisp3 "signed immediate 3 bit" () 9 3 INT #f #f) (df f-sdisp3 "signed immediate 3 bit" () 9 3 INT #f #f)

4
opcodes/ChangeLog
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@ -1,3 +1,7 @@
2019-12-11 Alan Modra <amodra@gmail.com>
* epiphany-ibld.c: Regenerate.
2019-12-10 Alan Modra <amodra@gmail.com> 2019-12-10 Alan Modra <amodra@gmail.com>
PR 24960 PR 24960

4
opcodes/epiphany-ibld.c
View File

@ -1100,7 +1100,7 @@ epiphany_cgen_extract_operand (CGEN_CPU_DESC cd,
{ {
long value; long value;
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 31, 24, 32, total_length, pc, & value); length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 31, 24, 32, total_length, pc, & value);
value = ((((value) << (1))) + (pc)); value = ((((value) * (2))) + (pc));
fields->f_simm24 = value; fields->f_simm24 = value;
} }
break; break;
@ -1111,7 +1111,7 @@ epiphany_cgen_extract_operand (CGEN_CPU_DESC cd,
{ {
long value; long value;
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 15, 8, 32, total_length, pc, & value); length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 15, 8, 32, total_length, pc, & value);
value = ((((value) << (1))) + (pc)); value = ((((value) * (2))) + (pc));
fields->f_simm8 = value; fields->f_simm8 = value;
} }
break; break;