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The patch fixed invalid compilation of instruction LD IY,(HL) and disassemble of this and LD (HL),IX instruction. Also it update testsuit.
PR 25627 opcodes * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX instructions. gas * config/tc-z80.c (emit_ld_rr_m): Fix invalid compilation of instruction LD IY,(HL). * testsuite/gas/z80/ez80_adl_all.d: Update expected disassembly. * testsuite/gas/z80/ez80_adl_all.s: Add tests of the instruction. * testsuite/gas/z80/ez80_z80_all.d: Update expected disassembly. * testsuite/gas/z80/ez80_z80_all.s: Add tests of the instruction.
This commit is contained in:
Sergey Belyashov
Nick Clifton
parent
7b973adce2
commit
b8ba138563
@ -1,3 +1,13 @@
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2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
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PR 25627
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* config/tc-z80.c (emit_ld_rr_m): Fix invalid compilation of
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instruction LD IY,(HL).
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* testsuite/gas/z80/ez80_adl_all.d: Update expected disassembly.
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* testsuite/gas/z80/ez80_adl_all.s: Add tests of the instruction.
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* testsuite/gas/z80/ez80_z80_all.d: Update expected disassembly.
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* testsuite/gas/z80/ez80_z80_all.s: Add tests of the instruction.
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2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/25622
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@ -2601,8 +2601,8 @@ emit_ld_rr_m (expressionS *dst, expressionS *src)
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case REG_BC: opcode = 0x07; break;
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case REG_DE: opcode = 0x17; break;
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case REG_HL: opcode = 0x27; break;
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case REG_IX: opcode = (!prefix || prefix == 0xDD) ? 0x37 : 0x31; break;
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case REG_IY: opcode = prefix ? ((prefix == 0xDD) ? 0x31 : 0x37) : 0x36; break;
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case REG_IX: opcode = (prefix == 0xED || prefix == 0xDD) ? 0x37 : 0x31; break;
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case REG_IY: opcode = (prefix == 0xED || prefix == 0xDD) ? 0x31 : 0x37; break;
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default:
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ill_op ();
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}
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@ -959,3 +959,13 @@ Disassembly of section .text:
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\s+7c1:\s+ab\s+xor a,e
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\s+7c2:\s+ac\s+xor a,h
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\s+7c3:\s+ad\s+xor a,l
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\s+7c4:\s+ed 07\s+ld bc,\(hl\)
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\s+7c6:\s+ed 17\s+ld de,\(hl\)
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\s+7c8:\s+ed 27\s+ld hl,\(hl\)
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\s+7ca:\s+ed 37\s+ld ix,\(hl\)
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\s+7cc:\s+ed 31\s+ld iy,\(hl\)
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\s+7ce:\s+ed 0f\s+ld \(hl\),bc
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\s+7d0:\s+ed 1f\s+ld \(hl\),de
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\s+7d2:\s+ed 2f\s+ld \(hl\),hl
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\s+7d4:\s+ed 3f\s+ld \(hl\),ix
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\s+7d6:\s+ed 3e\s+ld \(hl\),iy
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@ -480,7 +480,7 @@
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ex (sp),hl
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ex (sp),ix
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ex (sp),iy
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ex af,af'
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ex af,af' ;'
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ex de,hl
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exx
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halt
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@ -998,3 +998,13 @@
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xor e
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xor h
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xor l
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ld bc,(hl)
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ld de,(hl)
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ld hl,(hl)
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ld ix,(hl)
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ld iy,(hl)
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ld (hl),bc
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ld (hl),de
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ld (hl),hl
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ld (hl),ix
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ld (hl),iy
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@ -955,3 +955,13 @@ Disassembly of section .text:
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\s+793:\s+ab\s+xor a,e
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\s+794:\s+ac\s+xor a,h
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\s+795:\s+ad\s+xor a,l
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\s+796:\s+ed 07\s+ld bc,\(hl\)
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\s+798:\s+ed 17\s+ld de,\(hl\)
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\s+79a:\s+ed 27\s+ld hl,\(hl\)
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\s+79c:\s+ed 37\s+ld ix,\(hl\)
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\s+79e:\s+ed 31\s+ld iy,\(hl\)
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\s+7a0:\s+ed 0f\s+ld \(hl\),bc
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\s+7a2:\s+ed 1f\s+ld \(hl\),de
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\s+7a4:\s+ed 2f\s+ld \(hl\),hl
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\s+7a6:\s+ed 3f\s+ld \(hl\),ix
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\s+7a8:\s+ed 3e\s+ld \(hl\),iy
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@ -474,7 +474,7 @@
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ex (sp),hl
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ex (sp),ix
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ex (sp),iy
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ex af,af'
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ex af,af' ;'
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ex de,hl
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exx
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halt
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@ -992,3 +992,13 @@
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xor e
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xor h
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xor l
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ld bc,(hl)
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ld de,(hl)
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ld hl,(hl)
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ld ix,(hl)
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ld iy,(hl)
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ld (hl),bc
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ld (hl),de
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ld (hl),hl
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ld (hl),ix
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ld (hl),iy
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@ -1,3 +1,9 @@
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2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
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PR 25627
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* z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
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instructions.
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2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/25622
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@ -436,6 +436,7 @@ struct tab_elt opc_ed[] =
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{
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{ 0x30, 0xFF, prt, "mul d,e", INSS_Z80N },
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{ 0x31, 0xFF, prt, "add hl,a", INSS_Z80N },
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{ 0x31, 0xFF, prt, "ld iy,(hl)", INSS_EZ80 },
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{ 0x30, 0xFE, dump, "xx", INSS_ALL }, /* do not move this line */
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{ 0x00, 0xC7, prt_r_n, "in0 %s,(0x%%02x)", INSS_Z180|INSS_EZ80 },
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{ 0x01, 0xC7, prt_r_n, "out0 (0x%%02x),%s", INSS_Z180|INSS_EZ80 },
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@ -446,6 +447,7 @@ struct tab_elt opc_ed[] =
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{ 0x04, 0xC7, prt_r, "tst %s", INSS_Z180},
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{ 0x04, 0xC7, prt_r, "tst a,%s", INSS_EZ80 },
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{ 0x07, 0xFF, prt, "ld bc,(hl)", INSS_EZ80 },
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{ 0x3F, 0xFF, prt, "ld (hl),ix", INSS_EZ80 },
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{ 0x0F, 0xCF, prt_rr, "ld (hl),", INSS_EZ80 },
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{ 0x17, 0xFF, prt, "ld de,(hl)", INSS_EZ80 },
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{ 0x23, 0xFF, prt, "swapnib", INSS_Z80N },
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@ -462,10 +464,8 @@ struct tab_elt opc_ed[] =
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{ 0x34, 0xFF, prt_nn, "add hl,0x%04x", INSS_Z80N },
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{ 0x35, 0xFF, prt_nn, "add de,0x%04x", INSS_Z80N },
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{ 0x36, 0xFF, prt_nn, "add bc,0x%04x", INSS_Z80N },
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{ 0x36, 0xFF, prt, "ld iy,(hl)", INSS_EZ80 },
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{ 0x37, 0xFF, prt, "ld ix,(hl)", INSS_EZ80 },
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{ 0x3E, 0xFF, prt, "ld (hl),iy", INSS_EZ80 },
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{ 0x3F, 0xFF, prt, "ld (hl),ix", INSS_EZ80 },
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{ 0x70, 0xFF, prt, "in f,(c)", INSS_Z80 | INSS_R800 | INSS_Z80N },
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{ 0x70, 0xFF, dump, "xx", INSS_ALL },
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{ 0x40, 0xC7, prt_r, "in %s,(bc)", INSS_EZ80 },
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