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* config/tc-arm.c (parse_vfp_reg_list): Improve register bounds
checking. (do_neon_mov): Enable several VMOV variants for VFP. Add suitable architecture version checks. (insns): Allow overlapping instructions to be used in VFP mode.
This commit is contained in:
Julian Brown
parent
55a9ea5780
commit
b7fc276944
@ -1,3 +1,11 @@
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2006-05-05 Julian Brown <julian@codesourcery.com>
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* config/tc-arm.c (parse_vfp_reg_list): Improve register bounds
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checking.
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(do_neon_mov): Enable several VMOV variants for VFP. Add suitable
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architecture version checks.
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(insns): Allow overlapping instructions to be used in VFP mode.
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2006-05-05 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/2598
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@ -1553,6 +1553,15 @@ parse_vfp_reg_list (char **str, unsigned int *pbase, enum reg_list_els etype)
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case REGLIST_VFP_D:
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regtype = REG_TYPE_VFD;
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break;
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case REGLIST_NEON_D:
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regtype = REG_TYPE_NDQ;
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break;
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}
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if (etype != REGLIST_VFP_S)
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{
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/* VFPv3 allows 32 D registers. */
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if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3))
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{
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@ -1566,12 +1575,6 @@ parse_vfp_reg_list (char **str, unsigned int *pbase, enum reg_list_els etype)
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}
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else
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max_regs = 16;
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break;
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case REGLIST_NEON_D:
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regtype = REG_TYPE_NDQ;
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max_regs = 32;
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break;
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}
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base_reg = max_regs;
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@ -1588,6 +1591,12 @@ parse_vfp_reg_list (char **str, unsigned int *pbase, enum reg_list_els etype)
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return FAIL;
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}
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if (new_base >= max_regs)
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{
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first_error (_("register out of range in list"));
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return FAIL;
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}
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/* Note: a value of 2 * n is returned for the register Q<n>. */
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if (regtype == REG_TYPE_NQ)
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{
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@ -1626,6 +1635,12 @@ parse_vfp_reg_list (char **str, unsigned int *pbase, enum reg_list_els etype)
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return FAIL;
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}
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if (high_range >= max_regs)
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{
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first_error (_("register out of range in list"));
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return FAIL;
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}
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if (regtype == REG_TYPE_NQ)
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high_range = high_range + 1;
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@ -11303,6 +11318,9 @@ do_neon_dup (void)
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All the encoded bits are hardcoded by this function.
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Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
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Cases 5, 7 may be used with VFPv2 and above.
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FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
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can specify a type where it doesn't make sense to, and is ignored).
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*/
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@ -11313,6 +11331,7 @@ do_neon_mov (void)
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int nargs = inst.operands[0].present + inst.operands[1].present
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+ inst.operands[2].present;
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unsigned save_cond = thumb_mode ? 0xe0000000 : inst.instruction & 0xf0000000;
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const char *vfp_vers = "selected FPU does not support instruction";
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switch (nargs)
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{
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@ -11328,6 +11347,10 @@ do_neon_mov (void)
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unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
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unsigned abcdebits = 0;
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constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
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_(vfp_vers));
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constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
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&& et.size != 32, _(vfp_vers));
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constraint (et.type == NT_invtype, _("bad type for scalar"));
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constraint (x >= 64 / et.size, _("scalar index out of range"));
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@ -11361,6 +11384,10 @@ do_neon_mov (void)
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unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
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unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
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constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
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_(vfp_vers));
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constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
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&& et.size != 32, _(vfp_vers));
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constraint (et.type == NT_invtype, _("bad type for scalar"));
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constraint (x >= 64 / et.size, _("scalar index out of range"));
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@ -11411,6 +11438,9 @@ do_neon_mov (void)
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case 3:
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/* Cases 5, 7. */
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constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
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_(vfp_vers));
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if (inst.operands[0].regisimm)
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{
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/* Case 5. */
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@ -14155,7 +14185,16 @@ static const struct asm_opcode insns[] =
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nUF(vcvtq, vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
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/* One register and an immediate value. All encoding special-cased! */
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#undef THUMB_VARIANT
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#define THUMB_VARIANT &fpu_vfp_ext_v1
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#undef ARM_VARIANT
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#define ARM_VARIANT &fpu_vfp_ext_v1
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NCE(vmov, 0, 1, (VMOV), neon_mov),
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#undef THUMB_VARIANT
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#define THUMB_VARIANT &fpu_neon_ext_v1
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#undef ARM_VARIANT
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#define ARM_VARIANT &fpu_neon_ext_v1
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NCE(vmovq, 0, 1, (VMOV), neon_mov),
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nUF(vmvn, vmvn, 2, (RNDQ, RNDQ_IMVNb), neon_mvn),
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nUF(vmvnq, vmvn, 2, (RNQ, RNDQ_IMVNb), neon_mvn),
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@ -14250,9 +14289,9 @@ static const struct asm_opcode insns[] =
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NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
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#undef THUMB_VARIANT
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#define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext
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#define THUMB_VARIANT &fpu_vfp_ext_v1xd
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#undef ARM_VARIANT
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#define ARM_VARIANT &fpu_vfp_v3_or_neon_ext
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#define ARM_VARIANT &fpu_vfp_ext_v1xd
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/* Load/store instructions. Available in Neon or VFPv3. */
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NCE(vldm, c900b00, 2, (RRw, NRDLST), neon_ldm_stm),
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@ -14264,6 +14303,11 @@ static const struct asm_opcode insns[] =
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NCE(vldr, d100b00, 2, (RND, ADDR), neon_ldr_str),
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NCE(vstr, d000b00, 2, (RND, ADDR), neon_ldr_str),
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#undef THUMB_VARIANT
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#define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext
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#undef ARM_VARIANT
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#define ARM_VARIANT &fpu_vfp_v3_or_neon_ext
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/* Neon element/structure load/store. */
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nUF(vld1, vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
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nUF(vst1, vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
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