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* mn10300_sim.h (struct _state): Put all registers into a single
array to make gdb implementation easier.
(REG_*): Add definitions for all registers in the state array.
(SEXT32, SEXT40, SEXT44, SEXT60): Remove unused macros.
* simops.c: Related changes.
This commit is contained in:
Jeff Law
parent
a2bfe134c1
commit
b774c0e4b1
@ -1,3 +1,11 @@
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Tue Dec 31 16:20:41 1996 Jeffrey A Law (law@cygnus.com)
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* mn10300_sim.h (struct _state): Put all registers into a single
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array to make gdb implementation easier.
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(REG_*): Add definitions for all registers in the state array.
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(SEXT32, SEXT40, SEXT44, SEXT60): Remove unused macros.
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* simops.c: Related changes.
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Wed Dec 18 10:10:45 1996 Jeffrey A Law (law@cygnus.com)
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* interp.c (sim_resume): Handle 0xff as a single byte insn.
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@ -51,6 +51,7 @@ struct simops
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long mask;
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void (*func)();
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int length;
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int format;
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int numops;
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int operands[16];
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};
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@ -59,9 +60,8 @@ struct simops
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struct _state
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{
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reg_t regs[12]; /* registers, d0-d3, a0-a3, sp, mdr, lar, lir */
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reg_t sregs[8]; /* system registers, including psw */
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reg_t pc;
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reg_t regs[12]; /* registers, d0-d3, a0-a3, sp, pc, mdr, psw,
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lir, lar */
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uint8 *mem; /* main memory */
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int exception;
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} State;
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@ -69,9 +69,9 @@ struct _state
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extern uint32 OP[4];
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extern struct simops Simops[];
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#define PC (State.pc)
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#define PC (State.regs[9])
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#define PSW (State.sregs[0])
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#define PSW (State.regs[11])
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#define PSW_V 0x1
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#define PSW_C 0x2
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#define PSW_N 0x4
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@ -80,9 +80,11 @@ extern struct simops Simops[];
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#define REG_D0 0
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#define REG_A0 4
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#define REG_SP 8
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#define REG_MDR 9
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#define REG_LAR 10
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#define REG_LIR 11
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#define REG_PC 9
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#define REG_MDR 10
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#define REG_PSW 11
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#define REG_LIR 12
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#define REG_LAR 13
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#define SEXT3(x) ((((x)&0x7)^(~0x3))+0x4)
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@ -104,18 +106,6 @@ extern struct simops Simops[];
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/* sign-extend a 22-bit number */
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#define SEXT22(x) ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
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/* sign-extend a 32-bit number */
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#define SEXT32(x) ((((x)&0xffffffffLL)^(~0x7fffffffLL))+0x80000000LL)
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/* sign extend a 40 bit number */
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#define SEXT40(x) ((((x)&0xffffffffffLL)^(~0x7fffffffffLL))+0x8000000000LL)
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/* sign extend a 44 bit number */
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#define SEXT44(x) ((((x)&0xfffffffffffLL)^(~0x7ffffffffffLL))+0x80000000000LL)
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/* sign extend a 60 bit number */
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#define SEXT60(x) ((((x)&0xfffffffffffffffLL)^(~0x7ffffffffffffffLL))+0x800000000000000LL)
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#define MAX32 0x7fffffffLL
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#define MIN32 0xff80000000LL
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#define MASK32 0xffffffffLL
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@ -2253,7 +2253,7 @@ void OP_C800 (insn, extension)
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/* The dispatching code will add 2 after we return, so
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we subtract two here to make things right. */
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if (PSW & PSW_Z)
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State.pc += SEXT8 (insn & 0xff) - 2;
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State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
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}
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/* bne label:8 */
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@ -2263,7 +2263,7 @@ void OP_C900 (insn, extension)
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/* The dispatching code will add 2 after we return, so
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we subtract two here to make things right. */
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if (!(PSW & PSW_Z))
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State.pc += SEXT8 (insn & 0xff) - 2;
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State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
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}
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/* bgt label:8 */
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@ -2274,7 +2274,7 @@ void OP_C100 (insn, extension)
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we subtract two here to make things right. */
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if (!((PSW & PSW_Z)
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|| (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
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State.pc += SEXT8 (insn & 0xff) - 2;
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State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
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}
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/* bge label:8 */
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@ -2284,7 +2284,7 @@ void OP_C200 (insn, extension)
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/* The dispatching code will add 2 after we return, so
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we subtract two here to make things right. */
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if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
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State.pc += SEXT8 (insn & 0xff) - 2;
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State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
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}
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/* ble label:8 */
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@ -2295,7 +2295,7 @@ void OP_C300 (insn, extension)
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we subtract two here to make things right. */
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if ((PSW & PSW_Z)
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|| (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
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State.pc += SEXT8 (insn & 0xff) - 2;
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State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
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}
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/* blt label:8 */
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@ -2305,7 +2305,7 @@ void OP_C000 (insn, extension)
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/* The dispatching code will add 2 after we return, so
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we subtract two here to make things right. */
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if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
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State.pc += SEXT8 (insn & 0xff) - 2;
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State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
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}
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/* bhi label:8 */
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@ -2315,7 +2315,7 @@ void OP_C500 (insn, extension)
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/* The dispatching code will add 2 after we return, so
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we subtract two here to make things right. */
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if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
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State.pc += SEXT8 (insn & 0xff) - 2;
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State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
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}
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/* bcc label:8 */
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@ -2325,7 +2325,7 @@ void OP_C600 (insn, extension)
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/* The dispatching code will add 2 after we return, so
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we subtract two here to make things right. */
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if (!(PSW & PSW_C))
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State.pc += SEXT8 (insn & 0xff) - 2;
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State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
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}
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/* bls label:8 */
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@ -2335,7 +2335,7 @@ void OP_C700 (insn, extension)
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/* The dispatching code will add 2 after we return, so
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we subtract two here to make things right. */
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if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
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State.pc += SEXT8 (insn & 0xff) - 2;
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State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
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}
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/* bcs label:8 */
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@ -2345,7 +2345,7 @@ void OP_C400 (insn, extension)
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/* The dispatching code will add 2 after we return, so
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we subtract two here to make things right. */
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if (PSW & PSW_C)
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State.pc += SEXT8 (insn & 0xff) - 2;
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State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
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}
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/* bvc label:8 */
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@ -2355,7 +2355,7 @@ void OP_F8E800 (insn, extension)
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/* The dispatching code will add 3 after we return, so
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we subtract two here to make things right. */
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if (!(PSW & PSW_V))
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State.pc += SEXT8 (insn & 0xff) - 3;
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State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3;
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}
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/* bvs label:8 */
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@ -2365,7 +2365,7 @@ void OP_F8E900 (insn, extension)
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/* The dispatching code will add 3 after we return, so
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we subtract two here to make things right. */
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if (PSW & PSW_V)
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State.pc += SEXT8 (insn & 0xff) - 3;
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State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3;
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}
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/* bnc label:8 */
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@ -2375,7 +2375,7 @@ void OP_F8EA00 (insn, extension)
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/* The dispatching code will add 3 after we return, so
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we subtract two here to make things right. */
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if (!(PSW & PSW_N))
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State.pc += SEXT8 (insn & 0xff) - 3;
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State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3;
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}
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/* bns label:8 */
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@ -2385,7 +2385,7 @@ void OP_F8EB00 (insn, extension)
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/* The dispatching code will add 3 after we return, so
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we subtract two here to make things right. */
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if (PSW & PSW_N)
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State.pc += SEXT8 (insn & 0xff) - 3;
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State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3;
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}
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/* bra label:8 */
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@ -2394,7 +2394,7 @@ void OP_CA00 (insn, extension)
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{
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/* The dispatching code will add 2 after we return, so
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we subtract two here to make things right. */
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State.pc += SEXT8 (insn & 0xff) - 2;
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State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
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}
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/* leq */
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@ -2485,21 +2485,21 @@ void OP_DB (insn, extension)
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void OP_F0F4 (insn, extension)
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unsigned long insn, extension;
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{
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State.pc = State.regs[REG_A0 + REG0 (insn)] - 2;
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State.regs[REG_PC] = State.regs[REG_A0 + REG0 (insn)] - 2;
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}
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/* jmp label:16 */
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void OP_CC0000 (insn, extension)
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unsigned long insn, extension;
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{
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State.pc += SEXT16 (insn & 0xffff) - 3;
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State.regs[REG_PC] += SEXT16 (insn & 0xffff) - 3;
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}
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/* jmp label:32 */
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void OP_DC000000 (insn, extension)
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unsigned long insn, extension;
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{
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State.pc += (((insn & 0xffffff) << 8) + extension) - 5;
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State.regs[REG_PC] += (((insn & 0xffffff) << 8) + extension) - 5;
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}
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/* call label:16,reg_list,imm8 */
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@ -2510,7 +2510,7 @@ void OP_CD000000 (insn, extension)
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unsigned long mask;
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sp = State.regs[REG_SP];
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next_pc = State.pc + 2;
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next_pc = State.regs[REG_PC] + 2;
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State.mem[sp] = next_pc & 0xff;
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State.mem[sp+1] = (next_pc & 0xff00) >> 8;
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State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
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@ -2565,7 +2565,7 @@ void OP_CD000000 (insn, extension)
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/* And make sure to update the stack pointer. */
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State.regs[REG_SP] -= extension;
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State.regs[REG_MDR] = next_pc;
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State.pc += SEXT16 ((insn & 0xffff00) >> 8) - 5;
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State.regs[REG_PC] += SEXT16 ((insn & 0xffff00) >> 8) - 5;
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}
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/* call label:32,reg_list,imm8*/
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@ -2576,7 +2576,7 @@ void OP_DD000000 (insn, extension)
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unsigned long mask;
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sp = State.regs[REG_SP];
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next_pc = State.pc + 2;
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next_pc = State.regs[REG_PC] + 2;
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State.mem[sp] = next_pc & 0xff;
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State.mem[sp+1] = (next_pc & 0xff00) >> 8;
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State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
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@ -2631,7 +2631,7 @@ void OP_DD000000 (insn, extension)
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/* And make sure to update the stack pointer. */
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State.regs[REG_SP] -= (extension & 0xff);
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State.regs[REG_MDR] = next_pc;
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State.pc += (((insn & 0xffffff) << 8) | ((extension & 0xff0000) >> 16)) - 7;
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State.regs[REG_PC] += (((insn & 0xffffff) << 8) | ((extension & 0xff0000) >> 16)) - 7;
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}
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/* calls (an) */
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@ -2641,13 +2641,13 @@ void OP_F0F0 (insn, extension)
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unsigned int next_pc, sp;
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sp = State.regs[REG_SP];
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next_pc = State.pc + 2;
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next_pc = State.regs[REG_PC] + 2;
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State.mem[sp] = next_pc & 0xff;
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State.mem[sp+1] = (next_pc & 0xff00) >> 8;
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State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
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State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
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State.regs[REG_MDR] = next_pc;
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State.pc = State.regs[REG_A0 + REG0 (insn)] - 2;
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State.regs[REG_PC] = State.regs[REG_A0 + REG0 (insn)] - 2;
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}
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/* calls label:16 */
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@ -2657,13 +2657,13 @@ void OP_FAFF0000 (insn, extension)
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unsigned int next_pc, sp;
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sp = State.regs[REG_SP];
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next_pc = State.pc + 4;
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next_pc = State.regs[REG_PC] + 4;
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State.mem[sp] = next_pc & 0xff;
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State.mem[sp+1] = (next_pc & 0xff00) >> 8;
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State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
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State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
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State.regs[REG_MDR] = next_pc;
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State.pc += SEXT16 (insn & 0xffff) - 4;
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State.regs[REG_PC] += SEXT16 (insn & 0xffff) - 4;
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}
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/* calls label:32 */
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@ -2673,13 +2673,13 @@ void OP_FCFF0000 (insn, extension)
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unsigned int next_pc, sp;
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sp = State.regs[REG_SP];
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next_pc = State.pc + 6;
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next_pc = State.regs[REG_PC] + 6;
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State.mem[sp] = next_pc & 0xff;
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State.mem[sp+1] = (next_pc & 0xff00) >> 8;
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State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
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State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
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State.regs[REG_MDR] = next_pc;
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State.pc += (((insn & 0xffff) << 16) + extension) - 6;
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State.regs[REG_PC] += (((insn & 0xffff) << 16) + extension) - 6;
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}
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/* ret reg_list, imm8 */
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@ -2741,9 +2741,9 @@ void OP_DF0000 (insn, extension)
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State.regs[REG_SP] = sp;
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/* Restore the PC value. */
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State.pc = (State.mem[sp] | (State.mem[sp+1] << 8)
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State.regs[REG_PC] = (State.mem[sp] | (State.mem[sp+1] << 8)
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| (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
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State.pc -= 3;
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State.regs[REG_PC] -= 3;
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}
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/* retf reg_list,imm8 */
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@ -2755,7 +2755,7 @@ void OP_DE0000 (insn, extension)
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sp = State.regs[REG_SP] + (insn & 0xff);
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State.regs[REG_SP] = sp;
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State.pc = State.regs[REG_MDR] - 3;
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State.regs[REG_PC] = State.regs[REG_MDR] - 3;
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sp = State.regs[REG_SP];
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@ -2815,9 +2815,9 @@ void OP_F0FC (insn, extension)
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unsigned int sp;
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sp = State.regs[REG_SP];
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State.pc = (State.mem[sp] | (State.mem[sp+1] << 8)
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State.regs[REG_PC] = (State.mem[sp] | (State.mem[sp+1] << 8)
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| (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
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State.pc -= 2;
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State.regs[REG_PC] -= 2;
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}
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/* rti */
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