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aarch64: Rename AARCH64_OPND_SME_ZT0_INDEX2_12

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Rename to AARCH64_OPND_SME_ZT0_INDEX_MUL_VL.
This commit is contained in:
Andrew Carlotti 2025-01-06 18:06:51 +00:00
parent 9758466f46
commit b5378decd2
5 changed files with 7 additions and 7 deletions

2
gas/config/tc-aarch64.c

@ -8100,7 +8100,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
info->imm.value = vectype.index;
break;
case AARCH64_OPND_SME_ZT0_INDEX2_12:
case AARCH64_OPND_SME_ZT0_INDEX_MUL_VL:
po_misc_or_fail (parse_shifter_zt0_with_bit_index
(&str, info, SHIFTED_MUL_VL));
break;

2
include/opcode/aarch64.h

@ -881,7 +881,7 @@ enum aarch64_opnd
AARCH64_OPND_SME_VLxN_13, /* VLx2 or VLx4, in bit 13. */
AARCH64_OPND_SME_ZT0, /* The fixed token zt0/ZT0 (not encoded). */
AARCH64_OPND_SME_ZT0_INDEX, /* ZT0[<imm>], bits [14:12]. */
AARCH64_OPND_SME_ZT0_INDEX2_12, /* ZT0[<imm>], bits [13:12]. */
AARCH64_OPND_SME_ZT0_INDEX_MUL_VL,/* ZT0[<imm>], bits [13:12]. */
AARCH64_OPND_SME_ZT0_LIST, /* { zt0/ZT0 } (not encoded). */
AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */
AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */

2
opcodes/aarch64-opc-2.c

@ -339,7 +339,7 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_IMMEDIATE, "SME_VLxN_13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_VL_13}, "VLx2 or VLx4"},
{AARCH64_OPND_CLASS_SYSTEM, "SME_ZT0", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "ZT0"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SME_ZT0_INDEX", OPD_F_SHIFT_BY_3 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm3_12}, "a ZT0 index"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SME_ZT0_INDEX2_12", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm3_12}, "a ZT0 index"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SME_ZT0_INDEX_MUL_VL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm3_12}, "a ZT0 index"},
{AARCH64_OPND_CLASS_SYSTEM, "SME_ZT0_LIST", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "{ ZT0 }"},
{AARCH64_OPND_CLASS_IMMEDIATE, "TME_UIMM16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16_5}, "a 16-bit unsigned immediate for TME tcancel"},
{AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate"},

4
opcodes/aarch64-opc.c

@ -3242,7 +3242,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
}
break;
case AARCH64_OPND_SME_ZT0_INDEX2_12:
case AARCH64_OPND_SME_ZT0_INDEX_MUL_VL:
if (!value_in_range_p (opnd->imm.value, 0, 3))
{
set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, 3);
@ -5051,7 +5051,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
snprintf (buf, size, "%s[%s]", style_reg (styler, "zt0"),
style_imm (styler, "%d", (int) opnd->imm.value));
break;
case AARCH64_OPND_SME_ZT0_INDEX2_12:
case AARCH64_OPND_SME_ZT0_INDEX_MUL_VL:
snprintf (buf, size, "%s[%s, %s]", style_reg (styler, "zt0"),
style_imm (styler, "%d", (int) opnd->imm.value),
style_sub_mnem (styler, "mul vl"));

4
opcodes/aarch64-tbl.h

@ -6832,7 +6832,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
/* SME2 lutv2. */
LUTv2_SME2_INSN ("luti4", 0xc08b0000, 0xffffcc23, sme_size_12_b, OP3 (SME_Zdnx4, SME_ZT0, SME_Znx2_BIT_INDEX), OP_SVE_BUU, F_STRICT | 0),
LUTv2_SME2p1_INSN ("luti4", 0xc09b0000, 0xffffcc2c, sme_size_12_b, OP3 (SME_Ztx4_STRIDED, SME_ZT0, SME_Znx2_BIT_INDEX), OP_SVE_BUU, F_STRICT | 0),
LUTv2_SME2_INSN ("movt", 0xc04f03e0, 0xffffcfe0, sme_misc, OP2 (SME_ZT0_INDEX2_12, SVE_Zt), {}, 0),
LUTv2_SME2_INSN ("movt", 0xc04f03e0, 0xffffcfe0, sme_misc, OP2 (SME_ZT0_INDEX_MUL_VL, SVE_Zt), {}, 0),
/* SME FP16 ZA-targeting addition instructions. */
SME_F16F16_F8F16_INSNC("fadd", 0xc1a41c00, 0xffff9c38, sme_misc, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_HH, F_OD (2), 0),
SME_F16F16_F8F16_INSNC("fadd", 0xc1a51c00, 0xffff9c78, sme_misc, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_HH, F_OD (4), 0),
@ -7601,7 +7601,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
Y(SYSTEM, none, "SME_ZT0", 0, F (), "ZT0") \
Y(IMMEDIATE, imm, "SME_ZT0_INDEX", OPD_F_SHIFT_BY_3, \
F (FLD_imm3_12), "a ZT0 index") \
Y(IMMEDIATE, imm, "SME_ZT0_INDEX2_12", 0, \
Y(IMMEDIATE, imm, "SME_ZT0_INDEX_MUL_VL", 0, \
F (FLD_imm3_12), "a ZT0 index") \
Y(SYSTEM, none, "SME_ZT0_LIST", 0, F (), "{ ZT0 }") \
Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD_imm16_5), \