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https://sourceware.org/git/binutils-gdb.git
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aarch64: Add the SME2 multivector LD1 and ST1 instructions
SME2 adds LD1 and ST1 variants for lists of 2 and 4 registers. The registers can be consecutive or strided. In the strided case, 2-register lists have a stride of 8, starting at register x0xxx. 4-register lists have a stride of 4, starting at register x00xx. The instructions are predicated on a predicate-as-counter register in the range pn8-pn15. Although we already had register fields with upper bounds of 7 and 15, this is the first plain register operand to have a nonzero lower bound. The patch uses the operand-specific data field to record the minimum value, rather than having separate inserters and extractors for each lower bound. This in turn required adding an extra bit to the field.
This commit is contained in:
Richard Sandiford
parent
d8773a8a5f
commit
b408ebbf52
@ -5827,6 +5827,10 @@ output_operand_error_record (const operand_error_record *record, char *str)
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else if ((detail->data[0].i & -detail->data[0].i) == detail->data[0].i)
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handler (_("expected a list of %d registers at operand %d -- `%s'"),
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get_log2 (detail->data[0].i), idx + 1, str);
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else if (detail->data[0].i == 0x14)
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handler (_("expected a list of %d or %d registers at"
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" operand %d -- `%s'"),
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2, 4, idx + 1, str);
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else
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handler (_("invalid number of registers in the list"
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" at operand %d -- `%s'"), idx + 1, str);
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@ -5836,6 +5840,10 @@ output_operand_error_record (const operand_error_record *record, char *str)
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if (detail->data[0].i == (1 << 1))
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handler (_("the register list must have a stride of %d"
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" at operand %d -- `%s'"), 1, idx + 1, str);
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else if (detail->data[0].i == 0x12 || detail->data[0].i == 0x102)
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handler (_("the register list must have a stride of %d or %d"
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" at operand %d -- `%s`"), 1,
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detail->data[0].i == 0x12 ? 4 : 8, idx + 1, str);
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else
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handler (_("invalid register stride at operand %d -- `%s'"),
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idx + 1, str);
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@ -6630,6 +6638,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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case AARCH64_OPND_SVE_PNg4_10:
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case AARCH64_OPND_SVE_PNn:
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case AARCH64_OPND_SVE_PNt:
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case AARCH64_OPND_SME_PNg3:
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reg_type = REG_TYPE_PN;
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goto vector_reg;
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@ -6716,6 +6725,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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case AARCH64_OPND_SME_Zdnx4:
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case AARCH64_OPND_SME_Znx2:
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case AARCH64_OPND_SME_Znx4:
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case AARCH64_OPND_SME_Ztx2_STRIDED:
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case AARCH64_OPND_SME_Ztx4_STRIDED:
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reg_type = REG_TYPE_Z;
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goto vector_reg_list;
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3
gas/testsuite/gas/aarch64/sme2-2-invalid.d
Normal file
3
gas/testsuite/gas/aarch64/sme2-2-invalid.d
Normal file
@ -0,0 +1,3 @@
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#as: -march=armv8-a
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#source: sme2-2-invalid.s
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#error_output: sme2-2-invalid.l
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229
gas/testsuite/gas/aarch64/sme2-2-invalid.l
Normal file
229
gas/testsuite/gas/aarch64/sme2-2-invalid.l
Normal file
@ -0,0 +1,229 @@
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[^ :]+: Assembler messages:
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[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `ld1b 0,pn8/z,\[x0\]'
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[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 2 -- `ld1b {z0\.b-z1\.b},0,\[x0\]'
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[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,0'
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[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 1 -- `ld1b {z0\.b},pn8/z,\[x0\]'
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[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 1 -- `ld1b {z0\.b-z2\.b},pn8/z,\[x0\]'
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[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z1\.b-z2\.b},pn8/z,\[x0\]'
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[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1b {z0\.b-z1\.b},p8/z,\[x0\]'
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[^ :]+:[0-9]+: Error: operand mismatch -- `ld1b {z0\.b-z1\.b},pn8,\[x0\]'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: ld1b {z0\.b-z1\.b}, pn8/z, \[x0\]
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[^ :]+:[0-9]+: Error: operand mismatch -- `ld1b {z0\.b-z1\.b},pn8/m,\[x0\]'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: ld1b {z0\.b-z1\.b}, pn8/z, \[x0\]
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[^ :]+:[0-9]+: Error: operand mismatch -- `ld1b {z0\.b-z1\.b},pn8\.b,\[x0\]'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: ld1b {z0\.b-z1\.b}, pn8/z, \[x0\]
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[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1b {z0\.b-z1\.b},pn7/z,\[x0\]'
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[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[w0\]'
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[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[xzr\]'
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[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[x0,#1\]'
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[^ :]+:[0-9]+: Error: immediate offset out of range -16 to 14 at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[x0,#-32,mul vl\]'
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[^ :]+:[0-9]+: Error: immediate offset out of range -16 to 14 at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[x0,#-18,mul vl\]'
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[^ :]+:[0-9]+: Error: immediate value must be a multiple of 2 at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[x0,#-15,mul vl\]'
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[^ :]+:[0-9]+: Error: immediate value must be a multiple of 2 at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[x0,#-1,mul vl\]'
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[^ :]+:[0-9]+: Error: immediate value must be a multiple of 2 at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[x0,#1,mul vl\]'
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[^ :]+:[0-9]+: Error: immediate value must be a multiple of 2 at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[x0,#13,mul vl\]'
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[^ :]+:[0-9]+: Error: immediate offset out of range -16 to 14 at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[x0,#15,mul vl\]'
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[^ :]+:[0-9]+: Error: immediate offset out of range -16 to 14 at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[x0,#16,mul vl\]'
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[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z1\.b-z4\.b},pn8/z,\[x0\]'
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[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z2\.b-z5\.b},pn8/z,\[x0\]'
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[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z3\.b-z6\.b},pn8/z,\[x0\]'
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[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1b {z0\.b-z3\.b},p8/z,\[x0\]'
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[^ :]+:[0-9]+: Error: operand mismatch -- `ld1b {z0\.b-z3\.b},pn8,\[x0\]'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: ld1b {z0\.b-z3\.b}, pn8/z, \[x0\]
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[^ :]+:[0-9]+: Error: operand mismatch -- `ld1b {z0\.b-z3\.b},pn8/m,\[x0\]'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: ld1b {z0\.b-z3\.b}, pn8/z, \[x0\]
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[^ :]+:[0-9]+: Error: operand mismatch -- `ld1b {z0\.b-z3\.b},pn8\.b,\[x0\]'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: ld1b {z0\.b-z3\.b}, pn8/z, \[x0\]
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[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1b {z0\.b-z3\.b},pn0/z,\[x0\]'
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[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1b {z0\.b-z3\.b},pn7/z,\[x0\]'
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[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[w0\]'
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[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[xzr\]'
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[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#4\]'
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[^ :]+:[0-9]+: Error: immediate offset out of range -32 to 28 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#-36,mul vl\]'
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[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#-31,mul vl\]'
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[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#-30,mul vl\]'
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[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#-29,mul vl\]'
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[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#-14,mul vl\]'
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[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#-3,mul vl\]'
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[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#-2,mul vl\]'
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[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#-1,mul vl\]'
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[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#1,mul vl\]'
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[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#2,mul vl\]'
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[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#3,mul vl\]'
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[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#14,mul vl\]'
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[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#25,mul vl\]'
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[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#26,mul vl\]'
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[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#27,mul vl\]'
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[^ :]+:[0-9]+: Error: immediate offset out of range -32 to 28 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#29,mul vl\]'
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[^ :]+:[0-9]+: Error: immediate offset out of range -32 to 28 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#30,mul vl\]'
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[^ :]+:[0-9]+: Error: immediate offset out of range -32 to 28 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#31,mul vl\]'
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[^ :]+:[0-9]+: Error: immediate offset out of range -32 to 28 at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#32,mul vl\]'
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[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `ld1b {z0\.b,z8\.b,z16\.s},pn8/z,\[x0\]'
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[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `ld1b {z0\.b,z4\.b,z8\.s},pn8/z,\[x0\]'
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[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1b {z0\.b,z2\.b},pn8/z,\[x0\]`
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[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1b {z0\.b,z3\.b},pn8/z,\[x0\]`
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[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1b {z0\.b,z4\.b},pn8/z,\[x0\]`
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[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1b {z0\.b,z5\.b},pn8/z,\[x0\]`
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[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1b {z0\.b,z6\.b},pn8/z,\[x0\]`
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[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1b {z0\.b,z7\.b},pn8/z,\[x0\]`
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[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1b {z0\.b,z9\.b},pn8/z,\[x0\]`
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[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1b {z0\.b,z15\.b},pn8/z,\[x0\]`
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[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1b {z0\.b,z16\.b},pn8/z,\[x0\]`
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[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1b {z0\.b,z23\.b},pn8/z,\[x0\]`
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[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1b {z0\.b,z24\.b},pn8/z,\[x0\]`
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[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1b {z0\.b,z31\.b},pn8/z,\[x0\]`
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[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z8\.b,z16\.b},pn8/z,\[x0\]'
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[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z9\.b,z17\.b},pn8/z,\[x0\]'
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[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z10\.b,z18\.b},pn8/z,\[x0\]'
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[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z11\.b,z19\.b},pn8/z,\[x0\]'
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[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z12\.b,z20\.b},pn8/z,\[x0\]'
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[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z13\.b,z21\.b},pn8/z,\[x0\]'
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[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z14\.b,z22\.b},pn8/z,\[x0\]'
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[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z15\.b,z23\.b},pn8/z,\[x0\]'
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[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z24\.b,z0\.b},pn8/z,\[x0\]'
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[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z25\.b,z1\.b},pn8/z,\[x0\]'
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[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z26\.b,z2\.b},pn8/z,\[x0\]'
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[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z27\.b,z3\.b},pn8/z,\[x0\]'
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[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z28\.b,z4\.b},pn8/z,\[x0\]'
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[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z29\.b,z5\.b},pn8/z,\[x0\]'
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[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z30\.b,z6\.b},pn8/z,\[x0\]'
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[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z31\.b,z7\.b},pn8/z,\[x0\]'
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[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1b {z8\.b,z0\.b},pn8/z,\[x0\]`
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[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `ld1b {z0\.h,z8\.b},pn8/z,\[x0\]'
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[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `ld1b {z0\.b,z8\.h},pn8/z,\[x0\]'
|
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[^ :]+:[0-9]+: Error: operand mismatch -- `ld1b {z0\.h,z8\.h},pn8/z,\[x0\]'
|
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[^ :]+:[0-9]+: Info: did you mean this\?
|
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[^ :]+:[0-9]+: Info: ld1b {z0\.b, z8\.b}, pn8/z, \[x0\]
|
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[^ :]+:[0-9]+: Error: missing type suffix at operand 1 -- `ld1b {z0,z8},pn8/z,\[x0\]'
|
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[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1b {z0\.b,z8\.b},p8/z,\[x0\]'
|
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[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1b {z0\.b,z8\.b},pn8/z,\[w0\]'
|
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[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1b {z0\.b,z8\.b},pn8/z,\[xzr\]'
|
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[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b,z8\.b},pn8/z,\[x0,#-16\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b,z8\.b},pn8/z,\[x0,#-1\]'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range -16 to 14 at operand 3 -- `ld1b {z0\.b,z8\.b},pn8/z,\[x0,#-32,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range -16 to 14 at operand 3 -- `ld1b {z0\.b,z8\.b},pn8/z,\[x0,#-17,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: immediate value must be a multiple of 2 at operand 3 -- `ld1b {z0\.b,z8\.b},pn8/z,\[x0,#-15,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: immediate value must be a multiple of 2 at operand 3 -- `ld1b {z0\.b,z8\.b},pn8/z,\[x0,#-1,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: immediate value must be a multiple of 2 at operand 3 -- `ld1b {z0\.b,z8\.b},pn8/z,\[x0,#13,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range -16 to 14 at operand 3 -- `ld1b {z0\.b,z8\.b},pn8/z,\[x0,#15,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range -16 to 14 at operand 3 -- `ld1b {z0\.b,z8\.b},pn8/z,\[x0,#16,mul vl\]'
|
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[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z4\.b,z8\.b,z12\.b,z16\.b},pn8/z,\[x0\]'
|
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[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z5\.b,z9\.b,z13\.b,z17\.b},pn8/z,\[x0\]'
|
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[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z6\.b,z10\.b,z14\.b,z18\.b},pn8/z,\[x0\]'
|
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[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z7\.b,z11\.b,z15\.b,z19\.b},pn8/z,\[x0\]'
|
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[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z8\.b,z12\.b,z16\.b,z20\.b},pn8/z,\[x0\]'
|
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[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z9\.b,z13\.b,z17\.b,z21\.b},pn8/z,\[x0\]'
|
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[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z10\.b,z14\.b,z18\.b,z22\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z11\.b,z15\.b,z19\.b,z23\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z12\.b,z16\.b,z20\.b,z24\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z13\.b,z17\.b,z21\.b,z25\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z14\.b,z18\.b,z22\.b,z26\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z15\.b,z19\.b,z23\.b,z27\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z20\.b,z24\.b,z28\.b,z0\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 4 at operand 1 -- `ld1b {z0\.b,z2\.b,z4\.b,z6\.b},pn8/z,\[x0\]`
|
||||
[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 4 at operand 1 -- `ld1b {z0\.b,z3\.b,z6\.b,z9\.b},pn8/z,\[x0\]`
|
||||
[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 4 at operand 1 -- `ld1b {z0\.b,z8\.b,z16\.b,z24\.b},pn8/z,\[x0\]`
|
||||
[^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `ld1b {z0\.b,z4\.b,z5\.b,z6\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `ld1b {z0\.b,z4\.b,z8\.b,z9\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `ld1b {z0\.b,z1\.b,z3\.b,z7\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `ld1b {z0\.h,z4\.h,z8\.b,z12\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `ld1b {z0\.b,z4\.b,z8\.h,z12\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `ld1b {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: ld1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x0\]
|
||||
[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},p8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[w0\]'
|
||||
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[xzr\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#-32\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#-1\]'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range -32 to 28 at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#-64,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range -32 to 28 at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#-36,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#-31,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#-3,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#-2,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#-1,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#1,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#2,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#3,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#25,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#26,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: immediate value must be a multiple of 4 at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#27,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range -32 to 28 at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#29,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range -32 to 28 at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#32,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 1 -- `ld1b {z0\.b-z2\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z1\.b-z2\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1b {z0\.b-z1\.b},p8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `ld1b {z0\.b-z1\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: ld1b {z0\.b-z1\.b}, pn8/z, \[x0, x1\]
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `ld1b {z0\.b-z1\.b},pn8/m,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: ld1b {z0\.b-z1\.b}, pn8/z, \[x0, x1\]
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `ld1b {z0\.b-z1\.b},pn8\.b,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: ld1b {z0\.b-z1\.b}, pn8/z, \[x0, x1\]
|
||||
[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1b {z0\.b-z1\.b},pn0/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1b {z0\.b-z1\.b},pn7/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[w0,w1\]'
|
||||
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[xzr,x1\]'
|
||||
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[sp,sp\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[x0,x1,lsl#4\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[x0,w1,sxtw\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b-z1\.b},pn8/z,\[x0,w1,uxtw\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z1\.b-z4\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z2\.b-z5\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z3\.b-z6\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1b {z0\.b-z3\.b},p8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `ld1b {z0\.b-z3\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: ld1b {z0\.b-z3\.b}, pn8/z, \[x0, x1\]
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `ld1b {z0\.b-z3\.b},pn8/m,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: ld1b {z0\.b-z3\.b}, pn8/z, \[x0, x1\]
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `ld1b {z0\.b-z3\.b},pn8\.b,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: ld1b {z0\.b-z3\.b}, pn8/z, \[x0, x1\]
|
||||
[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1b {z0\.b-z3\.b},pn0/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1b {z0\.b-z3\.b},pn7/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[w0,w1\]'
|
||||
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[xzr,x1\]'
|
||||
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[sp,sp\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,x1,lsl#4\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,w1,sxtw\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b-z3\.b},pn8/z,\[x0,w1,uxtw\]'
|
||||
[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1b {z0\.b,z2\.b},pn8/z,\[x0,x1\]`
|
||||
[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1b {z0\.b,z3\.b},pn8/z,\[x0,x1\]`
|
||||
[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1b {z0\.b,z4\.b},pn8/z,\[x0,x1\]`
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z8\.b,z16\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z24\.b,z0\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1b {z8\.b,z0\.b},pn8/z,\[x0,x1\]`
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `ld1b {z0\.h,z8\.h},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: ld1b {z0\.b, z8\.b}, pn8/z, \[x0, x1\]
|
||||
[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1b {z0\.b,z8\.b},p8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1b {z0\.b,z8\.b},pn8/z,\[w0,w30\]'
|
||||
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1b {z0\.b,z8\.b},pn8/z,\[xzr,xzr\]'
|
||||
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ld1b {z0\.b,z8\.b},pn8/z,\[x0,sp\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b,z8\.b},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z4\.b,z8\.b,z12\.b,z16\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1b {z20\.b,z24\.b,z28\.b,z0\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `ld1b {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: ld1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x0, x1\]
|
||||
[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},p8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[w0,w30\]'
|
||||
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[xzr,xzr\]'
|
||||
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,sp\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,x1,lsl#1\]'
|
||||
205
gas/testsuite/gas/aarch64/sme2-2-invalid.s
Normal file
205
gas/testsuite/gas/aarch64/sme2-2-invalid.s
Normal file
@ -0,0 +1,205 @@
|
||||
ld1b 0, pn8/z, [x0]
|
||||
ld1b { z0.b - z1.b }, 0, [x0]
|
||||
ld1b { z0.b - z1.b }, pn8/z, 0
|
||||
|
||||
ld1b { z0.b }, pn8/z, [x0]
|
||||
ld1b { z0.b - z2.b }, pn8/z, [x0]
|
||||
ld1b { z1.b - z2.b }, pn8/z, [x0]
|
||||
ld1b { z0.b - z1.b }, p8/z, [x0]
|
||||
ld1b { z0.b - z1.b }, pn8, [x0]
|
||||
ld1b { z0.b - z1.b }, pn8/m, [x0]
|
||||
ld1b { z0.b - z1.b }, pn8.b, [x0]
|
||||
ld1b { z0.b - z1.b }, pn7/z, [x0]
|
||||
ld1b { z0.b - z1.b }, pn8/z, [w0]
|
||||
ld1b { z0.b - z1.b }, pn8/z, [xzr]
|
||||
ld1b { z0.b - z1.b }, pn8/z, [x0, #1]
|
||||
ld1b { z0.b - z1.b }, pn8/z, [x0, #-32, mul vl]
|
||||
ld1b { z0.b - z1.b }, pn8/z, [x0, #-18, mul vl]
|
||||
ld1b { z0.b - z1.b }, pn8/z, [x0, #-15, mul vl]
|
||||
ld1b { z0.b - z1.b }, pn8/z, [x0, #-1, mul vl]
|
||||
ld1b { z0.b - z1.b }, pn8/z, [x0, #1, mul vl]
|
||||
ld1b { z0.b - z1.b }, pn8/z, [x0, #13, mul vl]
|
||||
ld1b { z0.b - z1.b }, pn8/z, [x0, #15, mul vl]
|
||||
ld1b { z0.b - z1.b }, pn8/z, [x0, #16, mul vl]
|
||||
|
||||
ld1b { z1.b - z4.b }, pn8/z, [x0]
|
||||
ld1b { z2.b - z5.b }, pn8/z, [x0]
|
||||
ld1b { z3.b - z6.b }, pn8/z, [x0]
|
||||
ld1b { z0.b - z3.b }, p8/z, [x0]
|
||||
ld1b { z0.b - z3.b }, pn8, [x0]
|
||||
ld1b { z0.b - z3.b }, pn8/m, [x0]
|
||||
ld1b { z0.b - z3.b }, pn8.b, [x0]
|
||||
ld1b { z0.b - z3.b }, pn0/z, [x0]
|
||||
ld1b { z0.b - z3.b }, pn7/z, [x0]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [w0]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [xzr]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [x0, #4]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [x0, #-36, mul vl]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [x0, #-31, mul vl]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [x0, #-30, mul vl]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [x0, #-29, mul vl]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [x0, #-14, mul vl]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [x0, #-3, mul vl]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [x0, #-2, mul vl]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [x0, #-1, mul vl]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [x0, #1, mul vl]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [x0, #2, mul vl]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [x0, #3, mul vl]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [x0, #14, mul vl]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [x0, #25, mul vl]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [x0, #26, mul vl]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [x0, #27, mul vl]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [x0, #29, mul vl]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [x0, #30, mul vl]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [x0, #31, mul vl]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [x0, #32, mul vl]
|
||||
|
||||
ld1b { z0.b, z8.b, z16.s }, pn8/z, [x0]
|
||||
ld1b { z0.b, z4.b, z8.s }, pn8/z, [x0]
|
||||
|
||||
ld1b { z0.b, z2.b }, pn8/z, [x0]
|
||||
ld1b { z0.b, z3.b }, pn8/z, [x0]
|
||||
ld1b { z0.b, z4.b }, pn8/z, [x0]
|
||||
ld1b { z0.b, z5.b }, pn8/z, [x0]
|
||||
ld1b { z0.b, z6.b }, pn8/z, [x0]
|
||||
ld1b { z0.b, z7.b }, pn8/z, [x0]
|
||||
ld1b { z0.b, z9.b }, pn8/z, [x0]
|
||||
ld1b { z0.b, z15.b }, pn8/z, [x0]
|
||||
ld1b { z0.b, z16.b }, pn8/z, [x0]
|
||||
ld1b { z0.b, z23.b }, pn8/z, [x0]
|
||||
ld1b { z0.b, z24.b }, pn8/z, [x0]
|
||||
ld1b { z0.b, z31.b }, pn8/z, [x0]
|
||||
ld1b { z8.b, z16.b }, pn8/z, [x0]
|
||||
ld1b { z9.b, z17.b }, pn8/z, [x0]
|
||||
ld1b { z10.b, z18.b }, pn8/z, [x0]
|
||||
ld1b { z11.b, z19.b }, pn8/z, [x0]
|
||||
ld1b { z12.b, z20.b }, pn8/z, [x0]
|
||||
ld1b { z13.b, z21.b }, pn8/z, [x0]
|
||||
ld1b { z14.b, z22.b }, pn8/z, [x0]
|
||||
ld1b { z15.b, z23.b }, pn8/z, [x0]
|
||||
ld1b { z24.b, z0.b }, pn8/z, [x0]
|
||||
ld1b { z25.b, z1.b }, pn8/z, [x0]
|
||||
ld1b { z26.b, z2.b }, pn8/z, [x0]
|
||||
ld1b { z27.b, z3.b }, pn8/z, [x0]
|
||||
ld1b { z28.b, z4.b }, pn8/z, [x0]
|
||||
ld1b { z29.b, z5.b }, pn8/z, [x0]
|
||||
ld1b { z30.b, z6.b }, pn8/z, [x0]
|
||||
ld1b { z31.b, z7.b }, pn8/z, [x0]
|
||||
ld1b { z8.b, z0.b }, pn8/z, [x0]
|
||||
ld1b { z0.h, z8.b }, pn8/z, [x0]
|
||||
ld1b { z0.b, z8.h }, pn8/z, [x0]
|
||||
ld1b { z0.h, z8.h }, pn8/z, [x0]
|
||||
ld1b { z0, z8 }, pn8/z, [x0]
|
||||
ld1b { z0.b, z8.b }, p8/z, [x0]
|
||||
ld1b { z0.b, z8.b }, pn8/z, [w0]
|
||||
ld1b { z0.b, z8.b }, pn8/z, [xzr]
|
||||
ld1b { z0.b, z8.b }, pn8/z, [x0, #-16]
|
||||
ld1b { z0.b, z8.b }, pn8/z, [x0, #-1]
|
||||
ld1b { z0.b, z8.b }, pn8/z, [x0, #-32, mul vl]
|
||||
ld1b { z0.b, z8.b }, pn8/z, [x0, #-17, mul vl]
|
||||
ld1b { z0.b, z8.b }, pn8/z, [x0, #-15, mul vl]
|
||||
ld1b { z0.b, z8.b }, pn8/z, [x0, #-1, mul vl]
|
||||
ld1b { z0.b, z8.b }, pn8/z, [x0, #13, mul vl]
|
||||
ld1b { z0.b, z8.b }, pn8/z, [x0, #15, mul vl]
|
||||
ld1b { z0.b, z8.b }, pn8/z, [x0, #16, mul vl]
|
||||
|
||||
ld1b { z4.b, z8.b, z12.b, z16.b }, pn8/z, [x0]
|
||||
ld1b { z5.b, z9.b, z13.b, z17.b }, pn8/z, [x0]
|
||||
ld1b { z6.b, z10.b, z14.b, z18.b }, pn8/z, [x0]
|
||||
ld1b { z7.b, z11.b, z15.b, z19.b }, pn8/z, [x0]
|
||||
ld1b { z8.b, z12.b, z16.b, z20.b }, pn8/z, [x0]
|
||||
ld1b { z9.b, z13.b, z17.b, z21.b }, pn8/z, [x0]
|
||||
ld1b { z10.b, z14.b, z18.b, z22.b }, pn8/z, [x0]
|
||||
ld1b { z11.b, z15.b, z19.b, z23.b }, pn8/z, [x0]
|
||||
ld1b { z12.b, z16.b, z20.b, z24.b }, pn8/z, [x0]
|
||||
ld1b { z13.b, z17.b, z21.b, z25.b }, pn8/z, [x0]
|
||||
ld1b { z14.b, z18.b, z22.b, z26.b }, pn8/z, [x0]
|
||||
ld1b { z15.b, z19.b, z23.b, z27.b }, pn8/z, [x0]
|
||||
ld1b { z20.b, z24.b, z28.b, z0.b }, pn8/z, [x0]
|
||||
ld1b { z0.b, z2.b, z4.b, z6.b }, pn8/z, [x0]
|
||||
ld1b { z0.b, z3.b, z6.b, z9.b }, pn8/z, [x0]
|
||||
ld1b { z0.b, z8.b, z16.b, z24.b }, pn8/z, [x0]
|
||||
ld1b { z0.b, z4.b, z5.b, z6.b }, pn8/z, [x0]
|
||||
ld1b { z0.b, z4.b, z8.b, z9.b }, pn8/z, [x0]
|
||||
ld1b { z0.b, z1.b, z3.b, z7.b }, pn8/z, [x0]
|
||||
ld1b { z0.h, z4.h, z8.b, z12.b }, pn8/z, [x0]
|
||||
ld1b { z0.b, z4.b, z8.h, z12.h }, pn8/z, [x0]
|
||||
ld1b { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0]
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, p8/z, [x0]
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [w0]
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [xzr]
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #-32]
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #-1]
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #-64, mul vl]
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #-36, mul vl]
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #-31, mul vl]
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #-3, mul vl]
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #-2, mul vl]
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #-1, mul vl]
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #1, mul vl]
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #2, mul vl]
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #3, mul vl]
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #25, mul vl]
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #26, mul vl]
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #27, mul vl]
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #29, mul vl]
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #32, mul vl]
|
||||
|
||||
ld1b { z0.b - z2.b }, pn8/z, [x0, x1]
|
||||
ld1b { z1.b - z2.b }, pn8/z, [x0, x1]
|
||||
ld1b { z0.b - z1.b }, p8/z, [x0, x1]
|
||||
ld1b { z0.b - z1.b }, pn8, [x0, x1]
|
||||
ld1b { z0.b - z1.b }, pn8/m, [x0, x1]
|
||||
ld1b { z0.b - z1.b }, pn8.b, [x0, x1]
|
||||
ld1b { z0.b - z1.b }, pn0/z, [x0, x1]
|
||||
ld1b { z0.b - z1.b }, pn7/z, [x0, x1]
|
||||
ld1b { z0.b - z1.b }, pn8/z, [w0, w1]
|
||||
ld1b { z0.b - z1.b }, pn8/z, [xzr, x1]
|
||||
ld1b { z0.b - z1.b }, pn8/z, [sp, sp]
|
||||
ld1b { z0.b - z1.b }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1b { z0.b - z1.b }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1b { z0.b - z1.b }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1b { z0.b - z1.b }, pn8/z, [x0, x1, lsl #4]
|
||||
ld1b { z0.b - z1.b }, pn8/z, [x0, w1, sxtw]
|
||||
ld1b { z0.b - z1.b }, pn8/z, [x0, w1, uxtw]
|
||||
|
||||
ld1b { z1.b - z4.b }, pn8/z, [x0, x1]
|
||||
ld1b { z2.b - z5.b }, pn8/z, [x0, x1]
|
||||
ld1b { z3.b - z6.b }, pn8/z, [x0, x1]
|
||||
ld1b { z0.b - z3.b }, p8/z, [x0, x1]
|
||||
ld1b { z0.b - z3.b }, pn8, [x0, x1]
|
||||
ld1b { z0.b - z3.b }, pn8/m, [x0, x1]
|
||||
ld1b { z0.b - z3.b }, pn8.b, [x0, x1]
|
||||
ld1b { z0.b - z3.b }, pn0/z, [x0, x1]
|
||||
ld1b { z0.b - z3.b }, pn7/z, [x0, x1]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [w0, w1]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [xzr, x1]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [sp, sp]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [x0, x1, lsl #4]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [x0, w1, sxtw]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [x0, w1, uxtw]
|
||||
|
||||
ld1b { z0.b, z2.b }, pn8/z, [x0, x1]
|
||||
ld1b { z0.b, z3.b }, pn8/z, [x0, x1]
|
||||
ld1b { z0.b, z4.b }, pn8/z, [x0, x1]
|
||||
ld1b { z8.b, z16.b }, pn8/z, [x0, x1]
|
||||
ld1b { z24.b, z0.b }, pn8/z, [x0, x1]
|
||||
ld1b { z8.b, z0.b }, pn8/z, [x0, x1]
|
||||
ld1b { z0.h, z8.h }, pn8/z, [x0, x1]
|
||||
ld1b { z0.b, z8.b }, p8/z, [x0, x1]
|
||||
ld1b { z0.b, z8.b }, pn8/z, [w0, w30]
|
||||
ld1b { z0.b, z8.b }, pn8/z, [xzr, xzr]
|
||||
ld1b { z0.b, z8.b }, pn8/z, [x0, sp]
|
||||
ld1b { z0.b, z8.b }, pn8/z, [x0, x1, lsl #1]
|
||||
|
||||
ld1b { z4.b, z8.b, z12.b, z16.b }, pn8/z, [x0, x1]
|
||||
ld1b { z20.b, z24.b, z28.b, z0.b }, pn8/z, [x0, x1]
|
||||
ld1b { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, x1]
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, p8/z, [x0, x1]
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [w0, w30]
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [xzr, xzr]
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, sp]
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, x1, lsl #1]
|
||||
3
gas/testsuite/gas/aarch64/sme2-2-noarch.d
Normal file
3
gas/testsuite/gas/aarch64/sme2-2-noarch.d
Normal file
@ -0,0 +1,3 @@
|
||||
#as: -march=armv8-a+sme
|
||||
#source: sme2-2.s
|
||||
#error_output: sme2-2-noarch.l
|
||||
481
gas/testsuite/gas/aarch64/sme2-2-noarch.l
Normal file
481
gas/testsuite/gas/aarch64/sme2-2-noarch.l
Normal file
@ -0,0 +1,481 @@
|
||||
[^ :]+: Assembler messages:
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z1\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z1\.b},pn8/z,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {Z0\.B-Z1\.B},PN8/Z,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z30\.b-z31\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z1\.b},pn15/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z1\.b},pn8/z,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z1\.b},pn8/z,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z1\.b},pn8/z,\[x0,#-16,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z1\.b},pn8/z,\[x0,#14,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z12\.b-z13\.b},pn13/z,\[x11,#-10,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z3\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {Z0\.B-Z3\.B},PN8/Z,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z28\.b-z31\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z3\.b},pn15/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z3\.b},pn8/z,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z3\.b},pn8/z,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#-32,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z3\.b},pn8/z,\[x0,#28,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z8\.b-z11\.b},pn11/z,\[x17,#20,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z8\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z8\.b},pn8/z,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {Z0\.B,Z8\.B},PN8/Z,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z1\.b,z9\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z2\.b,z10\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z3\.b,z11\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z4\.b,z12\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z5\.b,z13\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z6\.b,z14\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z7\.b,z15\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z16\.b,z24\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z17\.b,z25\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z18\.b,z26\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z19\.b,z27\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z20\.b,z28\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z21\.b,z29\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z22\.b,z30\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z23\.b,z31\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z8\.b},pn15/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z8\.b},pn8/z,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z8\.b},pn8/z,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z8\.b},pn8/z,\[x0,#-16,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z8\.b},pn8/z,\[x0,#14,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z3\.b,z11\.b},pn10/z,\[x22,#6,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {Z0\.B,Z4\.B,Z8\.B,Z12\.B},PN8/Z,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z1\.b,z5\.b,z9\.b,z13\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z2\.b,z6\.b,z10\.b,z14\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z3\.b,z7\.b,z11\.b,z15\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z16\.b,z20\.b,z24\.b,z28\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z17\.b,z21\.b,z25\.b,z29\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z18\.b,z22\.b,z26\.b,z30\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z19\.b,z23\.b,z27\.b,z31\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn15/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#-32,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#28,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z2\.b,z6\.b,z10\.b,z14\.b},pn14/z,\[x29,#8,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z1\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z1\.b},pn8/z,\[x0,x1,lsl#0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {Z0\.B-Z1\.B},PN8/Z,\[X0,X1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z30\.b-z31\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z1\.b},pn15/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z1\.b},pn8/z,\[x30,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z1\.b},pn8/z,\[sp,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z1\.b},pn8/z,\[x0,x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z1\.b},pn8/z,\[x0,xzr\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z14\.b-z15\.b},pn9/z,\[x26,x3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z3\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z3\.b},pn8/z,\[x0,x1,lsl#0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {Z0\.B-Z3\.B},PN8/Z,\[X0,X1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z28\.b-z31\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z3\.b},pn15/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z3\.b},pn8/z,\[x30,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z3\.b},pn8/z,\[sp,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z3\.b},pn8/z,\[x0,x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b-z3\.b},pn8/z,\[x0,xzr\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z8\.b-z11\.b},pn11/z,\[x27,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z8\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z8\.b},pn8/z,\[x0,x1,lsl#0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {Z0\.B,Z8\.B},PN8/Z,\[X0,X1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z1\.b,z9\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z2\.b,z10\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z3\.b,z11\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z4\.b,z12\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z5\.b,z13\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z6\.b,z14\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z7\.b,z15\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z16\.b,z24\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z17\.b,z25\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z18\.b,z26\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z19\.b,z27\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z20\.b,z28\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z21\.b,z29\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z22\.b,z30\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z23\.b,z31\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z8\.b},pn15/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z8\.b},pn8/z,\[x30,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z8\.b},pn8/z,\[sp,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z8\.b},pn8/z,\[x0,x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z8\.b},pn8/z,\[x0,xzr\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z5\.b,z13\.b},pn14/z,\[x15,x24\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,x1,lsl#0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {Z0\.B,Z4\.B,Z8\.B,Z12\.B},PN8/Z,\[X0,X1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z1\.b,z5\.b,z9\.b,z13\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z2\.b,z6\.b,z10\.b,z14\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z3\.b,z7\.b,z11\.b,z15\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z16\.b,z20\.b,z24\.b,z28\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z17\.b,z21\.b,z25\.b,z29\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z18\.b,z22\.b,z26\.b,z30\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z19\.b,z23\.b,z27\.b,z31\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn15/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x30,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[sp,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,xzr\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1b {z17\.b,z21\.b,z25\.b,z29\.b},pn11/z,\[x4,x6\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z1\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z1\.b},pn8/z,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {Z0\.B-Z1\.B},PN8/Z,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z30\.b-z31\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z1\.b},pn15/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z1\.b},pn8/z,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z1\.b},pn8/z,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z1\.b},pn8/z,\[x0,#-16,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z1\.b},pn8/z,\[x0,#14,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z12\.b-z13\.b},pn13/z,\[x11,#-10,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z3\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z3\.b},pn8/z,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {Z0\.B-Z3\.B},PN8/Z,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z28\.b-z31\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z3\.b},pn15/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z3\.b},pn8/z,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z3\.b},pn8/z,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z3\.b},pn8/z,\[x0,#-32,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z3\.b},pn8/z,\[x0,#28,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z8\.b-z11\.b},pn11/z,\[x17,#20,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z8\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z8\.b},pn8/z,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {Z0\.B,Z8\.B},PN8/Z,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z1\.b,z9\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z2\.b,z10\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z3\.b,z11\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z4\.b,z12\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z5\.b,z13\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z6\.b,z14\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z7\.b,z15\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z16\.b,z24\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z17\.b,z25\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z18\.b,z26\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z19\.b,z27\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z20\.b,z28\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z21\.b,z29\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z22\.b,z30\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z23\.b,z31\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z8\.b},pn15/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z8\.b},pn8/z,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z8\.b},pn8/z,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z8\.b},pn8/z,\[x0,#-16,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z8\.b},pn8/z,\[x0,#14,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z3\.b,z11\.b},pn10/z,\[x22,#6,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {Z0\.B,Z4\.B,Z8\.B,Z12\.B},PN8/Z,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z1\.b,z5\.b,z9\.b,z13\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z2\.b,z6\.b,z10\.b,z14\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z3\.b,z7\.b,z11\.b,z15\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z16\.b,z20\.b,z24\.b,z28\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z17\.b,z21\.b,z25\.b,z29\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z18\.b,z22\.b,z26\.b,z30\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z19\.b,z23\.b,z27\.b,z31\.b},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn15/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#-32,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,#28,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z2\.b,z6\.b,z10\.b,z14\.b},pn14/z,\[x29,#8,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z1\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z1\.b},pn8/z,\[x0,x1,lsl#0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {Z0\.B-Z1\.B},PN8/Z,\[X0,X1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z30\.b-z31\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z1\.b},pn15/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z1\.b},pn8/z,\[x30,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z1\.b},pn8/z,\[sp,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z1\.b},pn8/z,\[x0,x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z1\.b},pn8/z,\[x0,xzr\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z14\.b-z15\.b},pn9/z,\[x26,x3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z3\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z3\.b},pn8/z,\[x0,x1,lsl#0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {Z0\.B-Z3\.B},PN8/Z,\[X0,X1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z28\.b-z31\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z3\.b},pn15/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z3\.b},pn8/z,\[x30,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z3\.b},pn8/z,\[sp,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z3\.b},pn8/z,\[x0,x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b-z3\.b},pn8/z,\[x0,xzr\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z8\.b-z11\.b},pn11/z,\[x27,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z8\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z8\.b},pn8/z,\[x0,x1,lsl#0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {Z0\.B,Z8\.B},PN8/Z,\[X0,X1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z1\.b,z9\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z2\.b,z10\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z3\.b,z11\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z4\.b,z12\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z5\.b,z13\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z6\.b,z14\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z7\.b,z15\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z16\.b,z24\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z17\.b,z25\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z18\.b,z26\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z19\.b,z27\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z20\.b,z28\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z21\.b,z29\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z22\.b,z30\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z23\.b,z31\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z8\.b},pn15/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z8\.b},pn8/z,\[x30,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z8\.b},pn8/z,\[sp,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z8\.b},pn8/z,\[x0,x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z8\.b},pn8/z,\[x0,xzr\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z5\.b,z13\.b},pn14/z,\[x15,x24\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,x1,lsl#0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {Z0\.B,Z4\.B,Z8\.B,Z12\.B},PN8/Z,\[X0,X1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z1\.b,z5\.b,z9\.b,z13\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z2\.b,z6\.b,z10\.b,z14\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z3\.b,z7\.b,z11\.b,z15\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z16\.b,z20\.b,z24\.b,z28\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z17\.b,z21\.b,z25\.b,z29\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z18\.b,z22\.b,z26\.b,z30\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z19\.b,z23\.b,z27\.b,z31\.b},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn15/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x30,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[sp,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8/z,\[x0,xzr\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z17\.b,z21\.b,z25\.b,z29\.b},pn11/z,\[x4,x6\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z1\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z1\.b},pn8,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {Z0\.B-Z1\.B},PN8,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z30\.b-z31\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z1\.b},pn15,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z1\.b},pn8,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z1\.b},pn8,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z1\.b},pn8,\[x0,#-16,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z1\.b},pn8,\[x0,#14,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z12\.b-z13\.b},pn13,\[x11,#-10,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z3\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z3\.b},pn8,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {Z0\.B-Z3\.B},PN8,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z28\.b-z31\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z3\.b},pn15,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z3\.b},pn8,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z3\.b},pn8,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z3\.b},pn8,\[x0,#-32,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z3\.b},pn8,\[x0,#28,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z8\.b-z11\.b},pn11,\[x17,#20,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z8\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z8\.b},pn8,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {Z0\.B,Z8\.B},PN8,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z1\.b,z9\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z2\.b,z10\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z3\.b,z11\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z4\.b,z12\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z5\.b,z13\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z6\.b,z14\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z7\.b,z15\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z16\.b,z24\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z17\.b,z25\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z18\.b,z26\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z19\.b,z27\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z20\.b,z28\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z21\.b,z29\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z22\.b,z30\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z23\.b,z31\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z8\.b},pn15,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z8\.b},pn8,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z8\.b},pn8,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z8\.b},pn8,\[x0,#-16,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z8\.b},pn8,\[x0,#14,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z3\.b,z11\.b},pn10,\[x22,#6,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {Z0\.B,Z4\.B,Z8\.B,Z12\.B},PN8,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z1\.b,z5\.b,z9\.b,z13\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z2\.b,z6\.b,z10\.b,z14\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z3\.b,z7\.b,z11\.b,z15\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z16\.b,z20\.b,z24\.b,z28\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z17\.b,z21\.b,z25\.b,z29\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z18\.b,z22\.b,z26\.b,z30\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z19\.b,z23\.b,z27\.b,z31\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z4\.b,z8\.b,z12\.b},pn15,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x0,#-32,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x0,#28,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z2\.b,z6\.b,z10\.b,z14\.b},pn14,\[x29,#8,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z1\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z1\.b},pn8,\[x0,x1,lsl#0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {Z0\.B-Z1\.B},PN8,\[X0,X1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z30\.b-z31\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z1\.b},pn15,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z1\.b},pn8,\[x30,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z1\.b},pn8,\[sp,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z1\.b},pn8,\[x0,x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z1\.b},pn8,\[x0,xzr\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z14\.b-z15\.b},pn9,\[x26,x3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z3\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z3\.b},pn8,\[x0,x1,lsl#0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {Z0\.B-Z3\.B},PN8,\[X0,X1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z28\.b-z31\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z3\.b},pn15,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z3\.b},pn8,\[x30,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z3\.b},pn8,\[sp,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z3\.b},pn8,\[x0,x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b-z3\.b},pn8,\[x0,xzr\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z8\.b-z11\.b},pn11,\[x27,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z8\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z8\.b},pn8,\[x0,x1,lsl#0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {Z0\.B,Z8\.B},PN8,\[X0,X1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z1\.b,z9\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z2\.b,z10\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z3\.b,z11\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z4\.b,z12\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z5\.b,z13\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z6\.b,z14\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z7\.b,z15\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z16\.b,z24\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z17\.b,z25\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z18\.b,z26\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z19\.b,z27\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z20\.b,z28\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z21\.b,z29\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z22\.b,z30\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z23\.b,z31\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z8\.b},pn15,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z8\.b},pn8,\[x30,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z8\.b},pn8,\[sp,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z8\.b},pn8,\[x0,x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z8\.b},pn8,\[x0,xzr\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z5\.b,z13\.b},pn14,\[x15,x24\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x0,x1,lsl#0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {Z0\.B,Z4\.B,Z8\.B,Z12\.B},PN8,\[X0,X1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z1\.b,z5\.b,z9\.b,z13\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z2\.b,z6\.b,z10\.b,z14\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z3\.b,z7\.b,z11\.b,z15\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z16\.b,z20\.b,z24\.b,z28\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z17\.b,z21\.b,z25\.b,z29\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z18\.b,z22\.b,z26\.b,z30\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z19\.b,z23\.b,z27\.b,z31\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z4\.b,z8\.b,z12\.b},pn15,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x30,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[sp,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x0,x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x0,xzr\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1b {z17\.b,z21\.b,z25\.b,z29\.b},pn11,\[x4,x6\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z1\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z1\.b},pn8,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {Z0\.B-Z1\.B},PN8,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z30\.b-z31\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z1\.b},pn15,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z1\.b},pn8,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z1\.b},pn8,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z1\.b},pn8,\[x0,#-16,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z1\.b},pn8,\[x0,#14,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z12\.b-z13\.b},pn13,\[x11,#-10,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z3\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z3\.b},pn8,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {Z0\.B-Z3\.B},PN8,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z28\.b-z31\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z3\.b},pn15,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z3\.b},pn8,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z3\.b},pn8,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z3\.b},pn8,\[x0,#-32,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z3\.b},pn8,\[x0,#28,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z8\.b-z11\.b},pn11,\[x17,#20,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z8\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z8\.b},pn8,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {Z0\.B,Z8\.B},PN8,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z1\.b,z9\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z2\.b,z10\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z3\.b,z11\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z4\.b,z12\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z5\.b,z13\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z6\.b,z14\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z7\.b,z15\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z16\.b,z24\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z17\.b,z25\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z18\.b,z26\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z19\.b,z27\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z20\.b,z28\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z21\.b,z29\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z22\.b,z30\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z23\.b,z31\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z8\.b},pn15,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z8\.b},pn8,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z8\.b},pn8,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z8\.b},pn8,\[x0,#-16,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z8\.b},pn8,\[x0,#14,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z3\.b,z11\.b},pn10,\[x22,#6,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {Z0\.B,Z4\.B,Z8\.B,Z12\.B},PN8,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z1\.b,z5\.b,z9\.b,z13\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z2\.b,z6\.b,z10\.b,z14\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z3\.b,z7\.b,z11\.b,z15\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z16\.b,z20\.b,z24\.b,z28\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z17\.b,z21\.b,z25\.b,z29\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z18\.b,z22\.b,z26\.b,z30\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z19\.b,z23\.b,z27\.b,z31\.b},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn15,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x0,#-32,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x0,#28,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z2\.b,z6\.b,z10\.b,z14\.b},pn14,\[x29,#8,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z1\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z1\.b},pn8,\[x0,x1,lsl#0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {Z0\.B-Z1\.B},PN8,\[X0,X1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z30\.b-z31\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z1\.b},pn15,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z1\.b},pn8,\[x30,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z1\.b},pn8,\[sp,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z1\.b},pn8,\[x0,x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z1\.b},pn8,\[x0,xzr\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z14\.b-z15\.b},pn9,\[x26,x3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z3\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z3\.b},pn8,\[x0,x1,lsl#0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {Z0\.B-Z3\.B},PN8,\[X0,X1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z28\.b-z31\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z3\.b},pn15,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z3\.b},pn8,\[x30,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z3\.b},pn8,\[sp,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z3\.b},pn8,\[x0,x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b-z3\.b},pn8,\[x0,xzr\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z8\.b-z11\.b},pn11,\[x27,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z8\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z8\.b},pn8,\[x0,x1,lsl#0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {Z0\.B,Z8\.B},PN8,\[X0,X1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z1\.b,z9\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z2\.b,z10\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z3\.b,z11\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z4\.b,z12\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z5\.b,z13\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z6\.b,z14\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z7\.b,z15\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z16\.b,z24\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z17\.b,z25\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z18\.b,z26\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z19\.b,z27\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z20\.b,z28\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z21\.b,z29\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z22\.b,z30\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z23\.b,z31\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z8\.b},pn15,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z8\.b},pn8,\[x30,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z8\.b},pn8,\[sp,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z8\.b},pn8,\[x0,x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z8\.b},pn8,\[x0,xzr\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z5\.b,z13\.b},pn14,\[x15,x24\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x0,x1,lsl#0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {Z0\.B,Z4\.B,Z8\.B,Z12\.B},PN8,\[X0,X1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z1\.b,z5\.b,z9\.b,z13\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z2\.b,z6\.b,z10\.b,z14\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z3\.b,z7\.b,z11\.b,z15\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z16\.b,z20\.b,z24\.b,z28\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z17\.b,z21\.b,z25\.b,z29\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z18\.b,z22\.b,z26\.b,z30\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z19\.b,z23\.b,z27\.b,z31\.b},pn8,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn15,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x30,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[sp,x1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x0,x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.b,z4\.b,z8\.b,z12\.b},pn8,\[x0,xzr\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z17\.b,z21\.b,z25\.b,z29\.b},pn11,\[x4,x6\]'
|
||||
489
gas/testsuite/gas/aarch64/sme2-2.d
Normal file
489
gas/testsuite/gas/aarch64/sme2-2.d
Normal file
@ -0,0 +1,489 @@
|
||||
#as: -march=armv8-a+sme2
|
||||
#objdump: -dr
|
||||
|
||||
[^:]+: file format .*
|
||||
|
||||
|
||||
[^:]+:
|
||||
|
||||
[^:]+:
|
||||
[^:]+: a0400000 ld1b {z0\.b-z1\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a0400000 ld1b {z0\.b-z1\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a0400000 ld1b {z0\.b-z1\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a040001e ld1b {z30\.b-z31\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a0401c00 ld1b {z0\.b-z1\.b}, pn15/z, \[x0\]
|
||||
[^:]+: a04003c0 ld1b {z0\.b-z1\.b}, pn8/z, \[x30\]
|
||||
[^:]+: a04003e0 ld1b {z0\.b-z1\.b}, pn8/z, \[sp\]
|
||||
[^:]+: a0480000 ld1b {z0\.b-z1\.b}, pn8/z, \[x0, #-16, mul vl\]
|
||||
[^:]+: a0470000 ld1b {z0\.b-z1\.b}, pn8/z, \[x0, #14, mul vl\]
|
||||
[^:]+: a04b156c ld1b {z12\.b-z13\.b}, pn13/z, \[x11, #-10, mul vl\]
|
||||
[^:]+: a0408000 ld1b {z0\.b-z3\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a0408000 ld1b {z0\.b-z3\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a0408000 ld1b {z0\.b-z3\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a040801c ld1b {z28\.b-z31\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a0409c00 ld1b {z0\.b-z3\.b}, pn15/z, \[x0\]
|
||||
[^:]+: a04083c0 ld1b {z0\.b-z3\.b}, pn8/z, \[x30\]
|
||||
[^:]+: a04083e0 ld1b {z0\.b-z3\.b}, pn8/z, \[sp\]
|
||||
[^:]+: a0488000 ld1b {z0\.b-z3\.b}, pn8/z, \[x0, #-32, mul vl\]
|
||||
[^:]+: a0478000 ld1b {z0\.b-z3\.b}, pn8/z, \[x0, #28, mul vl\]
|
||||
[^:]+: a0458e28 ld1b {z8\.b-z11\.b}, pn11/z, \[x17, #20, mul vl\]
|
||||
[^:]+: a1400000 ld1b {z0\.b, z8\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1400000 ld1b {z0\.b, z8\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1400000 ld1b {z0\.b, z8\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1400001 ld1b {z1\.b, z9\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1400002 ld1b {z2\.b, z10\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1400003 ld1b {z3\.b, z11\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1400004 ld1b {z4\.b, z12\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1400005 ld1b {z5\.b, z13\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1400006 ld1b {z6\.b, z14\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1400007 ld1b {z7\.b, z15\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1400010 ld1b {z16\.b, z24\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1400011 ld1b {z17\.b, z25\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1400012 ld1b {z18\.b, z26\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1400013 ld1b {z19\.b, z27\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1400014 ld1b {z20\.b, z28\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1400015 ld1b {z21\.b, z29\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1400016 ld1b {z22\.b, z30\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1400017 ld1b {z23\.b, z31\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1401c00 ld1b {z0\.b, z8\.b}, pn15/z, \[x0\]
|
||||
[^:]+: a14003c0 ld1b {z0\.b, z8\.b}, pn8/z, \[x30\]
|
||||
[^:]+: a14003e0 ld1b {z0\.b, z8\.b}, pn8/z, \[sp\]
|
||||
[^:]+: a1480000 ld1b {z0\.b, z8\.b}, pn8/z, \[x0, #-16, mul vl\]
|
||||
[^:]+: a1470000 ld1b {z0\.b, z8\.b}, pn8/z, \[x0, #14, mul vl\]
|
||||
[^:]+: a1430ac3 ld1b {z3\.b, z11\.b}, pn10/z, \[x22, #6, mul vl\]
|
||||
[^:]+: a1408000 ld1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1408000 ld1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1408000 ld1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1408001 ld1b {z1\.b, z5\.b, z9\.b, z13\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1408002 ld1b {z2\.b, z6\.b, z10\.b, z14\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1408003 ld1b {z3\.b, z7\.b, z11\.b, z15\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1408010 ld1b {z16\.b, z20\.b, z24\.b, z28\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1408011 ld1b {z17\.b, z21\.b, z25\.b, z29\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1408012 ld1b {z18\.b, z22\.b, z26\.b, z30\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1408013 ld1b {z19\.b, z23\.b, z27\.b, z31\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1409c00 ld1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn15/z, \[x0\]
|
||||
[^:]+: a14083c0 ld1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x30\]
|
||||
[^:]+: a14083e0 ld1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[sp\]
|
||||
[^:]+: a1488000 ld1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x0, #-32, mul vl\]
|
||||
[^:]+: a1478000 ld1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x0, #28, mul vl\]
|
||||
[^:]+: a1429ba2 ld1b {z2\.b, z6\.b, z10\.b, z14\.b}, pn14/z, \[x29, #8, mul vl\]
|
||||
[^:]+: a0010000 ld1b {z0\.b-z1\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a0010000 ld1b {z0\.b-z1\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a0010000 ld1b {z0\.b-z1\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a001001e ld1b {z30\.b-z31\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a0011c00 ld1b {z0\.b-z1\.b}, pn15/z, \[x0, x1\]
|
||||
[^:]+: a00103c0 ld1b {z0\.b-z1\.b}, pn8/z, \[x30, x1\]
|
||||
[^:]+: a00103e0 ld1b {z0\.b-z1\.b}, pn8/z, \[sp, x1\]
|
||||
[^:]+: a01e0000 ld1b {z0\.b-z1\.b}, pn8/z, \[x0, x30\]
|
||||
[^:]+: a01f0000 ld1b {z0\.b-z1\.b}, pn8/z, \[x0, xzr\]
|
||||
[^:]+: a003074e ld1b {z14\.b-z15\.b}, pn9/z, \[x26, x3\]
|
||||
[^:]+: a0018000 ld1b {z0\.b-z3\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a0018000 ld1b {z0\.b-z3\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a0018000 ld1b {z0\.b-z3\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a001801c ld1b {z28\.b-z31\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a0019c00 ld1b {z0\.b-z3\.b}, pn15/z, \[x0, x1\]
|
||||
[^:]+: a00183c0 ld1b {z0\.b-z3\.b}, pn8/z, \[x30, x1\]
|
||||
[^:]+: a00183e0 ld1b {z0\.b-z3\.b}, pn8/z, \[sp, x1\]
|
||||
[^:]+: a01e8000 ld1b {z0\.b-z3\.b}, pn8/z, \[x0, x30\]
|
||||
[^:]+: a01f8000 ld1b {z0\.b-z3\.b}, pn8/z, \[x0, xzr\]
|
||||
[^:]+: a0018f68 ld1b {z8\.b-z11\.b}, pn11/z, \[x27, x1\]
|
||||
[^:]+: a1010000 ld1b {z0\.b, z8\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1010000 ld1b {z0\.b, z8\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1010000 ld1b {z0\.b, z8\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1010001 ld1b {z1\.b, z9\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1010002 ld1b {z2\.b, z10\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1010003 ld1b {z3\.b, z11\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1010004 ld1b {z4\.b, z12\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1010005 ld1b {z5\.b, z13\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1010006 ld1b {z6\.b, z14\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1010007 ld1b {z7\.b, z15\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1010010 ld1b {z16\.b, z24\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1010011 ld1b {z17\.b, z25\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1010012 ld1b {z18\.b, z26\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1010013 ld1b {z19\.b, z27\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1010014 ld1b {z20\.b, z28\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1010015 ld1b {z21\.b, z29\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1010016 ld1b {z22\.b, z30\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1010017 ld1b {z23\.b, z31\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1011c00 ld1b {z0\.b, z8\.b}, pn15/z, \[x0, x1\]
|
||||
[^:]+: a10103c0 ld1b {z0\.b, z8\.b}, pn8/z, \[x30, x1\]
|
||||
[^:]+: a10103e0 ld1b {z0\.b, z8\.b}, pn8/z, \[sp, x1\]
|
||||
[^:]+: a11e0000 ld1b {z0\.b, z8\.b}, pn8/z, \[x0, x30\]
|
||||
[^:]+: a11f0000 ld1b {z0\.b, z8\.b}, pn8/z, \[x0, xzr\]
|
||||
[^:]+: a11819e5 ld1b {z5\.b, z13\.b}, pn14/z, \[x15, x24\]
|
||||
[^:]+: a1018000 ld1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1018000 ld1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1018000 ld1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1018001 ld1b {z1\.b, z5\.b, z9\.b, z13\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1018002 ld1b {z2\.b, z6\.b, z10\.b, z14\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1018003 ld1b {z3\.b, z7\.b, z11\.b, z15\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1018010 ld1b {z16\.b, z20\.b, z24\.b, z28\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1018011 ld1b {z17\.b, z21\.b, z25\.b, z29\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1018012 ld1b {z18\.b, z22\.b, z26\.b, z30\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1018013 ld1b {z19\.b, z23\.b, z27\.b, z31\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1019c00 ld1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn15/z, \[x0, x1\]
|
||||
[^:]+: a10183c0 ld1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x30, x1\]
|
||||
[^:]+: a10183e0 ld1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[sp, x1\]
|
||||
[^:]+: a11e8000 ld1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x0, x30\]
|
||||
[^:]+: a11f8000 ld1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x0, xzr\]
|
||||
[^:]+: a1068c91 ld1b {z17\.b, z21\.b, z25\.b, z29\.b}, pn11/z, \[x4, x6\]
|
||||
[^:]+: a0400001 ldnt1b {z0\.b-z1\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a0400001 ldnt1b {z0\.b-z1\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a0400001 ldnt1b {z0\.b-z1\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a040001f ldnt1b {z30\.b-z31\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a0401c01 ldnt1b {z0\.b-z1\.b}, pn15/z, \[x0\]
|
||||
[^:]+: a04003c1 ldnt1b {z0\.b-z1\.b}, pn8/z, \[x30\]
|
||||
[^:]+: a04003e1 ldnt1b {z0\.b-z1\.b}, pn8/z, \[sp\]
|
||||
[^:]+: a0480001 ldnt1b {z0\.b-z1\.b}, pn8/z, \[x0, #-16, mul vl\]
|
||||
[^:]+: a0470001 ldnt1b {z0\.b-z1\.b}, pn8/z, \[x0, #14, mul vl\]
|
||||
[^:]+: a04b156d ldnt1b {z12\.b-z13\.b}, pn13/z, \[x11, #-10, mul vl\]
|
||||
[^:]+: a0408001 ldnt1b {z0\.b-z3\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a0408001 ldnt1b {z0\.b-z3\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a0408001 ldnt1b {z0\.b-z3\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a040801d ldnt1b {z28\.b-z31\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a0409c01 ldnt1b {z0\.b-z3\.b}, pn15/z, \[x0\]
|
||||
[^:]+: a04083c1 ldnt1b {z0\.b-z3\.b}, pn8/z, \[x30\]
|
||||
[^:]+: a04083e1 ldnt1b {z0\.b-z3\.b}, pn8/z, \[sp\]
|
||||
[^:]+: a0488001 ldnt1b {z0\.b-z3\.b}, pn8/z, \[x0, #-32, mul vl\]
|
||||
[^:]+: a0478001 ldnt1b {z0\.b-z3\.b}, pn8/z, \[x0, #28, mul vl\]
|
||||
[^:]+: a0458e29 ldnt1b {z8\.b-z11\.b}, pn11/z, \[x17, #20, mul vl\]
|
||||
[^:]+: a1400008 ldnt1b {z0\.b, z8\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1400008 ldnt1b {z0\.b, z8\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1400008 ldnt1b {z0\.b, z8\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1400009 ldnt1b {z1\.b, z9\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a140000a ldnt1b {z2\.b, z10\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a140000b ldnt1b {z3\.b, z11\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a140000c ldnt1b {z4\.b, z12\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a140000d ldnt1b {z5\.b, z13\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a140000e ldnt1b {z6\.b, z14\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a140000f ldnt1b {z7\.b, z15\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1400018 ldnt1b {z16\.b, z24\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1400019 ldnt1b {z17\.b, z25\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a140001a ldnt1b {z18\.b, z26\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a140001b ldnt1b {z19\.b, z27\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a140001c ldnt1b {z20\.b, z28\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a140001d ldnt1b {z21\.b, z29\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a140001e ldnt1b {z22\.b, z30\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a140001f ldnt1b {z23\.b, z31\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1401c08 ldnt1b {z0\.b, z8\.b}, pn15/z, \[x0\]
|
||||
[^:]+: a14003c8 ldnt1b {z0\.b, z8\.b}, pn8/z, \[x30\]
|
||||
[^:]+: a14003e8 ldnt1b {z0\.b, z8\.b}, pn8/z, \[sp\]
|
||||
[^:]+: a1480008 ldnt1b {z0\.b, z8\.b}, pn8/z, \[x0, #-16, mul vl\]
|
||||
[^:]+: a1470008 ldnt1b {z0\.b, z8\.b}, pn8/z, \[x0, #14, mul vl\]
|
||||
[^:]+: a1430acb ldnt1b {z3\.b, z11\.b}, pn10/z, \[x22, #6, mul vl\]
|
||||
[^:]+: a1408008 ldnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1408008 ldnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1408008 ldnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1408009 ldnt1b {z1\.b, z5\.b, z9\.b, z13\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a140800a ldnt1b {z2\.b, z6\.b, z10\.b, z14\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a140800b ldnt1b {z3\.b, z7\.b, z11\.b, z15\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1408018 ldnt1b {z16\.b, z20\.b, z24\.b, z28\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1408019 ldnt1b {z17\.b, z21\.b, z25\.b, z29\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a140801a ldnt1b {z18\.b, z22\.b, z26\.b, z30\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a140801b ldnt1b {z19\.b, z23\.b, z27\.b, z31\.b}, pn8/z, \[x0\]
|
||||
[^:]+: a1409c08 ldnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn15/z, \[x0\]
|
||||
[^:]+: a14083c8 ldnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x30\]
|
||||
[^:]+: a14083e8 ldnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[sp\]
|
||||
[^:]+: a1488008 ldnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x0, #-32, mul vl\]
|
||||
[^:]+: a1478008 ldnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x0, #28, mul vl\]
|
||||
[^:]+: a1429baa ldnt1b {z2\.b, z6\.b, z10\.b, z14\.b}, pn14/z, \[x29, #8, mul vl\]
|
||||
[^:]+: a0010001 ldnt1b {z0\.b-z1\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a0010001 ldnt1b {z0\.b-z1\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a0010001 ldnt1b {z0\.b-z1\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a001001f ldnt1b {z30\.b-z31\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a0011c01 ldnt1b {z0\.b-z1\.b}, pn15/z, \[x0, x1\]
|
||||
[^:]+: a00103c1 ldnt1b {z0\.b-z1\.b}, pn8/z, \[x30, x1\]
|
||||
[^:]+: a00103e1 ldnt1b {z0\.b-z1\.b}, pn8/z, \[sp, x1\]
|
||||
[^:]+: a01e0001 ldnt1b {z0\.b-z1\.b}, pn8/z, \[x0, x30\]
|
||||
[^:]+: a01f0001 ldnt1b {z0\.b-z1\.b}, pn8/z, \[x0, xzr\]
|
||||
[^:]+: a003074f ldnt1b {z14\.b-z15\.b}, pn9/z, \[x26, x3\]
|
||||
[^:]+: a0018001 ldnt1b {z0\.b-z3\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a0018001 ldnt1b {z0\.b-z3\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a0018001 ldnt1b {z0\.b-z3\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a001801d ldnt1b {z28\.b-z31\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a0019c01 ldnt1b {z0\.b-z3\.b}, pn15/z, \[x0, x1\]
|
||||
[^:]+: a00183c1 ldnt1b {z0\.b-z3\.b}, pn8/z, \[x30, x1\]
|
||||
[^:]+: a00183e1 ldnt1b {z0\.b-z3\.b}, pn8/z, \[sp, x1\]
|
||||
[^:]+: a01e8001 ldnt1b {z0\.b-z3\.b}, pn8/z, \[x0, x30\]
|
||||
[^:]+: a01f8001 ldnt1b {z0\.b-z3\.b}, pn8/z, \[x0, xzr\]
|
||||
[^:]+: a0018f69 ldnt1b {z8\.b-z11\.b}, pn11/z, \[x27, x1\]
|
||||
[^:]+: a1010008 ldnt1b {z0\.b, z8\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1010008 ldnt1b {z0\.b, z8\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1010008 ldnt1b {z0\.b, z8\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1010009 ldnt1b {z1\.b, z9\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a101000a ldnt1b {z2\.b, z10\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a101000b ldnt1b {z3\.b, z11\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a101000c ldnt1b {z4\.b, z12\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a101000d ldnt1b {z5\.b, z13\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a101000e ldnt1b {z6\.b, z14\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a101000f ldnt1b {z7\.b, z15\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1010018 ldnt1b {z16\.b, z24\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1010019 ldnt1b {z17\.b, z25\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a101001a ldnt1b {z18\.b, z26\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a101001b ldnt1b {z19\.b, z27\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a101001c ldnt1b {z20\.b, z28\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a101001d ldnt1b {z21\.b, z29\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a101001e ldnt1b {z22\.b, z30\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a101001f ldnt1b {z23\.b, z31\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1011c08 ldnt1b {z0\.b, z8\.b}, pn15/z, \[x0, x1\]
|
||||
[^:]+: a10103c8 ldnt1b {z0\.b, z8\.b}, pn8/z, \[x30, x1\]
|
||||
[^:]+: a10103e8 ldnt1b {z0\.b, z8\.b}, pn8/z, \[sp, x1\]
|
||||
[^:]+: a11e0008 ldnt1b {z0\.b, z8\.b}, pn8/z, \[x0, x30\]
|
||||
[^:]+: a11f0008 ldnt1b {z0\.b, z8\.b}, pn8/z, \[x0, xzr\]
|
||||
[^:]+: a11819ed ldnt1b {z5\.b, z13\.b}, pn14/z, \[x15, x24\]
|
||||
[^:]+: a1018008 ldnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1018008 ldnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1018008 ldnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1018009 ldnt1b {z1\.b, z5\.b, z9\.b, z13\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a101800a ldnt1b {z2\.b, z6\.b, z10\.b, z14\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a101800b ldnt1b {z3\.b, z7\.b, z11\.b, z15\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1018018 ldnt1b {z16\.b, z20\.b, z24\.b, z28\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1018019 ldnt1b {z17\.b, z21\.b, z25\.b, z29\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a101801a ldnt1b {z18\.b, z22\.b, z26\.b, z30\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a101801b ldnt1b {z19\.b, z23\.b, z27\.b, z31\.b}, pn8/z, \[x0, x1\]
|
||||
[^:]+: a1019c08 ldnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn15/z, \[x0, x1\]
|
||||
[^:]+: a10183c8 ldnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x30, x1\]
|
||||
[^:]+: a10183e8 ldnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[sp, x1\]
|
||||
[^:]+: a11e8008 ldnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x0, x30\]
|
||||
[^:]+: a11f8008 ldnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8/z, \[x0, xzr\]
|
||||
[^:]+: a1068c99 ldnt1b {z17\.b, z21\.b, z25\.b, z29\.b}, pn11/z, \[x4, x6\]
|
||||
[^:]+: a0600000 st1b {z0\.b-z1\.b}, pn8, \[x0\]
|
||||
[^:]+: a0600000 st1b {z0\.b-z1\.b}, pn8, \[x0\]
|
||||
[^:]+: a0600000 st1b {z0\.b-z1\.b}, pn8, \[x0\]
|
||||
[^:]+: a060001e st1b {z30\.b-z31\.b}, pn8, \[x0\]
|
||||
[^:]+: a0601c00 st1b {z0\.b-z1\.b}, pn15, \[x0\]
|
||||
[^:]+: a06003c0 st1b {z0\.b-z1\.b}, pn8, \[x30\]
|
||||
[^:]+: a06003e0 st1b {z0\.b-z1\.b}, pn8, \[sp\]
|
||||
[^:]+: a0680000 st1b {z0\.b-z1\.b}, pn8, \[x0, #-16, mul vl\]
|
||||
[^:]+: a0670000 st1b {z0\.b-z1\.b}, pn8, \[x0, #14, mul vl\]
|
||||
[^:]+: a06b156c st1b {z12\.b-z13\.b}, pn13, \[x11, #-10, mul vl\]
|
||||
[^:]+: a0608000 st1b {z0\.b-z3\.b}, pn8, \[x0\]
|
||||
[^:]+: a0608000 st1b {z0\.b-z3\.b}, pn8, \[x0\]
|
||||
[^:]+: a0608000 st1b {z0\.b-z3\.b}, pn8, \[x0\]
|
||||
[^:]+: a060801c st1b {z28\.b-z31\.b}, pn8, \[x0\]
|
||||
[^:]+: a0609c00 st1b {z0\.b-z3\.b}, pn15, \[x0\]
|
||||
[^:]+: a06083c0 st1b {z0\.b-z3\.b}, pn8, \[x30\]
|
||||
[^:]+: a06083e0 st1b {z0\.b-z3\.b}, pn8, \[sp\]
|
||||
[^:]+: a0688000 st1b {z0\.b-z3\.b}, pn8, \[x0, #-32, mul vl\]
|
||||
[^:]+: a0678000 st1b {z0\.b-z3\.b}, pn8, \[x0, #28, mul vl\]
|
||||
[^:]+: a0658e28 st1b {z8\.b-z11\.b}, pn11, \[x17, #20, mul vl\]
|
||||
[^:]+: a1600000 st1b {z0\.b, z8\.b}, pn8, \[x0\]
|
||||
[^:]+: a1600000 st1b {z0\.b, z8\.b}, pn8, \[x0\]
|
||||
[^:]+: a1600000 st1b {z0\.b, z8\.b}, pn8, \[x0\]
|
||||
[^:]+: a1600001 st1b {z1\.b, z9\.b}, pn8, \[x0\]
|
||||
[^:]+: a1600002 st1b {z2\.b, z10\.b}, pn8, \[x0\]
|
||||
[^:]+: a1600003 st1b {z3\.b, z11\.b}, pn8, \[x0\]
|
||||
[^:]+: a1600004 st1b {z4\.b, z12\.b}, pn8, \[x0\]
|
||||
[^:]+: a1600005 st1b {z5\.b, z13\.b}, pn8, \[x0\]
|
||||
[^:]+: a1600006 st1b {z6\.b, z14\.b}, pn8, \[x0\]
|
||||
[^:]+: a1600007 st1b {z7\.b, z15\.b}, pn8, \[x0\]
|
||||
[^:]+: a1600010 st1b {z16\.b, z24\.b}, pn8, \[x0\]
|
||||
[^:]+: a1600011 st1b {z17\.b, z25\.b}, pn8, \[x0\]
|
||||
[^:]+: a1600012 st1b {z18\.b, z26\.b}, pn8, \[x0\]
|
||||
[^:]+: a1600013 st1b {z19\.b, z27\.b}, pn8, \[x0\]
|
||||
[^:]+: a1600014 st1b {z20\.b, z28\.b}, pn8, \[x0\]
|
||||
[^:]+: a1600015 st1b {z21\.b, z29\.b}, pn8, \[x0\]
|
||||
[^:]+: a1600016 st1b {z22\.b, z30\.b}, pn8, \[x0\]
|
||||
[^:]+: a1600017 st1b {z23\.b, z31\.b}, pn8, \[x0\]
|
||||
[^:]+: a1601c00 st1b {z0\.b, z8\.b}, pn15, \[x0\]
|
||||
[^:]+: a16003c0 st1b {z0\.b, z8\.b}, pn8, \[x30\]
|
||||
[^:]+: a16003e0 st1b {z0\.b, z8\.b}, pn8, \[sp\]
|
||||
[^:]+: a1680000 st1b {z0\.b, z8\.b}, pn8, \[x0, #-16, mul vl\]
|
||||
[^:]+: a1670000 st1b {z0\.b, z8\.b}, pn8, \[x0, #14, mul vl\]
|
||||
[^:]+: a1630ac3 st1b {z3\.b, z11\.b}, pn10, \[x22, #6, mul vl\]
|
||||
[^:]+: a1608000 st1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[x0\]
|
||||
[^:]+: a1608000 st1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[x0\]
|
||||
[^:]+: a1608000 st1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[x0\]
|
||||
[^:]+: a1608001 st1b {z1\.b, z5\.b, z9\.b, z13\.b}, pn8, \[x0\]
|
||||
[^:]+: a1608002 st1b {z2\.b, z6\.b, z10\.b, z14\.b}, pn8, \[x0\]
|
||||
[^:]+: a1608003 st1b {z3\.b, z7\.b, z11\.b, z15\.b}, pn8, \[x0\]
|
||||
[^:]+: a1608010 st1b {z16\.b, z20\.b, z24\.b, z28\.b}, pn8, \[x0\]
|
||||
[^:]+: a1608011 st1b {z17\.b, z21\.b, z25\.b, z29\.b}, pn8, \[x0\]
|
||||
[^:]+: a1608012 st1b {z18\.b, z22\.b, z26\.b, z30\.b}, pn8, \[x0\]
|
||||
[^:]+: a1608013 st1b {z19\.b, z23\.b, z27\.b, z31\.b}, pn8, \[x0\]
|
||||
[^:]+: a1609c00 st1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn15, \[x0\]
|
||||
[^:]+: a16083c0 st1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[x30\]
|
||||
[^:]+: a16083e0 st1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[sp\]
|
||||
[^:]+: a1688000 st1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[x0, #-32, mul vl\]
|
||||
[^:]+: a1678000 st1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[x0, #28, mul vl\]
|
||||
[^:]+: a1629ba2 st1b {z2\.b, z6\.b, z10\.b, z14\.b}, pn14, \[x29, #8, mul vl\]
|
||||
[^:]+: a0210000 st1b {z0\.b-z1\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a0210000 st1b {z0\.b-z1\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a0210000 st1b {z0\.b-z1\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a021001e st1b {z30\.b-z31\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a0211c00 st1b {z0\.b-z1\.b}, pn15, \[x0, x1\]
|
||||
[^:]+: a02103c0 st1b {z0\.b-z1\.b}, pn8, \[x30, x1\]
|
||||
[^:]+: a02103e0 st1b {z0\.b-z1\.b}, pn8, \[sp, x1\]
|
||||
[^:]+: a03e0000 st1b {z0\.b-z1\.b}, pn8, \[x0, x30\]
|
||||
[^:]+: a03f0000 st1b {z0\.b-z1\.b}, pn8, \[x0, xzr\]
|
||||
[^:]+: a023074e st1b {z14\.b-z15\.b}, pn9, \[x26, x3\]
|
||||
[^:]+: a0218000 st1b {z0\.b-z3\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a0218000 st1b {z0\.b-z3\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a0218000 st1b {z0\.b-z3\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a021801c st1b {z28\.b-z31\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a0219c00 st1b {z0\.b-z3\.b}, pn15, \[x0, x1\]
|
||||
[^:]+: a02183c0 st1b {z0\.b-z3\.b}, pn8, \[x30, x1\]
|
||||
[^:]+: a02183e0 st1b {z0\.b-z3\.b}, pn8, \[sp, x1\]
|
||||
[^:]+: a03e8000 st1b {z0\.b-z3\.b}, pn8, \[x0, x30\]
|
||||
[^:]+: a03f8000 st1b {z0\.b-z3\.b}, pn8, \[x0, xzr\]
|
||||
[^:]+: a0218f68 st1b {z8\.b-z11\.b}, pn11, \[x27, x1\]
|
||||
[^:]+: a1210000 st1b {z0\.b, z8\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a1210000 st1b {z0\.b, z8\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a1210000 st1b {z0\.b, z8\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a1210001 st1b {z1\.b, z9\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a1210002 st1b {z2\.b, z10\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a1210003 st1b {z3\.b, z11\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a1210004 st1b {z4\.b, z12\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a1210005 st1b {z5\.b, z13\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a1210006 st1b {z6\.b, z14\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a1210007 st1b {z7\.b, z15\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a1210010 st1b {z16\.b, z24\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a1210011 st1b {z17\.b, z25\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a1210012 st1b {z18\.b, z26\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a1210013 st1b {z19\.b, z27\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a1210014 st1b {z20\.b, z28\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a1210015 st1b {z21\.b, z29\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a1210016 st1b {z22\.b, z30\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a1210017 st1b {z23\.b, z31\.b}, pn8, \[x0, x1\]
|
||||
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|
||||
[^:]+: a12103c0 st1b {z0\.b, z8\.b}, pn8, \[x30, x1\]
|
||||
[^:]+: a12103e0 st1b {z0\.b, z8\.b}, pn8, \[sp, x1\]
|
||||
[^:]+: a13e0000 st1b {z0\.b, z8\.b}, pn8, \[x0, x30\]
|
||||
[^:]+: a13f0000 st1b {z0\.b, z8\.b}, pn8, \[x0, xzr\]
|
||||
[^:]+: a13819e5 st1b {z5\.b, z13\.b}, pn14, \[x15, x24\]
|
||||
[^:]+: a1218000 st1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a1218000 st1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a1218000 st1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a1218001 st1b {z1\.b, z5\.b, z9\.b, z13\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a1218002 st1b {z2\.b, z6\.b, z10\.b, z14\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a1218003 st1b {z3\.b, z7\.b, z11\.b, z15\.b}, pn8, \[x0, x1\]
|
||||
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|
||||
[^:]+: a1218011 st1b {z17\.b, z21\.b, z25\.b, z29\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a1218012 st1b {z18\.b, z22\.b, z26\.b, z30\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a1218013 st1b {z19\.b, z23\.b, z27\.b, z31\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a1219c00 st1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn15, \[x0, x1\]
|
||||
[^:]+: a12183c0 st1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[x30, x1\]
|
||||
[^:]+: a12183e0 st1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[sp, x1\]
|
||||
[^:]+: a13e8000 st1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[x0, x30\]
|
||||
[^:]+: a13f8000 st1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[x0, xzr\]
|
||||
[^:]+: a1268c91 st1b {z17\.b, z21\.b, z25\.b, z29\.b}, pn11, \[x4, x6\]
|
||||
[^:]+: a0600001 stnt1b {z0\.b-z1\.b}, pn8, \[x0\]
|
||||
[^:]+: a0600001 stnt1b {z0\.b-z1\.b}, pn8, \[x0\]
|
||||
[^:]+: a0600001 stnt1b {z0\.b-z1\.b}, pn8, \[x0\]
|
||||
[^:]+: a060001f stnt1b {z30\.b-z31\.b}, pn8, \[x0\]
|
||||
[^:]+: a0601c01 stnt1b {z0\.b-z1\.b}, pn15, \[x0\]
|
||||
[^:]+: a06003c1 stnt1b {z0\.b-z1\.b}, pn8, \[x30\]
|
||||
[^:]+: a06003e1 stnt1b {z0\.b-z1\.b}, pn8, \[sp\]
|
||||
[^:]+: a0680001 stnt1b {z0\.b-z1\.b}, pn8, \[x0, #-16, mul vl\]
|
||||
[^:]+: a0670001 stnt1b {z0\.b-z1\.b}, pn8, \[x0, #14, mul vl\]
|
||||
[^:]+: a06b156d stnt1b {z12\.b-z13\.b}, pn13, \[x11, #-10, mul vl\]
|
||||
[^:]+: a0608001 stnt1b {z0\.b-z3\.b}, pn8, \[x0\]
|
||||
[^:]+: a0608001 stnt1b {z0\.b-z3\.b}, pn8, \[x0\]
|
||||
[^:]+: a0608001 stnt1b {z0\.b-z3\.b}, pn8, \[x0\]
|
||||
[^:]+: a060801d stnt1b {z28\.b-z31\.b}, pn8, \[x0\]
|
||||
[^:]+: a0609c01 stnt1b {z0\.b-z3\.b}, pn15, \[x0\]
|
||||
[^:]+: a06083c1 stnt1b {z0\.b-z3\.b}, pn8, \[x30\]
|
||||
[^:]+: a06083e1 stnt1b {z0\.b-z3\.b}, pn8, \[sp\]
|
||||
[^:]+: a0688001 stnt1b {z0\.b-z3\.b}, pn8, \[x0, #-32, mul vl\]
|
||||
[^:]+: a0678001 stnt1b {z0\.b-z3\.b}, pn8, \[x0, #28, mul vl\]
|
||||
[^:]+: a0658e29 stnt1b {z8\.b-z11\.b}, pn11, \[x17, #20, mul vl\]
|
||||
[^:]+: a1600008 stnt1b {z0\.b, z8\.b}, pn8, \[x0\]
|
||||
[^:]+: a1600008 stnt1b {z0\.b, z8\.b}, pn8, \[x0\]
|
||||
[^:]+: a1600008 stnt1b {z0\.b, z8\.b}, pn8, \[x0\]
|
||||
[^:]+: a1600009 stnt1b {z1\.b, z9\.b}, pn8, \[x0\]
|
||||
[^:]+: a160000a stnt1b {z2\.b, z10\.b}, pn8, \[x0\]
|
||||
[^:]+: a160000b stnt1b {z3\.b, z11\.b}, pn8, \[x0\]
|
||||
[^:]+: a160000c stnt1b {z4\.b, z12\.b}, pn8, \[x0\]
|
||||
[^:]+: a160000d stnt1b {z5\.b, z13\.b}, pn8, \[x0\]
|
||||
[^:]+: a160000e stnt1b {z6\.b, z14\.b}, pn8, \[x0\]
|
||||
[^:]+: a160000f stnt1b {z7\.b, z15\.b}, pn8, \[x0\]
|
||||
[^:]+: a1600018 stnt1b {z16\.b, z24\.b}, pn8, \[x0\]
|
||||
[^:]+: a1600019 stnt1b {z17\.b, z25\.b}, pn8, \[x0\]
|
||||
[^:]+: a160001a stnt1b {z18\.b, z26\.b}, pn8, \[x0\]
|
||||
[^:]+: a160001b stnt1b {z19\.b, z27\.b}, pn8, \[x0\]
|
||||
[^:]+: a160001c stnt1b {z20\.b, z28\.b}, pn8, \[x0\]
|
||||
[^:]+: a160001d stnt1b {z21\.b, z29\.b}, pn8, \[x0\]
|
||||
[^:]+: a160001e stnt1b {z22\.b, z30\.b}, pn8, \[x0\]
|
||||
[^:]+: a160001f stnt1b {z23\.b, z31\.b}, pn8, \[x0\]
|
||||
[^:]+: a1601c08 stnt1b {z0\.b, z8\.b}, pn15, \[x0\]
|
||||
[^:]+: a16003c8 stnt1b {z0\.b, z8\.b}, pn8, \[x30\]
|
||||
[^:]+: a16003e8 stnt1b {z0\.b, z8\.b}, pn8, \[sp\]
|
||||
[^:]+: a1680008 stnt1b {z0\.b, z8\.b}, pn8, \[x0, #-16, mul vl\]
|
||||
[^:]+: a1670008 stnt1b {z0\.b, z8\.b}, pn8, \[x0, #14, mul vl\]
|
||||
[^:]+: a1630acb stnt1b {z3\.b, z11\.b}, pn10, \[x22, #6, mul vl\]
|
||||
[^:]+: a1608008 stnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[x0\]
|
||||
[^:]+: a1608008 stnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[x0\]
|
||||
[^:]+: a1608008 stnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[x0\]
|
||||
[^:]+: a1608009 stnt1b {z1\.b, z5\.b, z9\.b, z13\.b}, pn8, \[x0\]
|
||||
[^:]+: a160800a stnt1b {z2\.b, z6\.b, z10\.b, z14\.b}, pn8, \[x0\]
|
||||
[^:]+: a160800b stnt1b {z3\.b, z7\.b, z11\.b, z15\.b}, pn8, \[x0\]
|
||||
[^:]+: a1608018 stnt1b {z16\.b, z20\.b, z24\.b, z28\.b}, pn8, \[x0\]
|
||||
[^:]+: a1608019 stnt1b {z17\.b, z21\.b, z25\.b, z29\.b}, pn8, \[x0\]
|
||||
[^:]+: a160801a stnt1b {z18\.b, z22\.b, z26\.b, z30\.b}, pn8, \[x0\]
|
||||
[^:]+: a160801b stnt1b {z19\.b, z23\.b, z27\.b, z31\.b}, pn8, \[x0\]
|
||||
[^:]+: a1609c08 stnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn15, \[x0\]
|
||||
[^:]+: a16083c8 stnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[x30\]
|
||||
[^:]+: a16083e8 stnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[sp\]
|
||||
[^:]+: a1688008 stnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[x0, #-32, mul vl\]
|
||||
[^:]+: a1678008 stnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[x0, #28, mul vl\]
|
||||
[^:]+: a1629baa stnt1b {z2\.b, z6\.b, z10\.b, z14\.b}, pn14, \[x29, #8, mul vl\]
|
||||
[^:]+: a0210001 stnt1b {z0\.b-z1\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a0210001 stnt1b {z0\.b-z1\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a0210001 stnt1b {z0\.b-z1\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a021001f stnt1b {z30\.b-z31\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a0211c01 stnt1b {z0\.b-z1\.b}, pn15, \[x0, x1\]
|
||||
[^:]+: a02103c1 stnt1b {z0\.b-z1\.b}, pn8, \[x30, x1\]
|
||||
[^:]+: a02103e1 stnt1b {z0\.b-z1\.b}, pn8, \[sp, x1\]
|
||||
[^:]+: a03e0001 stnt1b {z0\.b-z1\.b}, pn8, \[x0, x30\]
|
||||
[^:]+: a03f0001 stnt1b {z0\.b-z1\.b}, pn8, \[x0, xzr\]
|
||||
[^:]+: a023074f stnt1b {z14\.b-z15\.b}, pn9, \[x26, x3\]
|
||||
[^:]+: a0218001 stnt1b {z0\.b-z3\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a0218001 stnt1b {z0\.b-z3\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a0218001 stnt1b {z0\.b-z3\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a021801d stnt1b {z28\.b-z31\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a0219c01 stnt1b {z0\.b-z3\.b}, pn15, \[x0, x1\]
|
||||
[^:]+: a02183c1 stnt1b {z0\.b-z3\.b}, pn8, \[x30, x1\]
|
||||
[^:]+: a02183e1 stnt1b {z0\.b-z3\.b}, pn8, \[sp, x1\]
|
||||
[^:]+: a03e8001 stnt1b {z0\.b-z3\.b}, pn8, \[x0, x30\]
|
||||
[^:]+: a03f8001 stnt1b {z0\.b-z3\.b}, pn8, \[x0, xzr\]
|
||||
[^:]+: a0218f69 stnt1b {z8\.b-z11\.b}, pn11, \[x27, x1\]
|
||||
[^:]+: a1210008 stnt1b {z0\.b, z8\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a1210008 stnt1b {z0\.b, z8\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a1210008 stnt1b {z0\.b, z8\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a1210009 stnt1b {z1\.b, z9\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a121000a stnt1b {z2\.b, z10\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a121000b stnt1b {z3\.b, z11\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a121000c stnt1b {z4\.b, z12\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a121000d stnt1b {z5\.b, z13\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a121000e stnt1b {z6\.b, z14\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a121000f stnt1b {z7\.b, z15\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a1210018 stnt1b {z16\.b, z24\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a1210019 stnt1b {z17\.b, z25\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a121001a stnt1b {z18\.b, z26\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a121001b stnt1b {z19\.b, z27\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a121001c stnt1b {z20\.b, z28\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a121001d stnt1b {z21\.b, z29\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a121001e stnt1b {z22\.b, z30\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a121001f stnt1b {z23\.b, z31\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a1211c08 stnt1b {z0\.b, z8\.b}, pn15, \[x0, x1\]
|
||||
[^:]+: a12103c8 stnt1b {z0\.b, z8\.b}, pn8, \[x30, x1\]
|
||||
[^:]+: a12103e8 stnt1b {z0\.b, z8\.b}, pn8, \[sp, x1\]
|
||||
[^:]+: a13e0008 stnt1b {z0\.b, z8\.b}, pn8, \[x0, x30\]
|
||||
[^:]+: a13f0008 stnt1b {z0\.b, z8\.b}, pn8, \[x0, xzr\]
|
||||
[^:]+: a13819ed stnt1b {z5\.b, z13\.b}, pn14, \[x15, x24\]
|
||||
[^:]+: a1218008 stnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a1218008 stnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a1218008 stnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a1218009 stnt1b {z1\.b, z5\.b, z9\.b, z13\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a121800a stnt1b {z2\.b, z6\.b, z10\.b, z14\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a121800b stnt1b {z3\.b, z7\.b, z11\.b, z15\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a1218018 stnt1b {z16\.b, z20\.b, z24\.b, z28\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a1218019 stnt1b {z17\.b, z21\.b, z25\.b, z29\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a121801a stnt1b {z18\.b, z22\.b, z26\.b, z30\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a121801b stnt1b {z19\.b, z23\.b, z27\.b, z31\.b}, pn8, \[x0, x1\]
|
||||
[^:]+: a1219c08 stnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn15, \[x0, x1\]
|
||||
[^:]+: a12183c8 stnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[x30, x1\]
|
||||
[^:]+: a12183e8 stnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[sp, x1\]
|
||||
[^:]+: a13e8008 stnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[x0, x30\]
|
||||
[^:]+: a13f8008 stnt1b {z0\.b, z4\.b, z8\.b, z12\.b}, pn8, \[x0, xzr\]
|
||||
[^:]+: a1268c99 stnt1b {z17\.b, z21\.b, z25\.b, z29\.b}, pn11, \[x4, x6\]
|
||||
511
gas/testsuite/gas/aarch64/sme2-2.s
Normal file
511
gas/testsuite/gas/aarch64/sme2-2.s
Normal file
@ -0,0 +1,511 @@
|
||||
ld1b { z0.b - z1.b }, pn8/z, [x0]
|
||||
ld1b { z0.b - z1.b }, pn8/z, [x0, #0, mul vl]
|
||||
LD1B { Z0.B - Z1.B }, PN8/Z, [X0]
|
||||
ld1b { z30.b - z31.b }, pn8/z, [x0]
|
||||
ld1b { z0.b - z1.b }, pn15/z, [x0]
|
||||
ld1b { z0.b - z1.b }, pn8/z, [x30]
|
||||
ld1b { z0.b - z1.b }, pn8/z, [sp]
|
||||
ld1b { z0.b - z1.b }, pn8/z, [x0, #-16, mul vl]
|
||||
ld1b { z0.b - z1.b }, pn8/z, [x0, #14, mul vl]
|
||||
ld1b { z12.b - z13.b }, pn13/z, [x11, #-10, mul vl]
|
||||
|
||||
ld1b { z0.b - z3.b }, pn8/z, [x0]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [x0, #0, mul vl]
|
||||
LD1B { Z0.B - Z3.B }, PN8/Z, [X0]
|
||||
ld1b { z28.b - z31.b }, pn8/z, [x0]
|
||||
ld1b { z0.b - z3.b }, pn15/z, [x0]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [x30]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [sp]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [x0, #-32, mul vl]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [x0, #28, mul vl]
|
||||
ld1b { z8.b - z11.b }, pn11/z, [x17, #20, mul vl]
|
||||
|
||||
ld1b { z0.b, z8.b }, pn8/z, [x0]
|
||||
ld1b { z0.b, z8.b }, pn8/z, [x0, #0, mul vl]
|
||||
LD1B { Z0.B, Z8.B }, PN8/Z, [X0]
|
||||
ld1b { z1.b, z9.b }, pn8/z, [x0]
|
||||
ld1b { z2.b, z10.b }, pn8/z, [x0]
|
||||
ld1b { z3.b, z11.b }, pn8/z, [x0]
|
||||
ld1b { z4.b, z12.b }, pn8/z, [x0]
|
||||
ld1b { z5.b, z13.b }, pn8/z, [x0]
|
||||
ld1b { z6.b, z14.b }, pn8/z, [x0]
|
||||
ld1b { z7.b, z15.b }, pn8/z, [x0]
|
||||
ld1b { z16.b, z24.b }, pn8/z, [x0]
|
||||
ld1b { z17.b, z25.b }, pn8/z, [x0]
|
||||
ld1b { z18.b, z26.b }, pn8/z, [x0]
|
||||
ld1b { z19.b, z27.b }, pn8/z, [x0]
|
||||
ld1b { z20.b, z28.b }, pn8/z, [x0]
|
||||
ld1b { z21.b, z29.b }, pn8/z, [x0]
|
||||
ld1b { z22.b, z30.b }, pn8/z, [x0]
|
||||
ld1b { z23.b, z31.b }, pn8/z, [x0]
|
||||
ld1b { z0.b, z8.b }, pn15/z, [x0]
|
||||
ld1b { z0.b, z8.b }, pn8/z, [x30]
|
||||
ld1b { z0.b, z8.b }, pn8/z, [sp]
|
||||
ld1b { z0.b, z8.b }, pn8/z, [x0, #-16, mul vl]
|
||||
ld1b { z0.b, z8.b }, pn8/z, [x0, #14, mul vl]
|
||||
ld1b { z3.b, z11.b }, pn10/z, [x22, #6, mul vl]
|
||||
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0]
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #0, mul vl]
|
||||
LD1B { Z0.B, Z4.B, Z8.B, Z12.B }, PN8/Z, [X0]
|
||||
ld1b { z1.b, z5.b, z9.b, z13.b }, pn8/z, [x0]
|
||||
ld1b { z2.b, z6.b, z10.b, z14.b }, pn8/z, [x0]
|
||||
ld1b { z3.b, z7.b, z11.b, z15.b }, pn8/z, [x0]
|
||||
ld1b { z16.b, z20.b, z24.b, z28.b }, pn8/z, [x0]
|
||||
ld1b { z17.b, z21.b, z25.b, z29.b }, pn8/z, [x0]
|
||||
ld1b { z18.b, z22.b, z26.b, z30.b }, pn8/z, [x0]
|
||||
ld1b { z19.b, z23.b, z27.b, z31.b }, pn8/z, [x0]
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, pn15/z, [x0]
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x30]
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [sp]
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #-32, mul vl]
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #28, mul vl]
|
||||
ld1b { z2.b, z6.b, z10.b, z14.b }, pn14/z, [x29, #8, mul vl]
|
||||
|
||||
ld1b { z0.b - z1.b }, pn8/z, [x0, x1]
|
||||
ld1b { z0.b - z1.b }, pn8/z, [x0, x1, lsl #0]
|
||||
LD1B { Z0.B - Z1.B }, PN8/Z, [X0, X1]
|
||||
ld1b { z30.b - z31.b }, pn8/z, [x0, x1]
|
||||
ld1b { z0.b - z1.b }, pn15/z, [x0, x1]
|
||||
ld1b { z0.b - z1.b }, pn8/z, [x30, x1]
|
||||
ld1b { z0.b - z1.b }, pn8/z, [sp, x1]
|
||||
ld1b { z0.b - z1.b }, pn8/z, [x0, x30]
|
||||
ld1b { z0.b - z1.b }, pn8/z, [x0, xzr]
|
||||
ld1b { z14.b - z15.b }, pn9/z, [x26, x3]
|
||||
|
||||
ld1b { z0.b - z3.b }, pn8/z, [x0, x1]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [x0, x1, lsl #0]
|
||||
LD1B { Z0.B - Z3.B }, PN8/Z, [X0, X1]
|
||||
ld1b { z28.b - z31.b }, pn8/z, [x0, x1]
|
||||
ld1b { z0.b - z3.b }, pn15/z, [x0, x1]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [x30, x1]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [sp, x1]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [x0, x30]
|
||||
ld1b { z0.b - z3.b }, pn8/z, [x0, xzr]
|
||||
ld1b { z8.b - z11.b }, pn11/z, [x27, x1]
|
||||
|
||||
ld1b { z0.b, z8.b }, pn8/z, [x0, x1]
|
||||
ld1b { z0.b, z8.b }, pn8/z, [x0, x1, lsl #0]
|
||||
LD1B { Z0.B, Z8.B }, PN8/Z, [X0, X1]
|
||||
ld1b { z1.b, z9.b }, pn8/z, [x0, x1]
|
||||
ld1b { z2.b, z10.b }, pn8/z, [x0, x1]
|
||||
ld1b { z3.b, z11.b }, pn8/z, [x0, x1]
|
||||
ld1b { z4.b, z12.b }, pn8/z, [x0, x1]
|
||||
ld1b { z5.b, z13.b }, pn8/z, [x0, x1]
|
||||
ld1b { z6.b, z14.b }, pn8/z, [x0, x1]
|
||||
ld1b { z7.b, z15.b }, pn8/z, [x0, x1]
|
||||
ld1b { z16.b, z24.b }, pn8/z, [x0, x1]
|
||||
ld1b { z17.b, z25.b }, pn8/z, [x0, x1]
|
||||
ld1b { z18.b, z26.b }, pn8/z, [x0, x1]
|
||||
ld1b { z19.b, z27.b }, pn8/z, [x0, x1]
|
||||
ld1b { z20.b, z28.b }, pn8/z, [x0, x1]
|
||||
ld1b { z21.b, z29.b }, pn8/z, [x0, x1]
|
||||
ld1b { z22.b, z30.b }, pn8/z, [x0, x1]
|
||||
ld1b { z23.b, z31.b }, pn8/z, [x0, x1]
|
||||
ld1b { z0.b, z8.b }, pn15/z, [x0, x1]
|
||||
ld1b { z0.b, z8.b }, pn8/z, [x30, x1]
|
||||
ld1b { z0.b, z8.b }, pn8/z, [sp, x1]
|
||||
ld1b { z0.b, z8.b }, pn8/z, [x0, x30]
|
||||
ld1b { z0.b, z8.b }, pn8/z, [x0, xzr]
|
||||
ld1b { z5.b, z13.b }, pn14/z, [x15, x24]
|
||||
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, x1]
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, x1, lsl #0]
|
||||
LD1B { Z0.B, Z4.B, Z8.B, Z12.B }, PN8/Z, [X0, X1]
|
||||
ld1b { z1.b, z5.b, z9.b, z13.b }, pn8/z, [x0, x1]
|
||||
ld1b { z2.b, z6.b, z10.b, z14.b }, pn8/z, [x0, x1]
|
||||
ld1b { z3.b, z7.b, z11.b, z15.b }, pn8/z, [x0, x1]
|
||||
ld1b { z16.b, z20.b, z24.b, z28.b }, pn8/z, [x0, x1]
|
||||
ld1b { z17.b, z21.b, z25.b, z29.b }, pn8/z, [x0, x1]
|
||||
ld1b { z18.b, z22.b, z26.b, z30.b }, pn8/z, [x0, x1]
|
||||
ld1b { z19.b, z23.b, z27.b, z31.b }, pn8/z, [x0, x1]
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, pn15/z, [x0, x1]
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x30, x1]
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [sp, x1]
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, x30]
|
||||
ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, xzr]
|
||||
ld1b { z17.b, z21.b, z25.b, z29.b }, pn11/z, [x4, x6]
|
||||
|
||||
ldnt1b { z0.b - z1.b }, pn8/z, [x0]
|
||||
ldnt1b { z0.b - z1.b }, pn8/z, [x0, #0, mul vl]
|
||||
LDNT1B { Z0.B - Z1.B }, PN8/Z, [X0]
|
||||
ldnt1b { z30.b - z31.b }, pn8/z, [x0]
|
||||
ldnt1b { z0.b - z1.b }, pn15/z, [x0]
|
||||
ldnt1b { z0.b - z1.b }, pn8/z, [x30]
|
||||
ldnt1b { z0.b - z1.b }, pn8/z, [sp]
|
||||
ldnt1b { z0.b - z1.b }, pn8/z, [x0, #-16, mul vl]
|
||||
ldnt1b { z0.b - z1.b }, pn8/z, [x0, #14, mul vl]
|
||||
ldnt1b { z12.b - z13.b }, pn13/z, [x11, #-10, mul vl]
|
||||
|
||||
ldnt1b { z0.b - z3.b }, pn8/z, [x0]
|
||||
ldnt1b { z0.b - z3.b }, pn8/z, [x0, #0, mul vl]
|
||||
LDNT1B { Z0.B - Z3.B }, PN8/Z, [X0]
|
||||
ldnt1b { z28.b - z31.b }, pn8/z, [x0]
|
||||
ldnt1b { z0.b - z3.b }, pn15/z, [x0]
|
||||
ldnt1b { z0.b - z3.b }, pn8/z, [x30]
|
||||
ldnt1b { z0.b - z3.b }, pn8/z, [sp]
|
||||
ldnt1b { z0.b - z3.b }, pn8/z, [x0, #-32, mul vl]
|
||||
ldnt1b { z0.b - z3.b }, pn8/z, [x0, #28, mul vl]
|
||||
ldnt1b { z8.b - z11.b }, pn11/z, [x17, #20, mul vl]
|
||||
|
||||
ldnt1b { z0.b, z8.b }, pn8/z, [x0]
|
||||
ldnt1b { z0.b, z8.b }, pn8/z, [x0, #0, mul vl]
|
||||
LDNT1B { Z0.B, Z8.B }, PN8/Z, [X0]
|
||||
ldnt1b { z1.b, z9.b }, pn8/z, [x0]
|
||||
ldnt1b { z2.b, z10.b }, pn8/z, [x0]
|
||||
ldnt1b { z3.b, z11.b }, pn8/z, [x0]
|
||||
ldnt1b { z4.b, z12.b }, pn8/z, [x0]
|
||||
ldnt1b { z5.b, z13.b }, pn8/z, [x0]
|
||||
ldnt1b { z6.b, z14.b }, pn8/z, [x0]
|
||||
ldnt1b { z7.b, z15.b }, pn8/z, [x0]
|
||||
ldnt1b { z16.b, z24.b }, pn8/z, [x0]
|
||||
ldnt1b { z17.b, z25.b }, pn8/z, [x0]
|
||||
ldnt1b { z18.b, z26.b }, pn8/z, [x0]
|
||||
ldnt1b { z19.b, z27.b }, pn8/z, [x0]
|
||||
ldnt1b { z20.b, z28.b }, pn8/z, [x0]
|
||||
ldnt1b { z21.b, z29.b }, pn8/z, [x0]
|
||||
ldnt1b { z22.b, z30.b }, pn8/z, [x0]
|
||||
ldnt1b { z23.b, z31.b }, pn8/z, [x0]
|
||||
ldnt1b { z0.b, z8.b }, pn15/z, [x0]
|
||||
ldnt1b { z0.b, z8.b }, pn8/z, [x30]
|
||||
ldnt1b { z0.b, z8.b }, pn8/z, [sp]
|
||||
ldnt1b { z0.b, z8.b }, pn8/z, [x0, #-16, mul vl]
|
||||
ldnt1b { z0.b, z8.b }, pn8/z, [x0, #14, mul vl]
|
||||
ldnt1b { z3.b, z11.b }, pn10/z, [x22, #6, mul vl]
|
||||
|
||||
ldnt1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0]
|
||||
ldnt1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #0, mul vl]
|
||||
LDNT1B { Z0.B, Z4.B, Z8.B, Z12.B }, PN8/Z, [X0]
|
||||
ldnt1b { z1.b, z5.b, z9.b, z13.b }, pn8/z, [x0]
|
||||
ldnt1b { z2.b, z6.b, z10.b, z14.b }, pn8/z, [x0]
|
||||
ldnt1b { z3.b, z7.b, z11.b, z15.b }, pn8/z, [x0]
|
||||
ldnt1b { z16.b, z20.b, z24.b, z28.b }, pn8/z, [x0]
|
||||
ldnt1b { z17.b, z21.b, z25.b, z29.b }, pn8/z, [x0]
|
||||
ldnt1b { z18.b, z22.b, z26.b, z30.b }, pn8/z, [x0]
|
||||
ldnt1b { z19.b, z23.b, z27.b, z31.b }, pn8/z, [x0]
|
||||
ldnt1b { z0.b, z4.b, z8.b, z12.b }, pn15/z, [x0]
|
||||
ldnt1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x30]
|
||||
ldnt1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [sp]
|
||||
ldnt1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #-32, mul vl]
|
||||
ldnt1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, #28, mul vl]
|
||||
ldnt1b { z2.b, z6.b, z10.b, z14.b }, pn14/z, [x29, #8, mul vl]
|
||||
|
||||
ldnt1b { z0.b - z1.b }, pn8/z, [x0, x1]
|
||||
ldnt1b { z0.b - z1.b }, pn8/z, [x0, x1, lsl #0]
|
||||
LDNT1B { Z0.B - Z1.B }, PN8/Z, [X0, X1]
|
||||
ldnt1b { z30.b - z31.b }, pn8/z, [x0, x1]
|
||||
ldnt1b { z0.b - z1.b }, pn15/z, [x0, x1]
|
||||
ldnt1b { z0.b - z1.b }, pn8/z, [x30, x1]
|
||||
ldnt1b { z0.b - z1.b }, pn8/z, [sp, x1]
|
||||
ldnt1b { z0.b - z1.b }, pn8/z, [x0, x30]
|
||||
ldnt1b { z0.b - z1.b }, pn8/z, [x0, xzr]
|
||||
ldnt1b { z14.b - z15.b }, pn9/z, [x26, x3]
|
||||
|
||||
ldnt1b { z0.b - z3.b }, pn8/z, [x0, x1]
|
||||
ldnt1b { z0.b - z3.b }, pn8/z, [x0, x1, lsl #0]
|
||||
LDNT1B { Z0.B - Z3.B }, PN8/Z, [X0, X1]
|
||||
ldnt1b { z28.b - z31.b }, pn8/z, [x0, x1]
|
||||
ldnt1b { z0.b - z3.b }, pn15/z, [x0, x1]
|
||||
ldnt1b { z0.b - z3.b }, pn8/z, [x30, x1]
|
||||
ldnt1b { z0.b - z3.b }, pn8/z, [sp, x1]
|
||||
ldnt1b { z0.b - z3.b }, pn8/z, [x0, x30]
|
||||
ldnt1b { z0.b - z3.b }, pn8/z, [x0, xzr]
|
||||
ldnt1b { z8.b - z11.b }, pn11/z, [x27, x1]
|
||||
|
||||
ldnt1b { z0.b, z8.b }, pn8/z, [x0, x1]
|
||||
ldnt1b { z0.b, z8.b }, pn8/z, [x0, x1, lsl #0]
|
||||
LDNT1B { Z0.B, Z8.B }, PN8/Z, [X0, X1]
|
||||
ldnt1b { z1.b, z9.b }, pn8/z, [x0, x1]
|
||||
ldnt1b { z2.b, z10.b }, pn8/z, [x0, x1]
|
||||
ldnt1b { z3.b, z11.b }, pn8/z, [x0, x1]
|
||||
ldnt1b { z4.b, z12.b }, pn8/z, [x0, x1]
|
||||
ldnt1b { z5.b, z13.b }, pn8/z, [x0, x1]
|
||||
ldnt1b { z6.b, z14.b }, pn8/z, [x0, x1]
|
||||
ldnt1b { z7.b, z15.b }, pn8/z, [x0, x1]
|
||||
ldnt1b { z16.b, z24.b }, pn8/z, [x0, x1]
|
||||
ldnt1b { z17.b, z25.b }, pn8/z, [x0, x1]
|
||||
ldnt1b { z18.b, z26.b }, pn8/z, [x0, x1]
|
||||
ldnt1b { z19.b, z27.b }, pn8/z, [x0, x1]
|
||||
ldnt1b { z20.b, z28.b }, pn8/z, [x0, x1]
|
||||
ldnt1b { z21.b, z29.b }, pn8/z, [x0, x1]
|
||||
ldnt1b { z22.b, z30.b }, pn8/z, [x0, x1]
|
||||
ldnt1b { z23.b, z31.b }, pn8/z, [x0, x1]
|
||||
ldnt1b { z0.b, z8.b }, pn15/z, [x0, x1]
|
||||
ldnt1b { z0.b, z8.b }, pn8/z, [x30, x1]
|
||||
ldnt1b { z0.b, z8.b }, pn8/z, [sp, x1]
|
||||
ldnt1b { z0.b, z8.b }, pn8/z, [x0, x30]
|
||||
ldnt1b { z0.b, z8.b }, pn8/z, [x0, xzr]
|
||||
ldnt1b { z5.b, z13.b }, pn14/z, [x15, x24]
|
||||
|
||||
ldnt1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, x1]
|
||||
ldnt1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, x1, lsl #0]
|
||||
LDNT1B { Z0.B, Z4.B, Z8.B, Z12.B }, PN8/Z, [X0, X1]
|
||||
ldnt1b { z1.b, z5.b, z9.b, z13.b }, pn8/z, [x0, x1]
|
||||
ldnt1b { z2.b, z6.b, z10.b, z14.b }, pn8/z, [x0, x1]
|
||||
ldnt1b { z3.b, z7.b, z11.b, z15.b }, pn8/z, [x0, x1]
|
||||
ldnt1b { z16.b, z20.b, z24.b, z28.b }, pn8/z, [x0, x1]
|
||||
ldnt1b { z17.b, z21.b, z25.b, z29.b }, pn8/z, [x0, x1]
|
||||
ldnt1b { z18.b, z22.b, z26.b, z30.b }, pn8/z, [x0, x1]
|
||||
ldnt1b { z19.b, z23.b, z27.b, z31.b }, pn8/z, [x0, x1]
|
||||
ldnt1b { z0.b, z4.b, z8.b, z12.b }, pn15/z, [x0, x1]
|
||||
ldnt1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x30, x1]
|
||||
ldnt1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [sp, x1]
|
||||
ldnt1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, x30]
|
||||
ldnt1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, xzr]
|
||||
ldnt1b { z17.b, z21.b, z25.b, z29.b }, pn11/z, [x4, x6]
|
||||
|
||||
st1b { z0.b - z1.b }, pn8, [x0]
|
||||
st1b { z0.b - z1.b }, pn8, [x0, #0, mul vl]
|
||||
ST1B { Z0.B - Z1.B }, PN8, [X0]
|
||||
st1b { z30.b - z31.b }, pn8, [x0]
|
||||
st1b { z0.b - z1.b }, pn15, [x0]
|
||||
st1b { z0.b - z1.b }, pn8, [x30]
|
||||
st1b { z0.b - z1.b }, pn8, [sp]
|
||||
st1b { z0.b - z1.b }, pn8, [x0, #-16, mul vl]
|
||||
st1b { z0.b - z1.b }, pn8, [x0, #14, mul vl]
|
||||
st1b { z12.b - z13.b }, pn13, [x11, #-10, mul vl]
|
||||
|
||||
st1b { z0.b - z3.b }, pn8, [x0]
|
||||
st1b { z0.b - z3.b }, pn8, [x0, #0, mul vl]
|
||||
ST1B { Z0.B - Z3.B }, PN8, [X0]
|
||||
st1b { z28.b - z31.b }, pn8, [x0]
|
||||
st1b { z0.b - z3.b }, pn15, [x0]
|
||||
st1b { z0.b - z3.b }, pn8, [x30]
|
||||
st1b { z0.b - z3.b }, pn8, [sp]
|
||||
st1b { z0.b - z3.b }, pn8, [x0, #-32, mul vl]
|
||||
st1b { z0.b - z3.b }, pn8, [x0, #28, mul vl]
|
||||
st1b { z8.b - z11.b }, pn11, [x17, #20, mul vl]
|
||||
|
||||
st1b { z0.b, z8.b }, pn8, [x0]
|
||||
st1b { z0.b, z8.b }, pn8, [x0, #0, mul vl]
|
||||
ST1B { Z0.B, Z8.B }, PN8, [X0]
|
||||
st1b { z1.b, z9.b }, pn8, [x0]
|
||||
st1b { z2.b, z10.b }, pn8, [x0]
|
||||
st1b { z3.b, z11.b }, pn8, [x0]
|
||||
st1b { z4.b, z12.b }, pn8, [x0]
|
||||
st1b { z5.b, z13.b }, pn8, [x0]
|
||||
st1b { z6.b, z14.b }, pn8, [x0]
|
||||
st1b { z7.b, z15.b }, pn8, [x0]
|
||||
st1b { z16.b, z24.b }, pn8, [x0]
|
||||
st1b { z17.b, z25.b }, pn8, [x0]
|
||||
st1b { z18.b, z26.b }, pn8, [x0]
|
||||
st1b { z19.b, z27.b }, pn8, [x0]
|
||||
st1b { z20.b, z28.b }, pn8, [x0]
|
||||
st1b { z21.b, z29.b }, pn8, [x0]
|
||||
st1b { z22.b, z30.b }, pn8, [x0]
|
||||
st1b { z23.b, z31.b }, pn8, [x0]
|
||||
st1b { z0.b, z8.b }, pn15, [x0]
|
||||
st1b { z0.b, z8.b }, pn8, [x30]
|
||||
st1b { z0.b, z8.b }, pn8, [sp]
|
||||
st1b { z0.b, z8.b }, pn8, [x0, #-16, mul vl]
|
||||
st1b { z0.b, z8.b }, pn8, [x0, #14, mul vl]
|
||||
st1b { z3.b, z11.b }, pn10, [x22, #6, mul vl]
|
||||
|
||||
st1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0]
|
||||
st1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, #0, mul vl]
|
||||
ST1B { Z0.B, Z4.B, Z8.B, Z12.B }, PN8, [X0]
|
||||
st1b { z1.b, z5.b, z9.b, z13.b }, pn8, [x0]
|
||||
st1b { z2.b, z6.b, z10.b, z14.b }, pn8, [x0]
|
||||
st1b { z3.b, z7.b, z11.b, z15.b }, pn8, [x0]
|
||||
st1b { z16.b, z20.b, z24.b, z28.b }, pn8, [x0]
|
||||
st1b { z17.b, z21.b, z25.b, z29.b }, pn8, [x0]
|
||||
st1b { z18.b, z22.b, z26.b, z30.b }, pn8, [x0]
|
||||
st1b { z19.b, z23.b, z27.b, z31.b }, pn8, [x0]
|
||||
st1b { z0.b, z4.b, z8.b, z12.b }, pn15, [x0]
|
||||
st1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x30]
|
||||
st1b { z0.b, z4.b, z8.b, z12.b }, pn8, [sp]
|
||||
st1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, #-32, mul vl]
|
||||
st1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, #28, mul vl]
|
||||
st1b { z2.b, z6.b, z10.b, z14.b }, pn14, [x29, #8, mul vl]
|
||||
|
||||
st1b { z0.b - z1.b }, pn8, [x0, x1]
|
||||
st1b { z0.b - z1.b }, pn8, [x0, x1, lsl #0]
|
||||
ST1B { Z0.B - Z1.B }, PN8, [X0, X1]
|
||||
st1b { z30.b - z31.b }, pn8, [x0, x1]
|
||||
st1b { z0.b - z1.b }, pn15, [x0, x1]
|
||||
st1b { z0.b - z1.b }, pn8, [x30, x1]
|
||||
st1b { z0.b - z1.b }, pn8, [sp, x1]
|
||||
st1b { z0.b - z1.b }, pn8, [x0, x30]
|
||||
st1b { z0.b - z1.b }, pn8, [x0, xzr]
|
||||
st1b { z14.b - z15.b }, pn9, [x26, x3]
|
||||
|
||||
st1b { z0.b - z3.b }, pn8, [x0, x1]
|
||||
st1b { z0.b - z3.b }, pn8, [x0, x1, lsl #0]
|
||||
ST1B { Z0.B - Z3.B }, PN8, [X0, X1]
|
||||
st1b { z28.b - z31.b }, pn8, [x0, x1]
|
||||
st1b { z0.b - z3.b }, pn15, [x0, x1]
|
||||
st1b { z0.b - z3.b }, pn8, [x30, x1]
|
||||
st1b { z0.b - z3.b }, pn8, [sp, x1]
|
||||
st1b { z0.b - z3.b }, pn8, [x0, x30]
|
||||
st1b { z0.b - z3.b }, pn8, [x0, xzr]
|
||||
st1b { z8.b - z11.b }, pn11, [x27, x1]
|
||||
|
||||
st1b { z0.b, z8.b }, pn8, [x0, x1]
|
||||
st1b { z0.b, z8.b }, pn8, [x0, x1, lsl #0]
|
||||
ST1B { Z0.B, Z8.B }, PN8, [X0, X1]
|
||||
st1b { z1.b, z9.b }, pn8, [x0, x1]
|
||||
st1b { z2.b, z10.b }, pn8, [x0, x1]
|
||||
st1b { z3.b, z11.b }, pn8, [x0, x1]
|
||||
st1b { z4.b, z12.b }, pn8, [x0, x1]
|
||||
st1b { z5.b, z13.b }, pn8, [x0, x1]
|
||||
st1b { z6.b, z14.b }, pn8, [x0, x1]
|
||||
st1b { z7.b, z15.b }, pn8, [x0, x1]
|
||||
st1b { z16.b, z24.b }, pn8, [x0, x1]
|
||||
st1b { z17.b, z25.b }, pn8, [x0, x1]
|
||||
st1b { z18.b, z26.b }, pn8, [x0, x1]
|
||||
st1b { z19.b, z27.b }, pn8, [x0, x1]
|
||||
st1b { z20.b, z28.b }, pn8, [x0, x1]
|
||||
st1b { z21.b, z29.b }, pn8, [x0, x1]
|
||||
st1b { z22.b, z30.b }, pn8, [x0, x1]
|
||||
st1b { z23.b, z31.b }, pn8, [x0, x1]
|
||||
st1b { z0.b, z8.b }, pn15, [x0, x1]
|
||||
st1b { z0.b, z8.b }, pn8, [x30, x1]
|
||||
st1b { z0.b, z8.b }, pn8, [sp, x1]
|
||||
st1b { z0.b, z8.b }, pn8, [x0, x30]
|
||||
st1b { z0.b, z8.b }, pn8, [x0, xzr]
|
||||
st1b { z5.b, z13.b }, pn14, [x15, x24]
|
||||
|
||||
st1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, x1]
|
||||
st1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, x1, lsl #0]
|
||||
ST1B { Z0.B, Z4.B, Z8.B, Z12.B }, PN8, [X0, X1]
|
||||
st1b { z1.b, z5.b, z9.b, z13.b }, pn8, [x0, x1]
|
||||
st1b { z2.b, z6.b, z10.b, z14.b }, pn8, [x0, x1]
|
||||
st1b { z3.b, z7.b, z11.b, z15.b }, pn8, [x0, x1]
|
||||
st1b { z16.b, z20.b, z24.b, z28.b }, pn8, [x0, x1]
|
||||
st1b { z17.b, z21.b, z25.b, z29.b }, pn8, [x0, x1]
|
||||
st1b { z18.b, z22.b, z26.b, z30.b }, pn8, [x0, x1]
|
||||
st1b { z19.b, z23.b, z27.b, z31.b }, pn8, [x0, x1]
|
||||
st1b { z0.b, z4.b, z8.b, z12.b }, pn15, [x0, x1]
|
||||
st1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x30, x1]
|
||||
st1b { z0.b, z4.b, z8.b, z12.b }, pn8, [sp, x1]
|
||||
st1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, x30]
|
||||
st1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, xzr]
|
||||
st1b { z17.b, z21.b, z25.b, z29.b }, pn11, [x4, x6]
|
||||
|
||||
stnt1b { z0.b - z1.b }, pn8, [x0]
|
||||
stnt1b { z0.b - z1.b }, pn8, [x0, #0, mul vl]
|
||||
STNT1B { Z0.B - Z1.B }, PN8, [X0]
|
||||
stnt1b { z30.b - z31.b }, pn8, [x0]
|
||||
stnt1b { z0.b - z1.b }, pn15, [x0]
|
||||
stnt1b { z0.b - z1.b }, pn8, [x30]
|
||||
stnt1b { z0.b - z1.b }, pn8, [sp]
|
||||
stnt1b { z0.b - z1.b }, pn8, [x0, #-16, mul vl]
|
||||
stnt1b { z0.b - z1.b }, pn8, [x0, #14, mul vl]
|
||||
stnt1b { z12.b - z13.b }, pn13, [x11, #-10, mul vl]
|
||||
|
||||
stnt1b { z0.b - z3.b }, pn8, [x0]
|
||||
stnt1b { z0.b - z3.b }, pn8, [x0, #0, mul vl]
|
||||
STNT1B { Z0.B - Z3.B }, PN8, [X0]
|
||||
stnt1b { z28.b - z31.b }, pn8, [x0]
|
||||
stnt1b { z0.b - z3.b }, pn15, [x0]
|
||||
stnt1b { z0.b - z3.b }, pn8, [x30]
|
||||
stnt1b { z0.b - z3.b }, pn8, [sp]
|
||||
stnt1b { z0.b - z3.b }, pn8, [x0, #-32, mul vl]
|
||||
stnt1b { z0.b - z3.b }, pn8, [x0, #28, mul vl]
|
||||
stnt1b { z8.b - z11.b }, pn11, [x17, #20, mul vl]
|
||||
|
||||
stnt1b { z0.b, z8.b }, pn8, [x0]
|
||||
stnt1b { z0.b, z8.b }, pn8, [x0, #0, mul vl]
|
||||
STNT1B { Z0.B, Z8.B }, PN8, [X0]
|
||||
stnt1b { z1.b, z9.b }, pn8, [x0]
|
||||
stnt1b { z2.b, z10.b }, pn8, [x0]
|
||||
stnt1b { z3.b, z11.b }, pn8, [x0]
|
||||
stnt1b { z4.b, z12.b }, pn8, [x0]
|
||||
stnt1b { z5.b, z13.b }, pn8, [x0]
|
||||
stnt1b { z6.b, z14.b }, pn8, [x0]
|
||||
stnt1b { z7.b, z15.b }, pn8, [x0]
|
||||
stnt1b { z16.b, z24.b }, pn8, [x0]
|
||||
stnt1b { z17.b, z25.b }, pn8, [x0]
|
||||
stnt1b { z18.b, z26.b }, pn8, [x0]
|
||||
stnt1b { z19.b, z27.b }, pn8, [x0]
|
||||
stnt1b { z20.b, z28.b }, pn8, [x0]
|
||||
stnt1b { z21.b, z29.b }, pn8, [x0]
|
||||
stnt1b { z22.b, z30.b }, pn8, [x0]
|
||||
stnt1b { z23.b, z31.b }, pn8, [x0]
|
||||
stnt1b { z0.b, z8.b }, pn15, [x0]
|
||||
stnt1b { z0.b, z8.b }, pn8, [x30]
|
||||
stnt1b { z0.b, z8.b }, pn8, [sp]
|
||||
stnt1b { z0.b, z8.b }, pn8, [x0, #-16, mul vl]
|
||||
stnt1b { z0.b, z8.b }, pn8, [x0, #14, mul vl]
|
||||
stnt1b { z3.b, z11.b }, pn10, [x22, #6, mul vl]
|
||||
|
||||
stnt1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0]
|
||||
stnt1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, #0, mul vl]
|
||||
STNT1B { Z0.B, Z4.B, Z8.B, Z12.B }, PN8, [X0]
|
||||
stnt1b { z1.b, z5.b, z9.b, z13.b }, pn8, [x0]
|
||||
stnt1b { z2.b, z6.b, z10.b, z14.b }, pn8, [x0]
|
||||
stnt1b { z3.b, z7.b, z11.b, z15.b }, pn8, [x0]
|
||||
stnt1b { z16.b, z20.b, z24.b, z28.b }, pn8, [x0]
|
||||
stnt1b { z17.b, z21.b, z25.b, z29.b }, pn8, [x0]
|
||||
stnt1b { z18.b, z22.b, z26.b, z30.b }, pn8, [x0]
|
||||
stnt1b { z19.b, z23.b, z27.b, z31.b }, pn8, [x0]
|
||||
stnt1b { z0.b, z4.b, z8.b, z12.b }, pn15, [x0]
|
||||
stnt1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x30]
|
||||
stnt1b { z0.b, z4.b, z8.b, z12.b }, pn8, [sp]
|
||||
stnt1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, #-32, mul vl]
|
||||
stnt1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, #28, mul vl]
|
||||
stnt1b { z2.b, z6.b, z10.b, z14.b }, pn14, [x29, #8, mul vl]
|
||||
|
||||
stnt1b { z0.b - z1.b }, pn8, [x0, x1]
|
||||
stnt1b { z0.b - z1.b }, pn8, [x0, x1, lsl #0]
|
||||
STNT1B { Z0.B - Z1.B }, PN8, [X0, X1]
|
||||
stnt1b { z30.b - z31.b }, pn8, [x0, x1]
|
||||
stnt1b { z0.b - z1.b }, pn15, [x0, x1]
|
||||
stnt1b { z0.b - z1.b }, pn8, [x30, x1]
|
||||
stnt1b { z0.b - z1.b }, pn8, [sp, x1]
|
||||
stnt1b { z0.b - z1.b }, pn8, [x0, x30]
|
||||
stnt1b { z0.b - z1.b }, pn8, [x0, xzr]
|
||||
stnt1b { z14.b - z15.b }, pn9, [x26, x3]
|
||||
|
||||
stnt1b { z0.b - z3.b }, pn8, [x0, x1]
|
||||
stnt1b { z0.b - z3.b }, pn8, [x0, x1, lsl #0]
|
||||
STNT1B { Z0.B - Z3.B }, PN8, [X0, X1]
|
||||
stnt1b { z28.b - z31.b }, pn8, [x0, x1]
|
||||
stnt1b { z0.b - z3.b }, pn15, [x0, x1]
|
||||
stnt1b { z0.b - z3.b }, pn8, [x30, x1]
|
||||
stnt1b { z0.b - z3.b }, pn8, [sp, x1]
|
||||
stnt1b { z0.b - z3.b }, pn8, [x0, x30]
|
||||
stnt1b { z0.b - z3.b }, pn8, [x0, xzr]
|
||||
stnt1b { z8.b - z11.b }, pn11, [x27, x1]
|
||||
|
||||
stnt1b { z0.b, z8.b }, pn8, [x0, x1]
|
||||
stnt1b { z0.b, z8.b }, pn8, [x0, x1, lsl #0]
|
||||
STNT1B { Z0.B, Z8.B }, PN8, [X0, X1]
|
||||
stnt1b { z1.b, z9.b }, pn8, [x0, x1]
|
||||
stnt1b { z2.b, z10.b }, pn8, [x0, x1]
|
||||
stnt1b { z3.b, z11.b }, pn8, [x0, x1]
|
||||
stnt1b { z4.b, z12.b }, pn8, [x0, x1]
|
||||
stnt1b { z5.b, z13.b }, pn8, [x0, x1]
|
||||
stnt1b { z6.b, z14.b }, pn8, [x0, x1]
|
||||
stnt1b { z7.b, z15.b }, pn8, [x0, x1]
|
||||
stnt1b { z16.b, z24.b }, pn8, [x0, x1]
|
||||
stnt1b { z17.b, z25.b }, pn8, [x0, x1]
|
||||
stnt1b { z18.b, z26.b }, pn8, [x0, x1]
|
||||
stnt1b { z19.b, z27.b }, pn8, [x0, x1]
|
||||
stnt1b { z20.b, z28.b }, pn8, [x0, x1]
|
||||
stnt1b { z21.b, z29.b }, pn8, [x0, x1]
|
||||
stnt1b { z22.b, z30.b }, pn8, [x0, x1]
|
||||
stnt1b { z23.b, z31.b }, pn8, [x0, x1]
|
||||
stnt1b { z0.b, z8.b }, pn15, [x0, x1]
|
||||
stnt1b { z0.b, z8.b }, pn8, [x30, x1]
|
||||
stnt1b { z0.b, z8.b }, pn8, [sp, x1]
|
||||
stnt1b { z0.b, z8.b }, pn8, [x0, x30]
|
||||
stnt1b { z0.b, z8.b }, pn8, [x0, xzr]
|
||||
stnt1b { z5.b, z13.b }, pn14, [x15, x24]
|
||||
|
||||
stnt1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, x1]
|
||||
stnt1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, x1, lsl #0]
|
||||
STNT1B { Z0.B, Z4.B, Z8.B, Z12.B }, PN8, [X0, X1]
|
||||
stnt1b { z1.b, z5.b, z9.b, z13.b }, pn8, [x0, x1]
|
||||
stnt1b { z2.b, z6.b, z10.b, z14.b }, pn8, [x0, x1]
|
||||
stnt1b { z3.b, z7.b, z11.b, z15.b }, pn8, [x0, x1]
|
||||
stnt1b { z16.b, z20.b, z24.b, z28.b }, pn8, [x0, x1]
|
||||
stnt1b { z17.b, z21.b, z25.b, z29.b }, pn8, [x0, x1]
|
||||
stnt1b { z18.b, z22.b, z26.b, z30.b }, pn8, [x0, x1]
|
||||
stnt1b { z19.b, z23.b, z27.b, z31.b }, pn8, [x0, x1]
|
||||
stnt1b { z0.b, z4.b, z8.b, z12.b }, pn15, [x0, x1]
|
||||
stnt1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x30, x1]
|
||||
stnt1b { z0.b, z4.b, z8.b, z12.b }, pn8, [sp, x1]
|
||||
stnt1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, x30]
|
||||
stnt1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, xzr]
|
||||
stnt1b { z17.b, z21.b, z25.b, z29.b }, pn11, [x4, x6]
|
||||
3
gas/testsuite/gas/aarch64/sme2-3-invalid.d
Normal file
3
gas/testsuite/gas/aarch64/sme2-3-invalid.d
Normal file
@ -0,0 +1,3 @@
|
||||
#as: -march=armv8-a
|
||||
#source: sme2-3-invalid.s
|
||||
#error_output: sme2-3-invalid.l
|
||||
75
gas/testsuite/gas/aarch64/sme2-3-invalid.l
Normal file
75
gas/testsuite/gas/aarch64/sme2-3-invalid.l
Normal file
@ -0,0 +1,75 @@
|
||||
[^ :]+: Assembler messages:
|
||||
[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `ld1d 0,pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 2 -- `ld1d {z0\.d-z1\.d},0,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {z0\.d-z1\.d},pn8/z,0'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 1 -- `ld1d {z0\.d-z2\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1d {z1\.d-z2\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1d {z0\.d-z1\.d},p8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `ld1d {z0\.d-z1\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: ld1d {z0\.d-z1\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `ld1d {z0\.d-z1\.d},pn8/m,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: ld1d {z0\.d-z1\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `ld1d {z0\.d-z1\.d},pn8\.d,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: ld1d {z0\.d-z1\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1d {z0\.d-z1\.d},pn0/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1d {z0\.d-z1\.d},pn7/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1d {z0\.d-z1\.d},pn8/z,\[w0,w1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1d {z0\.d-z1\.d},pn8/z,\[xzr,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ld1d {z0\.d-z1\.d},pn8/z,\[sp,sp,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {z0\.d-z1\.d},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {z0\.d-z1\.d},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {z0\.d-z1\.d},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {z0\.d-z1\.d},pn8/z,\[x0,x1,lsl#4\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {z0\.d-z1\.d},pn8/z,\[x0,w1,sxtw#3\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {z0\.d-z1\.d},pn8/z,\[x0,w1,uxtw#3\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1d {z1\.d-z4\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1d {z2\.d-z5\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1d {z3\.d-z6\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1d {z0\.d-z3\.d},p8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `ld1d {z0\.d-z3\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: ld1d {z0\.d-z3\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `ld1d {z0\.d-z3\.d},pn8/m,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: ld1d {z0\.d-z3\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `ld1d {z0\.d-z3\.d},pn8\.d,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: ld1d {z0\.d-z3\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1d {z0\.d-z3\.d},pn0/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1d {z0\.d-z3\.d},pn7/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1d {z0\.d-z3\.d},pn8/z,\[w0,w1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1d {z0\.d-z3\.d},pn8/z,\[xzr,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ld1d {z0\.d-z3\.d},pn8/z,\[sp,sp,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {z0\.d-z3\.d},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {z0\.d-z3\.d},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {z0\.d-z3\.d},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {z0\.d-z3\.d},pn8/z,\[x0,x1,lsl#4\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {z0\.d-z3\.d},pn8/z,\[x0,w1,sxtw#3\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {z0\.d-z3\.d},pn8/z,\[x0,w1,uxtw#3\]'
|
||||
[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1d {z0\.d,z2\.d},pn8/z,\[x0,x1,lsl#3\]`
|
||||
[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1d {z0\.d,z3\.d},pn8/z,\[x0,x1,lsl#3\]`
|
||||
[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1d {z0\.d,z4\.d},pn8/z,\[x0,x1,lsl#3\]`
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1d {z8\.d,z16\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1d {z24\.d,z0\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1d {z8\.d,z0\.d},pn8/z,\[x0,x1,lsl#3\]`
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `ld1d {z0\.h,z8\.h},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: ld1d {z0\.d, z8\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1d {z0\.d,z8\.d},p8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1d {z0\.d,z8\.d},pn8/z,\[w0,w30,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1d {z0\.d,z8\.d},pn8/z,\[xzr,xzr,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ld1d {z0\.d,z8\.d},pn8/z,\[x0,sp,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {z0\.d,z8\.d},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1d {z4\.d,z8\.d,z12\.d,z16\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1d {z20\.d,z24\.d,z28\.d,z0\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `ld1d {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: ld1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},p8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[w0,w30,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[xzr,xzr,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0,sp,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0,x1,lsl#1\]'
|
||||
62
gas/testsuite/gas/aarch64/sme2-3-invalid.s
Normal file
62
gas/testsuite/gas/aarch64/sme2-3-invalid.s
Normal file
@ -0,0 +1,62 @@
|
||||
ld1d 0, pn8/z, [x0]
|
||||
ld1d { z0.d - z1.d }, 0, [x0]
|
||||
ld1d { z0.d - z1.d }, pn8/z, 0
|
||||
|
||||
ld1d { z0.d - z2.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z1.d - z2.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z0.d - z1.d }, p8/z, [x0, x1, lsl #3]
|
||||
ld1d { z0.d - z1.d }, pn8, [x0, x1, lsl #3]
|
||||
ld1d { z0.d - z1.d }, pn8/m, [x0, x1, lsl #3]
|
||||
ld1d { z0.d - z1.d }, pn8.d, [x0, x1, lsl #3]
|
||||
ld1d { z0.d - z1.d }, pn0/z, [x0, x1, lsl #3]
|
||||
ld1d { z0.d - z1.d }, pn7/z, [x0, x1, lsl #3]
|
||||
ld1d { z0.d - z1.d }, pn8/z, [w0, w1, lsl #3]
|
||||
ld1d { z0.d - z1.d }, pn8/z, [xzr, x1, lsl #3]
|
||||
ld1d { z0.d - z1.d }, pn8/z, [sp, sp, lsl #3]
|
||||
ld1d { z0.d - z1.d }, pn8/z, [x0, x1]
|
||||
ld1d { z0.d - z1.d }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1d { z0.d - z1.d }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1d { z0.d - z1.d }, pn8/z, [x0, x1, lsl #4]
|
||||
ld1d { z0.d - z1.d }, pn8/z, [x0, w1, sxtw #3]
|
||||
ld1d { z0.d - z1.d }, pn8/z, [x0, w1, uxtw #3]
|
||||
|
||||
ld1d { z1.d - z4.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z2.d - z5.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z3.d - z6.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z0.d - z3.d }, p8/z, [x0, x1, lsl #3]
|
||||
ld1d { z0.d - z3.d }, pn8, [x0, x1, lsl #3]
|
||||
ld1d { z0.d - z3.d }, pn8/m, [x0, x1, lsl #3]
|
||||
ld1d { z0.d - z3.d }, pn8.d, [x0, x1, lsl #3]
|
||||
ld1d { z0.d - z3.d }, pn0/z, [x0, x1, lsl #3]
|
||||
ld1d { z0.d - z3.d }, pn7/z, [x0, x1, lsl #3]
|
||||
ld1d { z0.d - z3.d }, pn8/z, [w0, w1, lsl #3]
|
||||
ld1d { z0.d - z3.d }, pn8/z, [xzr, x1, lsl #3]
|
||||
ld1d { z0.d - z3.d }, pn8/z, [sp, sp, lsl #3]
|
||||
ld1d { z0.d - z3.d }, pn8/z, [x0, x1]
|
||||
ld1d { z0.d - z3.d }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1d { z0.d - z3.d }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1d { z0.d - z3.d }, pn8/z, [x0, x1, lsl #4]
|
||||
ld1d { z0.d - z3.d }, pn8/z, [x0, w1, sxtw #3]
|
||||
ld1d { z0.d - z3.d }, pn8/z, [x0, w1, uxtw #3]
|
||||
|
||||
ld1d { z0.d, z2.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z0.d, z3.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z0.d, z4.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z8.d, z16.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z24.d, z0.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z8.d, z0.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z0.h, z8.h }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z0.d, z8.d }, p8/z, [x0, x1, lsl #3]
|
||||
ld1d { z0.d, z8.d }, pn8/z, [w0, w30, lsl #3]
|
||||
ld1d { z0.d, z8.d }, pn8/z, [xzr, xzr, lsl #3]
|
||||
ld1d { z0.d, z8.d }, pn8/z, [x0, sp, lsl #3]
|
||||
ld1d { z0.d, z8.d }, pn8/z, [x0, x1, lsl #1]
|
||||
|
||||
ld1d { z4.d, z8.d, z12.d, z16.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z20.d, z24.d, z28.d, z0.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z0.d, z4.d, z8.d, z12.d }, p8/z, [x0, x1, lsl #3]
|
||||
ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [w0, w30, lsl #3]
|
||||
ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [xzr, xzr, lsl #3]
|
||||
ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, sp, lsl #3]
|
||||
ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, x1, lsl #1]
|
||||
3
gas/testsuite/gas/aarch64/sme2-3-noarch.d
Normal file
3
gas/testsuite/gas/aarch64/sme2-3-noarch.d
Normal file
@ -0,0 +1,3 @@
|
||||
#as: -march=armv8-a+sme
|
||||
#source: sme2-3.s
|
||||
#error_output: sme2-3-noarch.l
|
||||
481
gas/testsuite/gas/aarch64/sme2-3-noarch.l
Normal file
481
gas/testsuite/gas/aarch64/sme2-3-noarch.l
Normal file
@ -0,0 +1,481 @@
|
||||
[^ :]+: Assembler messages:
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z1\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z1\.d},pn8/z,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {Z0\.D-Z1\.D},PN8/Z,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z30\.d-z31\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z1\.d},pn15/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z1\.d},pn8/z,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z1\.d},pn8/z,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z1\.d},pn8/z,\[x0,#-16,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z1\.d},pn8/z,\[x0,#14,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z12\.d-z13\.d},pn13/z,\[x11,#-10,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z3\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z3\.d},pn8/z,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {Z0\.D-Z3\.D},PN8/Z,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z28\.d-z31\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z3\.d},pn15/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z3\.d},pn8/z,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z3\.d},pn8/z,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z3\.d},pn8/z,\[x0,#-32,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z3\.d},pn8/z,\[x0,#28,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z8\.d-z11\.d},pn11/z,\[x17,#20,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z8\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z8\.d},pn8/z,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {Z0\.D,Z8\.D},PN8/Z,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z1\.d,z9\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z2\.d,z10\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z3\.d,z11\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z4\.d,z12\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z5\.d,z13\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z6\.d,z14\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z7\.d,z15\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z16\.d,z24\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z17\.d,z25\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z18\.d,z26\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z19\.d,z27\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z20\.d,z28\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z21\.d,z29\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z22\.d,z30\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z23\.d,z31\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z8\.d},pn15/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z8\.d},pn8/z,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z8\.d},pn8/z,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z8\.d},pn8/z,\[x0,#-16,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z8\.d},pn8/z,\[x0,#14,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z3\.d,z11\.d},pn10/z,\[x22,#6,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {Z0\.D,Z4\.D,Z8\.D,Z12\.D},PN8/Z,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z1\.d,z5\.d,z9\.d,z13\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z2\.d,z6\.d,z10\.d,z14\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z3\.d,z7\.d,z11\.d,z15\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z16\.d,z20\.d,z24\.d,z28\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z17\.d,z21\.d,z25\.d,z29\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z18\.d,z22\.d,z26\.d,z30\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z19\.d,z23\.d,z27\.d,z31\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},pn15/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0,#-32,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0,#28,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z2\.d,z6\.d,z10\.d,z14\.d},pn14/z,\[x29,#8,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z1\.d},pn8/z,\[x0,x1,lsl 3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z1\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {Z0\.D-Z1\.D},PN8/Z,\[X0,X1,LSL#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z30\.d-z31\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z1\.d},pn15/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z1\.d},pn8/z,\[x30,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z1\.d},pn8/z,\[sp,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z1\.d},pn8/z,\[x0,x30,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z1\.d},pn8/z,\[x0,xzr,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z14\.d-z15\.d},pn9/z,\[x26,x3,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z3\.d},pn8/z,\[x0,x1,lsl 3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z3\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {Z0\.D-Z3\.D},PN8/Z,\[X0,X1,LSL#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z28\.d-z31\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z3\.d},pn15/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z3\.d},pn8/z,\[x30,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z3\.d},pn8/z,\[sp,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z3\.d},pn8/z,\[x0,x30,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d-z3\.d},pn8/z,\[x0,xzr,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z8\.d-z11\.d},pn11/z,\[x27,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z8\.d},pn8/z,\[x0,x1,lsl 3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z8\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {Z0\.D,Z8\.D},PN8/Z,\[X0,X1,LSL#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z1\.d,z9\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z2\.d,z10\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z3\.d,z11\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z4\.d,z12\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z5\.d,z13\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z6\.d,z14\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z7\.d,z15\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z16\.d,z24\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z17\.d,z25\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z18\.d,z26\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z19\.d,z27\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z20\.d,z28\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z21\.d,z29\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z22\.d,z30\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z23\.d,z31\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z8\.d},pn15/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z8\.d},pn8/z,\[x30,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z8\.d},pn8/z,\[sp,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z8\.d},pn8/z,\[x0,x30,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z8\.d},pn8/z,\[x0,xzr,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z5\.d,z13\.d},pn14/z,\[x15,x24,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0,x1,lsl 3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {Z0\.D,Z4\.D,Z8\.D,Z12\.D},PN8/Z,\[X0,X1,LSL#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z1\.d,z5\.d,z9\.d,z13\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z2\.d,z6\.d,z10\.d,z14\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z3\.d,z7\.d,z11\.d,z15\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z16\.d,z20\.d,z24\.d,z28\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z17\.d,z21\.d,z25\.d,z29\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z18\.d,z22\.d,z26\.d,z30\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z19\.d,z23\.d,z27\.d,z31\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},pn15/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x30,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[sp,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0,x30,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0,xzr,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1d {z17\.d,z21\.d,z25\.d,z29\.d},pn11/z,\[x4,x6,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z1\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z1\.d},pn8/z,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {Z0\.D-Z1\.D},PN8/Z,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z30\.d-z31\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z1\.d},pn15/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z1\.d},pn8/z,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z1\.d},pn8/z,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z1\.d},pn8/z,\[x0,#-16,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z1\.d},pn8/z,\[x0,#14,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z12\.d-z13\.d},pn13/z,\[x11,#-10,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z3\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z3\.d},pn8/z,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {Z0\.D-Z3\.D},PN8/Z,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z28\.d-z31\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z3\.d},pn15/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z3\.d},pn8/z,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z3\.d},pn8/z,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z3\.d},pn8/z,\[x0,#-32,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z3\.d},pn8/z,\[x0,#28,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z8\.d-z11\.d},pn11/z,\[x17,#20,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z8\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z8\.d},pn8/z,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {Z0\.D,Z8\.D},PN8/Z,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z1\.d,z9\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z2\.d,z10\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z3\.d,z11\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z4\.d,z12\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z5\.d,z13\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z6\.d,z14\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z7\.d,z15\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z16\.d,z24\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z17\.d,z25\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z18\.d,z26\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z19\.d,z27\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z20\.d,z28\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z21\.d,z29\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z22\.d,z30\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z23\.d,z31\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z8\.d},pn15/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z8\.d},pn8/z,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z8\.d},pn8/z,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z8\.d},pn8/z,\[x0,#-16,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z8\.d},pn8/z,\[x0,#14,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z3\.d,z11\.d},pn10/z,\[x22,#6,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {Z0\.D,Z4\.D,Z8\.D,Z12\.D},PN8/Z,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z1\.d,z5\.d,z9\.d,z13\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z2\.d,z6\.d,z10\.d,z14\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z3\.d,z7\.d,z11\.d,z15\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z16\.d,z20\.d,z24\.d,z28\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z17\.d,z21\.d,z25\.d,z29\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z18\.d,z22\.d,z26\.d,z30\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z19\.d,z23\.d,z27\.d,z31\.d},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn15/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0,#-32,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0,#28,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z2\.d,z6\.d,z10\.d,z14\.d},pn14/z,\[x29,#8,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z1\.d},pn8/z,\[x0,x1,lsl 3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z1\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {Z0\.D-Z1\.D},PN8/Z,\[X0,X1,LSL#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z30\.d-z31\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z1\.d},pn15/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z1\.d},pn8/z,\[x30,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z1\.d},pn8/z,\[sp,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z1\.d},pn8/z,\[x0,x30,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z1\.d},pn8/z,\[x0,xzr,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z14\.d-z15\.d},pn9/z,\[x26,x3,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z3\.d},pn8/z,\[x0,x1,lsl 3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z3\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {Z0\.D-Z3\.D},PN8/Z,\[X0,X1,LSL#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z28\.d-z31\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z3\.d},pn15/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z3\.d},pn8/z,\[x30,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z3\.d},pn8/z,\[sp,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z3\.d},pn8/z,\[x0,x30,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d-z3\.d},pn8/z,\[x0,xzr,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z8\.d-z11\.d},pn11/z,\[x27,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z8\.d},pn8/z,\[x0,x1,lsl 3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z8\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {Z0\.D,Z8\.D},PN8/Z,\[X0,X1,LSL#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z1\.d,z9\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z2\.d,z10\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z3\.d,z11\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z4\.d,z12\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z5\.d,z13\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z6\.d,z14\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z7\.d,z15\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z16\.d,z24\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z17\.d,z25\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z18\.d,z26\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z19\.d,z27\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z20\.d,z28\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z21\.d,z29\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z22\.d,z30\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z23\.d,z31\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z8\.d},pn15/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z8\.d},pn8/z,\[x30,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z8\.d},pn8/z,\[sp,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z8\.d},pn8/z,\[x0,x30,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z8\.d},pn8/z,\[x0,xzr,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z5\.d,z13\.d},pn14/z,\[x15,x24,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0,x1,lsl 3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {Z0\.D,Z4\.D,Z8\.D,Z12\.D},PN8/Z,\[X0,X1,LSL#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z1\.d,z5\.d,z9\.d,z13\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z2\.d,z6\.d,z10\.d,z14\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z3\.d,z7\.d,z11\.d,z15\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z16\.d,z20\.d,z24\.d,z28\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z17\.d,z21\.d,z25\.d,z29\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z18\.d,z22\.d,z26\.d,z30\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z19\.d,z23\.d,z27\.d,z31\.d},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn15/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x30,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[sp,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0,x30,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0,xzr,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z17\.d,z21\.d,z25\.d,z29\.d},pn11/z,\[x4,x6,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z1\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z1\.d},pn8,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {Z0\.D-Z1\.D},PN8,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z30\.d-z31\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z1\.d},pn15,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z1\.d},pn8,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z1\.d},pn8,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z1\.d},pn8,\[x0,#-16,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z1\.d},pn8,\[x0,#14,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z12\.d-z13\.d},pn13,\[x11,#-10,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z3\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z3\.d},pn8,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {Z0\.D-Z3\.D},PN8,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z28\.d-z31\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z3\.d},pn15,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z3\.d},pn8,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z3\.d},pn8,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z3\.d},pn8,\[x0,#-32,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z3\.d},pn8,\[x0,#28,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z8\.d-z11\.d},pn11,\[x17,#20,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z8\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z8\.d},pn8,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {Z0\.D,Z8\.D},PN8,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z1\.d,z9\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z2\.d,z10\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z3\.d,z11\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z4\.d,z12\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z5\.d,z13\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z6\.d,z14\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z7\.d,z15\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z16\.d,z24\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z17\.d,z25\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z18\.d,z26\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z19\.d,z27\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z20\.d,z28\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z21\.d,z29\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z22\.d,z30\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z23\.d,z31\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z8\.d},pn15,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z8\.d},pn8,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z8\.d},pn8,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z8\.d},pn8,\[x0,#-16,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z8\.d},pn8,\[x0,#14,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z3\.d,z11\.d},pn10,\[x22,#6,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {Z0\.D,Z4\.D,Z8\.D,Z12\.D},PN8,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z1\.d,z5\.d,z9\.d,z13\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z2\.d,z6\.d,z10\.d,z14\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z3\.d,z7\.d,z11\.d,z15\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z16\.d,z20\.d,z24\.d,z28\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z17\.d,z21\.d,z25\.d,z29\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z18\.d,z22\.d,z26\.d,z30\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z19\.d,z23\.d,z27\.d,z31\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z4\.d,z8\.d,z12\.d},pn15,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x0,#-32,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x0,#28,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z2\.d,z6\.d,z10\.d,z14\.d},pn14,\[x29,#8,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z1\.d},pn8,\[x0,x1,lsl 3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z1\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {Z0\.D-Z1\.D},PN8,\[X0,X1,LSL#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z30\.d-z31\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z1\.d},pn15,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z1\.d},pn8,\[x30,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z1\.d},pn8,\[sp,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z1\.d},pn8,\[x0,x30,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z1\.d},pn8,\[x0,xzr,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z14\.d-z15\.d},pn9,\[x26,x3,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z3\.d},pn8,\[x0,x1,lsl 3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z3\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {Z0\.D-Z3\.D},PN8,\[X0,X1,LSL#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z28\.d-z31\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z3\.d},pn15,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z3\.d},pn8,\[x30,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z3\.d},pn8,\[sp,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z3\.d},pn8,\[x0,x30,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d-z3\.d},pn8,\[x0,xzr,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z8\.d-z11\.d},pn11,\[x27,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z8\.d},pn8,\[x0,x1,lsl 3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z8\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {Z0\.D,Z8\.D},PN8,\[X0,X1,LSL#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z1\.d,z9\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z2\.d,z10\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z3\.d,z11\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z4\.d,z12\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z5\.d,z13\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z6\.d,z14\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z7\.d,z15\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z16\.d,z24\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z17\.d,z25\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z18\.d,z26\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z19\.d,z27\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z20\.d,z28\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z21\.d,z29\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z22\.d,z30\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z23\.d,z31\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z8\.d},pn15,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z8\.d},pn8,\[x30,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z8\.d},pn8,\[sp,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z8\.d},pn8,\[x0,x30,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z8\.d},pn8,\[x0,xzr,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z5\.d,z13\.d},pn14,\[x15,x24,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x0,x1,lsl 3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {Z0\.D,Z4\.D,Z8\.D,Z12\.D},PN8,\[X0,X1,LSL#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z1\.d,z5\.d,z9\.d,z13\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z2\.d,z6\.d,z10\.d,z14\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z3\.d,z7\.d,z11\.d,z15\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z16\.d,z20\.d,z24\.d,z28\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z17\.d,z21\.d,z25\.d,z29\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z18\.d,z22\.d,z26\.d,z30\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z19\.d,z23\.d,z27\.d,z31\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z4\.d,z8\.d,z12\.d},pn15,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x30,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[sp,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x0,x30,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x0,xzr,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1d {z17\.d,z21\.d,z25\.d,z29\.d},pn11,\[x4,x6,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z1\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z1\.d},pn8,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {Z0\.D-Z1\.D},PN8,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z30\.d-z31\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z1\.d},pn15,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z1\.d},pn8,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z1\.d},pn8,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z1\.d},pn8,\[x0,#-16,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z1\.d},pn8,\[x0,#14,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z12\.d-z13\.d},pn13,\[x11,#-10,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z3\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z3\.d},pn8,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {Z0\.D-Z3\.D},PN8,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z28\.d-z31\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z3\.d},pn15,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z3\.d},pn8,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z3\.d},pn8,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z3\.d},pn8,\[x0,#-32,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z3\.d},pn8,\[x0,#28,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z8\.d-z11\.d},pn11,\[x17,#20,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z8\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z8\.d},pn8,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {Z0\.D,Z8\.D},PN8,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z1\.d,z9\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z2\.d,z10\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z3\.d,z11\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z4\.d,z12\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z5\.d,z13\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z6\.d,z14\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z7\.d,z15\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z16\.d,z24\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z17\.d,z25\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z18\.d,z26\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z19\.d,z27\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z20\.d,z28\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z21\.d,z29\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z22\.d,z30\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z23\.d,z31\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z8\.d},pn15,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z8\.d},pn8,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z8\.d},pn8,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z8\.d},pn8,\[x0,#-16,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z8\.d},pn8,\[x0,#14,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z3\.d,z11\.d},pn10,\[x22,#6,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {Z0\.D,Z4\.D,Z8\.D,Z12\.D},PN8,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z1\.d,z5\.d,z9\.d,z13\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z2\.d,z6\.d,z10\.d,z14\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z3\.d,z7\.d,z11\.d,z15\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z16\.d,z20\.d,z24\.d,z28\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z17\.d,z21\.d,z25\.d,z29\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z18\.d,z22\.d,z26\.d,z30\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z19\.d,z23\.d,z27\.d,z31\.d},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn15,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x0,#-32,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x0,#28,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z2\.d,z6\.d,z10\.d,z14\.d},pn14,\[x29,#8,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z1\.d},pn8,\[x0,x1,lsl 3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z1\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {Z0\.D-Z1\.D},PN8,\[X0,X1,LSL#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z30\.d-z31\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z1\.d},pn15,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z1\.d},pn8,\[x30,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z1\.d},pn8,\[sp,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z1\.d},pn8,\[x0,x30,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z1\.d},pn8,\[x0,xzr,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z14\.d-z15\.d},pn9,\[x26,x3,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z3\.d},pn8,\[x0,x1,lsl 3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z3\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {Z0\.D-Z3\.D},PN8,\[X0,X1,LSL#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z28\.d-z31\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z3\.d},pn15,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z3\.d},pn8,\[x30,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z3\.d},pn8,\[sp,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z3\.d},pn8,\[x0,x30,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d-z3\.d},pn8,\[x0,xzr,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z8\.d-z11\.d},pn11,\[x27,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z8\.d},pn8,\[x0,x1,lsl 3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z8\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {Z0\.D,Z8\.D},PN8,\[X0,X1,LSL#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z1\.d,z9\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z2\.d,z10\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z3\.d,z11\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z4\.d,z12\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z5\.d,z13\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z6\.d,z14\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z7\.d,z15\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z16\.d,z24\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z17\.d,z25\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z18\.d,z26\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z19\.d,z27\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z20\.d,z28\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z21\.d,z29\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z22\.d,z30\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z23\.d,z31\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z8\.d},pn15,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z8\.d},pn8,\[x30,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z8\.d},pn8,\[sp,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z8\.d},pn8,\[x0,x30,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z8\.d},pn8,\[x0,xzr,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z5\.d,z13\.d},pn14,\[x15,x24,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x0,x1,lsl 3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {Z0\.D,Z4\.D,Z8\.D,Z12\.D},PN8,\[X0,X1,LSL#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z1\.d,z5\.d,z9\.d,z13\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z2\.d,z6\.d,z10\.d,z14\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z3\.d,z7\.d,z11\.d,z15\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z16\.d,z20\.d,z24\.d,z28\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z17\.d,z21\.d,z25\.d,z29\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z18\.d,z22\.d,z26\.d,z30\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z19\.d,z23\.d,z27\.d,z31\.d},pn8,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn15,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x30,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[sp,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x0,x30,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d,z4\.d,z8\.d,z12\.d},pn8,\[x0,xzr,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z17\.d,z21\.d,z25\.d,z29\.d},pn11,\[x4,x6,lsl#3\]'
|
||||
489
gas/testsuite/gas/aarch64/sme2-3.d
Normal file
489
gas/testsuite/gas/aarch64/sme2-3.d
Normal file
@ -0,0 +1,489 @@
|
||||
#as: -march=armv8-a+sme2
|
||||
#objdump: -dr
|
||||
|
||||
[^:]+: file format .*
|
||||
|
||||
|
||||
[^:]+:
|
||||
|
||||
[^:]+:
|
||||
[^:]+: a0406000 ld1d {z0\.d-z1\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a0406000 ld1d {z0\.d-z1\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a0406000 ld1d {z0\.d-z1\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a040601e ld1d {z30\.d-z31\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a0407c00 ld1d {z0\.d-z1\.d}, pn15/z, \[x0\]
|
||||
[^:]+: a04063c0 ld1d {z0\.d-z1\.d}, pn8/z, \[x30\]
|
||||
[^:]+: a04063e0 ld1d {z0\.d-z1\.d}, pn8/z, \[sp\]
|
||||
[^:]+: a0486000 ld1d {z0\.d-z1\.d}, pn8/z, \[x0, #-16, mul vl\]
|
||||
[^:]+: a0476000 ld1d {z0\.d-z1\.d}, pn8/z, \[x0, #14, mul vl\]
|
||||
[^:]+: a04b756c ld1d {z12\.d-z13\.d}, pn13/z, \[x11, #-10, mul vl\]
|
||||
[^:]+: a040e000 ld1d {z0\.d-z3\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a040e000 ld1d {z0\.d-z3\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a040e000 ld1d {z0\.d-z3\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a040e01c ld1d {z28\.d-z31\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a040fc00 ld1d {z0\.d-z3\.d}, pn15/z, \[x0\]
|
||||
[^:]+: a040e3c0 ld1d {z0\.d-z3\.d}, pn8/z, \[x30\]
|
||||
[^:]+: a040e3e0 ld1d {z0\.d-z3\.d}, pn8/z, \[sp\]
|
||||
[^:]+: a048e000 ld1d {z0\.d-z3\.d}, pn8/z, \[x0, #-32, mul vl\]
|
||||
[^:]+: a047e000 ld1d {z0\.d-z3\.d}, pn8/z, \[x0, #28, mul vl\]
|
||||
[^:]+: a045ee28 ld1d {z8\.d-z11\.d}, pn11/z, \[x17, #20, mul vl\]
|
||||
[^:]+: a1406000 ld1d {z0\.d, z8\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a1406000 ld1d {z0\.d, z8\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a1406000 ld1d {z0\.d, z8\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a1406001 ld1d {z1\.d, z9\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a1406002 ld1d {z2\.d, z10\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a1406003 ld1d {z3\.d, z11\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a1406004 ld1d {z4\.d, z12\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a1406005 ld1d {z5\.d, z13\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a1406006 ld1d {z6\.d, z14\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a1406007 ld1d {z7\.d, z15\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a1406010 ld1d {z16\.d, z24\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a1406011 ld1d {z17\.d, z25\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a1406012 ld1d {z18\.d, z26\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a1406013 ld1d {z19\.d, z27\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a1406014 ld1d {z20\.d, z28\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a1406015 ld1d {z21\.d, z29\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a1406016 ld1d {z22\.d, z30\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a1406017 ld1d {z23\.d, z31\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a1407c00 ld1d {z0\.d, z8\.d}, pn15/z, \[x0\]
|
||||
[^:]+: a14063c0 ld1d {z0\.d, z8\.d}, pn8/z, \[x30\]
|
||||
[^:]+: a14063e0 ld1d {z0\.d, z8\.d}, pn8/z, \[sp\]
|
||||
[^:]+: a1486000 ld1d {z0\.d, z8\.d}, pn8/z, \[x0, #-16, mul vl\]
|
||||
[^:]+: a1476000 ld1d {z0\.d, z8\.d}, pn8/z, \[x0, #14, mul vl\]
|
||||
[^:]+: a1436ac3 ld1d {z3\.d, z11\.d}, pn10/z, \[x22, #6, mul vl\]
|
||||
[^:]+: a140e000 ld1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a140e000 ld1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a140e000 ld1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a140e001 ld1d {z1\.d, z5\.d, z9\.d, z13\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a140e002 ld1d {z2\.d, z6\.d, z10\.d, z14\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a140e003 ld1d {z3\.d, z7\.d, z11\.d, z15\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a140e010 ld1d {z16\.d, z20\.d, z24\.d, z28\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a140e011 ld1d {z17\.d, z21\.d, z25\.d, z29\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a140e012 ld1d {z18\.d, z22\.d, z26\.d, z30\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a140e013 ld1d {z19\.d, z23\.d, z27\.d, z31\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a140fc00 ld1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn15/z, \[x0\]
|
||||
[^:]+: a140e3c0 ld1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x30\]
|
||||
[^:]+: a140e3e0 ld1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[sp\]
|
||||
[^:]+: a148e000 ld1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x0, #-32, mul vl\]
|
||||
[^:]+: a147e000 ld1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x0, #28, mul vl\]
|
||||
[^:]+: a142fba2 ld1d {z2\.d, z6\.d, z10\.d, z14\.d}, pn14/z, \[x29, #8, mul vl\]
|
||||
[^:]+: a0016000 ld1d {z0\.d-z1\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a0016000 ld1d {z0\.d-z1\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a0016000 ld1d {z0\.d-z1\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a001601e ld1d {z30\.d-z31\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a0017c00 ld1d {z0\.d-z1\.d}, pn15/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a00163c0 ld1d {z0\.d-z1\.d}, pn8/z, \[x30, x1, lsl #3\]
|
||||
[^:]+: a00163e0 ld1d {z0\.d-z1\.d}, pn8/z, \[sp, x1, lsl #3\]
|
||||
[^:]+: a01e6000 ld1d {z0\.d-z1\.d}, pn8/z, \[x0, x30, lsl #3\]
|
||||
[^:]+: a01f6000 ld1d {z0\.d-z1\.d}, pn8/z, \[x0, xzr, lsl #3\]
|
||||
[^:]+: a003674e ld1d {z14\.d-z15\.d}, pn9/z, \[x26, x3, lsl #3\]
|
||||
[^:]+: a001e000 ld1d {z0\.d-z3\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a001e000 ld1d {z0\.d-z3\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a001e000 ld1d {z0\.d-z3\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a001e01c ld1d {z28\.d-z31\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a001fc00 ld1d {z0\.d-z3\.d}, pn15/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a001e3c0 ld1d {z0\.d-z3\.d}, pn8/z, \[x30, x1, lsl #3\]
|
||||
[^:]+: a001e3e0 ld1d {z0\.d-z3\.d}, pn8/z, \[sp, x1, lsl #3\]
|
||||
[^:]+: a01ee000 ld1d {z0\.d-z3\.d}, pn8/z, \[x0, x30, lsl #3\]
|
||||
[^:]+: a01fe000 ld1d {z0\.d-z3\.d}, pn8/z, \[x0, xzr, lsl #3\]
|
||||
[^:]+: a001ef68 ld1d {z8\.d-z11\.d}, pn11/z, \[x27, x1, lsl #3\]
|
||||
[^:]+: a1016000 ld1d {z0\.d, z8\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1016000 ld1d {z0\.d, z8\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1016000 ld1d {z0\.d, z8\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1016001 ld1d {z1\.d, z9\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1016002 ld1d {z2\.d, z10\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1016003 ld1d {z3\.d, z11\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1016004 ld1d {z4\.d, z12\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1016005 ld1d {z5\.d, z13\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1016006 ld1d {z6\.d, z14\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1016007 ld1d {z7\.d, z15\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1016010 ld1d {z16\.d, z24\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1016011 ld1d {z17\.d, z25\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1016012 ld1d {z18\.d, z26\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1016013 ld1d {z19\.d, z27\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1016014 ld1d {z20\.d, z28\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1016015 ld1d {z21\.d, z29\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1016016 ld1d {z22\.d, z30\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1016017 ld1d {z23\.d, z31\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1017c00 ld1d {z0\.d, z8\.d}, pn15/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a10163c0 ld1d {z0\.d, z8\.d}, pn8/z, \[x30, x1, lsl #3\]
|
||||
[^:]+: a10163e0 ld1d {z0\.d, z8\.d}, pn8/z, \[sp, x1, lsl #3\]
|
||||
[^:]+: a11e6000 ld1d {z0\.d, z8\.d}, pn8/z, \[x0, x30, lsl #3\]
|
||||
[^:]+: a11f6000 ld1d {z0\.d, z8\.d}, pn8/z, \[x0, xzr, lsl #3\]
|
||||
[^:]+: a11879e5 ld1d {z5\.d, z13\.d}, pn14/z, \[x15, x24, lsl #3\]
|
||||
[^:]+: a101e000 ld1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a101e000 ld1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a101e000 ld1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a101e001 ld1d {z1\.d, z5\.d, z9\.d, z13\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a101e002 ld1d {z2\.d, z6\.d, z10\.d, z14\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a101e003 ld1d {z3\.d, z7\.d, z11\.d, z15\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a101e010 ld1d {z16\.d, z20\.d, z24\.d, z28\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a101e011 ld1d {z17\.d, z21\.d, z25\.d, z29\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a101e012 ld1d {z18\.d, z22\.d, z26\.d, z30\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a101e013 ld1d {z19\.d, z23\.d, z27\.d, z31\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a101fc00 ld1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn15/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a101e3c0 ld1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x30, x1, lsl #3\]
|
||||
[^:]+: a101e3e0 ld1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[sp, x1, lsl #3\]
|
||||
[^:]+: a11ee000 ld1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x0, x30, lsl #3\]
|
||||
[^:]+: a11fe000 ld1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x0, xzr, lsl #3\]
|
||||
[^:]+: a106ec91 ld1d {z17\.d, z21\.d, z25\.d, z29\.d}, pn11/z, \[x4, x6, lsl #3\]
|
||||
[^:]+: a0406001 ldnt1d {z0\.d-z1\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a0406001 ldnt1d {z0\.d-z1\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a0406001 ldnt1d {z0\.d-z1\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a040601f ldnt1d {z30\.d-z31\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a0407c01 ldnt1d {z0\.d-z1\.d}, pn15/z, \[x0\]
|
||||
[^:]+: a04063c1 ldnt1d {z0\.d-z1\.d}, pn8/z, \[x30\]
|
||||
[^:]+: a04063e1 ldnt1d {z0\.d-z1\.d}, pn8/z, \[sp\]
|
||||
[^:]+: a0486001 ldnt1d {z0\.d-z1\.d}, pn8/z, \[x0, #-16, mul vl\]
|
||||
[^:]+: a0476001 ldnt1d {z0\.d-z1\.d}, pn8/z, \[x0, #14, mul vl\]
|
||||
[^:]+: a04b756d ldnt1d {z12\.d-z13\.d}, pn13/z, \[x11, #-10, mul vl\]
|
||||
[^:]+: a040e001 ldnt1d {z0\.d-z3\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a040e001 ldnt1d {z0\.d-z3\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a040e001 ldnt1d {z0\.d-z3\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a040e01d ldnt1d {z28\.d-z31\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a040fc01 ldnt1d {z0\.d-z3\.d}, pn15/z, \[x0\]
|
||||
[^:]+: a040e3c1 ldnt1d {z0\.d-z3\.d}, pn8/z, \[x30\]
|
||||
[^:]+: a040e3e1 ldnt1d {z0\.d-z3\.d}, pn8/z, \[sp\]
|
||||
[^:]+: a048e001 ldnt1d {z0\.d-z3\.d}, pn8/z, \[x0, #-32, mul vl\]
|
||||
[^:]+: a047e001 ldnt1d {z0\.d-z3\.d}, pn8/z, \[x0, #28, mul vl\]
|
||||
[^:]+: a045ee29 ldnt1d {z8\.d-z11\.d}, pn11/z, \[x17, #20, mul vl\]
|
||||
[^:]+: a1406008 ldnt1d {z0\.d, z8\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a1406008 ldnt1d {z0\.d, z8\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a1406008 ldnt1d {z0\.d, z8\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a1406009 ldnt1d {z1\.d, z9\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a140600a ldnt1d {z2\.d, z10\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a140600b ldnt1d {z3\.d, z11\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a140600c ldnt1d {z4\.d, z12\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a140600d ldnt1d {z5\.d, z13\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a140600e ldnt1d {z6\.d, z14\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a140600f ldnt1d {z7\.d, z15\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a1406018 ldnt1d {z16\.d, z24\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a1406019 ldnt1d {z17\.d, z25\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a140601a ldnt1d {z18\.d, z26\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a140601b ldnt1d {z19\.d, z27\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a140601c ldnt1d {z20\.d, z28\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a140601d ldnt1d {z21\.d, z29\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a140601e ldnt1d {z22\.d, z30\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a140601f ldnt1d {z23\.d, z31\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a1407c08 ldnt1d {z0\.d, z8\.d}, pn15/z, \[x0\]
|
||||
[^:]+: a14063c8 ldnt1d {z0\.d, z8\.d}, pn8/z, \[x30\]
|
||||
[^:]+: a14063e8 ldnt1d {z0\.d, z8\.d}, pn8/z, \[sp\]
|
||||
[^:]+: a1486008 ldnt1d {z0\.d, z8\.d}, pn8/z, \[x0, #-16, mul vl\]
|
||||
[^:]+: a1476008 ldnt1d {z0\.d, z8\.d}, pn8/z, \[x0, #14, mul vl\]
|
||||
[^:]+: a1436acb ldnt1d {z3\.d, z11\.d}, pn10/z, \[x22, #6, mul vl\]
|
||||
[^:]+: a140e008 ldnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a140e008 ldnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a140e008 ldnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a140e009 ldnt1d {z1\.d, z5\.d, z9\.d, z13\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a140e00a ldnt1d {z2\.d, z6\.d, z10\.d, z14\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a140e00b ldnt1d {z3\.d, z7\.d, z11\.d, z15\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a140e018 ldnt1d {z16\.d, z20\.d, z24\.d, z28\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a140e019 ldnt1d {z17\.d, z21\.d, z25\.d, z29\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a140e01a ldnt1d {z18\.d, z22\.d, z26\.d, z30\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a140e01b ldnt1d {z19\.d, z23\.d, z27\.d, z31\.d}, pn8/z, \[x0\]
|
||||
[^:]+: a140fc08 ldnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn15/z, \[x0\]
|
||||
[^:]+: a140e3c8 ldnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x30\]
|
||||
[^:]+: a140e3e8 ldnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[sp\]
|
||||
[^:]+: a148e008 ldnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x0, #-32, mul vl\]
|
||||
[^:]+: a147e008 ldnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x0, #28, mul vl\]
|
||||
[^:]+: a142fbaa ldnt1d {z2\.d, z6\.d, z10\.d, z14\.d}, pn14/z, \[x29, #8, mul vl\]
|
||||
[^:]+: a0016001 ldnt1d {z0\.d-z1\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a0016001 ldnt1d {z0\.d-z1\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a0016001 ldnt1d {z0\.d-z1\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a001601f ldnt1d {z30\.d-z31\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a0017c01 ldnt1d {z0\.d-z1\.d}, pn15/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a00163c1 ldnt1d {z0\.d-z1\.d}, pn8/z, \[x30, x1, lsl #3\]
|
||||
[^:]+: a00163e1 ldnt1d {z0\.d-z1\.d}, pn8/z, \[sp, x1, lsl #3\]
|
||||
[^:]+: a01e6001 ldnt1d {z0\.d-z1\.d}, pn8/z, \[x0, x30, lsl #3\]
|
||||
[^:]+: a01f6001 ldnt1d {z0\.d-z1\.d}, pn8/z, \[x0, xzr, lsl #3\]
|
||||
[^:]+: a003674f ldnt1d {z14\.d-z15\.d}, pn9/z, \[x26, x3, lsl #3\]
|
||||
[^:]+: a001e001 ldnt1d {z0\.d-z3\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a001e001 ldnt1d {z0\.d-z3\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a001e001 ldnt1d {z0\.d-z3\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a001e01d ldnt1d {z28\.d-z31\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a001fc01 ldnt1d {z0\.d-z3\.d}, pn15/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a001e3c1 ldnt1d {z0\.d-z3\.d}, pn8/z, \[x30, x1, lsl #3\]
|
||||
[^:]+: a001e3e1 ldnt1d {z0\.d-z3\.d}, pn8/z, \[sp, x1, lsl #3\]
|
||||
[^:]+: a01ee001 ldnt1d {z0\.d-z3\.d}, pn8/z, \[x0, x30, lsl #3\]
|
||||
[^:]+: a01fe001 ldnt1d {z0\.d-z3\.d}, pn8/z, \[x0, xzr, lsl #3\]
|
||||
[^:]+: a001ef69 ldnt1d {z8\.d-z11\.d}, pn11/z, \[x27, x1, lsl #3\]
|
||||
[^:]+: a1016008 ldnt1d {z0\.d, z8\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1016008 ldnt1d {z0\.d, z8\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1016008 ldnt1d {z0\.d, z8\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1016009 ldnt1d {z1\.d, z9\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a101600a ldnt1d {z2\.d, z10\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a101600b ldnt1d {z3\.d, z11\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a101600c ldnt1d {z4\.d, z12\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a101600d ldnt1d {z5\.d, z13\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a101600e ldnt1d {z6\.d, z14\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a101600f ldnt1d {z7\.d, z15\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1016018 ldnt1d {z16\.d, z24\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1016019 ldnt1d {z17\.d, z25\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a101601a ldnt1d {z18\.d, z26\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a101601b ldnt1d {z19\.d, z27\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a101601c ldnt1d {z20\.d, z28\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a101601d ldnt1d {z21\.d, z29\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a101601e ldnt1d {z22\.d, z30\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a101601f ldnt1d {z23\.d, z31\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1017c08 ldnt1d {z0\.d, z8\.d}, pn15/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a10163c8 ldnt1d {z0\.d, z8\.d}, pn8/z, \[x30, x1, lsl #3\]
|
||||
[^:]+: a10163e8 ldnt1d {z0\.d, z8\.d}, pn8/z, \[sp, x1, lsl #3\]
|
||||
[^:]+: a11e6008 ldnt1d {z0\.d, z8\.d}, pn8/z, \[x0, x30, lsl #3\]
|
||||
[^:]+: a11f6008 ldnt1d {z0\.d, z8\.d}, pn8/z, \[x0, xzr, lsl #3\]
|
||||
[^:]+: a11879ed ldnt1d {z5\.d, z13\.d}, pn14/z, \[x15, x24, lsl #3\]
|
||||
[^:]+: a101e008 ldnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a101e008 ldnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a101e008 ldnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a101e009 ldnt1d {z1\.d, z5\.d, z9\.d, z13\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a101e00a ldnt1d {z2\.d, z6\.d, z10\.d, z14\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a101e00b ldnt1d {z3\.d, z7\.d, z11\.d, z15\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a101e018 ldnt1d {z16\.d, z20\.d, z24\.d, z28\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a101e019 ldnt1d {z17\.d, z21\.d, z25\.d, z29\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a101e01a ldnt1d {z18\.d, z22\.d, z26\.d, z30\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a101e01b ldnt1d {z19\.d, z23\.d, z27\.d, z31\.d}, pn8/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a101fc08 ldnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn15/z, \[x0, x1, lsl #3\]
|
||||
[^:]+: a101e3c8 ldnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x30, x1, lsl #3\]
|
||||
[^:]+: a101e3e8 ldnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[sp, x1, lsl #3\]
|
||||
[^:]+: a11ee008 ldnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x0, x30, lsl #3\]
|
||||
[^:]+: a11fe008 ldnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8/z, \[x0, xzr, lsl #3\]
|
||||
[^:]+: a106ec99 ldnt1d {z17\.d, z21\.d, z25\.d, z29\.d}, pn11/z, \[x4, x6, lsl #3\]
|
||||
[^:]+: a0606000 st1d {z0\.d-z1\.d}, pn8, \[x0\]
|
||||
[^:]+: a0606000 st1d {z0\.d-z1\.d}, pn8, \[x0\]
|
||||
[^:]+: a0606000 st1d {z0\.d-z1\.d}, pn8, \[x0\]
|
||||
[^:]+: a060601e st1d {z30\.d-z31\.d}, pn8, \[x0\]
|
||||
[^:]+: a0607c00 st1d {z0\.d-z1\.d}, pn15, \[x0\]
|
||||
[^:]+: a06063c0 st1d {z0\.d-z1\.d}, pn8, \[x30\]
|
||||
[^:]+: a06063e0 st1d {z0\.d-z1\.d}, pn8, \[sp\]
|
||||
[^:]+: a0686000 st1d {z0\.d-z1\.d}, pn8, \[x0, #-16, mul vl\]
|
||||
[^:]+: a0676000 st1d {z0\.d-z1\.d}, pn8, \[x0, #14, mul vl\]
|
||||
[^:]+: a06b756c st1d {z12\.d-z13\.d}, pn13, \[x11, #-10, mul vl\]
|
||||
[^:]+: a060e000 st1d {z0\.d-z3\.d}, pn8, \[x0\]
|
||||
[^:]+: a060e000 st1d {z0\.d-z3\.d}, pn8, \[x0\]
|
||||
[^:]+: a060e000 st1d {z0\.d-z3\.d}, pn8, \[x0\]
|
||||
[^:]+: a060e01c st1d {z28\.d-z31\.d}, pn8, \[x0\]
|
||||
[^:]+: a060fc00 st1d {z0\.d-z3\.d}, pn15, \[x0\]
|
||||
[^:]+: a060e3c0 st1d {z0\.d-z3\.d}, pn8, \[x30\]
|
||||
[^:]+: a060e3e0 st1d {z0\.d-z3\.d}, pn8, \[sp\]
|
||||
[^:]+: a068e000 st1d {z0\.d-z3\.d}, pn8, \[x0, #-32, mul vl\]
|
||||
[^:]+: a067e000 st1d {z0\.d-z3\.d}, pn8, \[x0, #28, mul vl\]
|
||||
[^:]+: a065ee28 st1d {z8\.d-z11\.d}, pn11, \[x17, #20, mul vl\]
|
||||
[^:]+: a1606000 st1d {z0\.d, z8\.d}, pn8, \[x0\]
|
||||
[^:]+: a1606000 st1d {z0\.d, z8\.d}, pn8, \[x0\]
|
||||
[^:]+: a1606000 st1d {z0\.d, z8\.d}, pn8, \[x0\]
|
||||
[^:]+: a1606001 st1d {z1\.d, z9\.d}, pn8, \[x0\]
|
||||
[^:]+: a1606002 st1d {z2\.d, z10\.d}, pn8, \[x0\]
|
||||
[^:]+: a1606003 st1d {z3\.d, z11\.d}, pn8, \[x0\]
|
||||
[^:]+: a1606004 st1d {z4\.d, z12\.d}, pn8, \[x0\]
|
||||
[^:]+: a1606005 st1d {z5\.d, z13\.d}, pn8, \[x0\]
|
||||
[^:]+: a1606006 st1d {z6\.d, z14\.d}, pn8, \[x0\]
|
||||
[^:]+: a1606007 st1d {z7\.d, z15\.d}, pn8, \[x0\]
|
||||
[^:]+: a1606010 st1d {z16\.d, z24\.d}, pn8, \[x0\]
|
||||
[^:]+: a1606011 st1d {z17\.d, z25\.d}, pn8, \[x0\]
|
||||
[^:]+: a1606012 st1d {z18\.d, z26\.d}, pn8, \[x0\]
|
||||
[^:]+: a1606013 st1d {z19\.d, z27\.d}, pn8, \[x0\]
|
||||
[^:]+: a1606014 st1d {z20\.d, z28\.d}, pn8, \[x0\]
|
||||
[^:]+: a1606015 st1d {z21\.d, z29\.d}, pn8, \[x0\]
|
||||
[^:]+: a1606016 st1d {z22\.d, z30\.d}, pn8, \[x0\]
|
||||
[^:]+: a1606017 st1d {z23\.d, z31\.d}, pn8, \[x0\]
|
||||
[^:]+: a1607c00 st1d {z0\.d, z8\.d}, pn15, \[x0\]
|
||||
[^:]+: a16063c0 st1d {z0\.d, z8\.d}, pn8, \[x30\]
|
||||
[^:]+: a16063e0 st1d {z0\.d, z8\.d}, pn8, \[sp\]
|
||||
[^:]+: a1686000 st1d {z0\.d, z8\.d}, pn8, \[x0, #-16, mul vl\]
|
||||
[^:]+: a1676000 st1d {z0\.d, z8\.d}, pn8, \[x0, #14, mul vl\]
|
||||
[^:]+: a1636ac3 st1d {z3\.d, z11\.d}, pn10, \[x22, #6, mul vl\]
|
||||
[^:]+: a160e000 st1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[x0\]
|
||||
[^:]+: a160e000 st1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[x0\]
|
||||
[^:]+: a160e000 st1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[x0\]
|
||||
[^:]+: a160e001 st1d {z1\.d, z5\.d, z9\.d, z13\.d}, pn8, \[x0\]
|
||||
[^:]+: a160e002 st1d {z2\.d, z6\.d, z10\.d, z14\.d}, pn8, \[x0\]
|
||||
[^:]+: a160e003 st1d {z3\.d, z7\.d, z11\.d, z15\.d}, pn8, \[x0\]
|
||||
[^:]+: a160e010 st1d {z16\.d, z20\.d, z24\.d, z28\.d}, pn8, \[x0\]
|
||||
[^:]+: a160e011 st1d {z17\.d, z21\.d, z25\.d, z29\.d}, pn8, \[x0\]
|
||||
[^:]+: a160e012 st1d {z18\.d, z22\.d, z26\.d, z30\.d}, pn8, \[x0\]
|
||||
[^:]+: a160e013 st1d {z19\.d, z23\.d, z27\.d, z31\.d}, pn8, \[x0\]
|
||||
[^:]+: a160fc00 st1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn15, \[x0\]
|
||||
[^:]+: a160e3c0 st1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[x30\]
|
||||
[^:]+: a160e3e0 st1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[sp\]
|
||||
[^:]+: a168e000 st1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[x0, #-32, mul vl\]
|
||||
[^:]+: a167e000 st1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[x0, #28, mul vl\]
|
||||
[^:]+: a162fba2 st1d {z2\.d, z6\.d, z10\.d, z14\.d}, pn14, \[x29, #8, mul vl\]
|
||||
[^:]+: a0216000 st1d {z0\.d-z1\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a0216000 st1d {z0\.d-z1\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a0216000 st1d {z0\.d-z1\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a021601e st1d {z30\.d-z31\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a0217c00 st1d {z0\.d-z1\.d}, pn15, \[x0, x1, lsl #3\]
|
||||
[^:]+: a02163c0 st1d {z0\.d-z1\.d}, pn8, \[x30, x1, lsl #3\]
|
||||
[^:]+: a02163e0 st1d {z0\.d-z1\.d}, pn8, \[sp, x1, lsl #3\]
|
||||
[^:]+: a03e6000 st1d {z0\.d-z1\.d}, pn8, \[x0, x30, lsl #3\]
|
||||
[^:]+: a03f6000 st1d {z0\.d-z1\.d}, pn8, \[x0, xzr, lsl #3\]
|
||||
[^:]+: a023674e st1d {z14\.d-z15\.d}, pn9, \[x26, x3, lsl #3\]
|
||||
[^:]+: a021e000 st1d {z0\.d-z3\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a021e000 st1d {z0\.d-z3\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a021e000 st1d {z0\.d-z3\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a021e01c st1d {z28\.d-z31\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a021fc00 st1d {z0\.d-z3\.d}, pn15, \[x0, x1, lsl #3\]
|
||||
[^:]+: a021e3c0 st1d {z0\.d-z3\.d}, pn8, \[x30, x1, lsl #3\]
|
||||
[^:]+: a021e3e0 st1d {z0\.d-z3\.d}, pn8, \[sp, x1, lsl #3\]
|
||||
[^:]+: a03ee000 st1d {z0\.d-z3\.d}, pn8, \[x0, x30, lsl #3\]
|
||||
[^:]+: a03fe000 st1d {z0\.d-z3\.d}, pn8, \[x0, xzr, lsl #3\]
|
||||
[^:]+: a021ef68 st1d {z8\.d-z11\.d}, pn11, \[x27, x1, lsl #3\]
|
||||
[^:]+: a1216000 st1d {z0\.d, z8\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1216000 st1d {z0\.d, z8\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1216000 st1d {z0\.d, z8\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1216001 st1d {z1\.d, z9\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1216002 st1d {z2\.d, z10\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1216003 st1d {z3\.d, z11\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1216004 st1d {z4\.d, z12\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1216005 st1d {z5\.d, z13\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1216006 st1d {z6\.d, z14\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1216007 st1d {z7\.d, z15\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1216010 st1d {z16\.d, z24\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1216011 st1d {z17\.d, z25\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1216012 st1d {z18\.d, z26\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1216013 st1d {z19\.d, z27\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1216014 st1d {z20\.d, z28\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1216015 st1d {z21\.d, z29\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1216016 st1d {z22\.d, z30\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1216017 st1d {z23\.d, z31\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1217c00 st1d {z0\.d, z8\.d}, pn15, \[x0, x1, lsl #3\]
|
||||
[^:]+: a12163c0 st1d {z0\.d, z8\.d}, pn8, \[x30, x1, lsl #3\]
|
||||
[^:]+: a12163e0 st1d {z0\.d, z8\.d}, pn8, \[sp, x1, lsl #3\]
|
||||
[^:]+: a13e6000 st1d {z0\.d, z8\.d}, pn8, \[x0, x30, lsl #3\]
|
||||
[^:]+: a13f6000 st1d {z0\.d, z8\.d}, pn8, \[x0, xzr, lsl #3\]
|
||||
[^:]+: a13879e5 st1d {z5\.d, z13\.d}, pn14, \[x15, x24, lsl #3\]
|
||||
[^:]+: a121e000 st1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a121e000 st1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a121e000 st1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a121e001 st1d {z1\.d, z5\.d, z9\.d, z13\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a121e002 st1d {z2\.d, z6\.d, z10\.d, z14\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a121e003 st1d {z3\.d, z7\.d, z11\.d, z15\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a121e010 st1d {z16\.d, z20\.d, z24\.d, z28\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a121e011 st1d {z17\.d, z21\.d, z25\.d, z29\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a121e012 st1d {z18\.d, z22\.d, z26\.d, z30\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a121e013 st1d {z19\.d, z23\.d, z27\.d, z31\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a121fc00 st1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn15, \[x0, x1, lsl #3\]
|
||||
[^:]+: a121e3c0 st1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[x30, x1, lsl #3\]
|
||||
[^:]+: a121e3e0 st1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[sp, x1, lsl #3\]
|
||||
[^:]+: a13ee000 st1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[x0, x30, lsl #3\]
|
||||
[^:]+: a13fe000 st1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[x0, xzr, lsl #3\]
|
||||
[^:]+: a126ec91 st1d {z17\.d, z21\.d, z25\.d, z29\.d}, pn11, \[x4, x6, lsl #3\]
|
||||
[^:]+: a0606001 stnt1d {z0\.d-z1\.d}, pn8, \[x0\]
|
||||
[^:]+: a0606001 stnt1d {z0\.d-z1\.d}, pn8, \[x0\]
|
||||
[^:]+: a0606001 stnt1d {z0\.d-z1\.d}, pn8, \[x0\]
|
||||
[^:]+: a060601f stnt1d {z30\.d-z31\.d}, pn8, \[x0\]
|
||||
[^:]+: a0607c01 stnt1d {z0\.d-z1\.d}, pn15, \[x0\]
|
||||
[^:]+: a06063c1 stnt1d {z0\.d-z1\.d}, pn8, \[x30\]
|
||||
[^:]+: a06063e1 stnt1d {z0\.d-z1\.d}, pn8, \[sp\]
|
||||
[^:]+: a0686001 stnt1d {z0\.d-z1\.d}, pn8, \[x0, #-16, mul vl\]
|
||||
[^:]+: a0676001 stnt1d {z0\.d-z1\.d}, pn8, \[x0, #14, mul vl\]
|
||||
[^:]+: a06b756d stnt1d {z12\.d-z13\.d}, pn13, \[x11, #-10, mul vl\]
|
||||
[^:]+: a060e001 stnt1d {z0\.d-z3\.d}, pn8, \[x0\]
|
||||
[^:]+: a060e001 stnt1d {z0\.d-z3\.d}, pn8, \[x0\]
|
||||
[^:]+: a060e001 stnt1d {z0\.d-z3\.d}, pn8, \[x0\]
|
||||
[^:]+: a060e01d stnt1d {z28\.d-z31\.d}, pn8, \[x0\]
|
||||
[^:]+: a060fc01 stnt1d {z0\.d-z3\.d}, pn15, \[x0\]
|
||||
[^:]+: a060e3c1 stnt1d {z0\.d-z3\.d}, pn8, \[x30\]
|
||||
[^:]+: a060e3e1 stnt1d {z0\.d-z3\.d}, pn8, \[sp\]
|
||||
[^:]+: a068e001 stnt1d {z0\.d-z3\.d}, pn8, \[x0, #-32, mul vl\]
|
||||
[^:]+: a067e001 stnt1d {z0\.d-z3\.d}, pn8, \[x0, #28, mul vl\]
|
||||
[^:]+: a065ee29 stnt1d {z8\.d-z11\.d}, pn11, \[x17, #20, mul vl\]
|
||||
[^:]+: a1606008 stnt1d {z0\.d, z8\.d}, pn8, \[x0\]
|
||||
[^:]+: a1606008 stnt1d {z0\.d, z8\.d}, pn8, \[x0\]
|
||||
[^:]+: a1606008 stnt1d {z0\.d, z8\.d}, pn8, \[x0\]
|
||||
[^:]+: a1606009 stnt1d {z1\.d, z9\.d}, pn8, \[x0\]
|
||||
[^:]+: a160600a stnt1d {z2\.d, z10\.d}, pn8, \[x0\]
|
||||
[^:]+: a160600b stnt1d {z3\.d, z11\.d}, pn8, \[x0\]
|
||||
[^:]+: a160600c stnt1d {z4\.d, z12\.d}, pn8, \[x0\]
|
||||
[^:]+: a160600d stnt1d {z5\.d, z13\.d}, pn8, \[x0\]
|
||||
[^:]+: a160600e stnt1d {z6\.d, z14\.d}, pn8, \[x0\]
|
||||
[^:]+: a160600f stnt1d {z7\.d, z15\.d}, pn8, \[x0\]
|
||||
[^:]+: a1606018 stnt1d {z16\.d, z24\.d}, pn8, \[x0\]
|
||||
[^:]+: a1606019 stnt1d {z17\.d, z25\.d}, pn8, \[x0\]
|
||||
[^:]+: a160601a stnt1d {z18\.d, z26\.d}, pn8, \[x0\]
|
||||
[^:]+: a160601b stnt1d {z19\.d, z27\.d}, pn8, \[x0\]
|
||||
[^:]+: a160601c stnt1d {z20\.d, z28\.d}, pn8, \[x0\]
|
||||
[^:]+: a160601d stnt1d {z21\.d, z29\.d}, pn8, \[x0\]
|
||||
[^:]+: a160601e stnt1d {z22\.d, z30\.d}, pn8, \[x0\]
|
||||
[^:]+: a160601f stnt1d {z23\.d, z31\.d}, pn8, \[x0\]
|
||||
[^:]+: a1607c08 stnt1d {z0\.d, z8\.d}, pn15, \[x0\]
|
||||
[^:]+: a16063c8 stnt1d {z0\.d, z8\.d}, pn8, \[x30\]
|
||||
[^:]+: a16063e8 stnt1d {z0\.d, z8\.d}, pn8, \[sp\]
|
||||
[^:]+: a1686008 stnt1d {z0\.d, z8\.d}, pn8, \[x0, #-16, mul vl\]
|
||||
[^:]+: a1676008 stnt1d {z0\.d, z8\.d}, pn8, \[x0, #14, mul vl\]
|
||||
[^:]+: a1636acb stnt1d {z3\.d, z11\.d}, pn10, \[x22, #6, mul vl\]
|
||||
[^:]+: a160e008 stnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[x0\]
|
||||
[^:]+: a160e008 stnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[x0\]
|
||||
[^:]+: a160e008 stnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[x0\]
|
||||
[^:]+: a160e009 stnt1d {z1\.d, z5\.d, z9\.d, z13\.d}, pn8, \[x0\]
|
||||
[^:]+: a160e00a stnt1d {z2\.d, z6\.d, z10\.d, z14\.d}, pn8, \[x0\]
|
||||
[^:]+: a160e00b stnt1d {z3\.d, z7\.d, z11\.d, z15\.d}, pn8, \[x0\]
|
||||
[^:]+: a160e018 stnt1d {z16\.d, z20\.d, z24\.d, z28\.d}, pn8, \[x0\]
|
||||
[^:]+: a160e019 stnt1d {z17\.d, z21\.d, z25\.d, z29\.d}, pn8, \[x0\]
|
||||
[^:]+: a160e01a stnt1d {z18\.d, z22\.d, z26\.d, z30\.d}, pn8, \[x0\]
|
||||
[^:]+: a160e01b stnt1d {z19\.d, z23\.d, z27\.d, z31\.d}, pn8, \[x0\]
|
||||
[^:]+: a160fc08 stnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn15, \[x0\]
|
||||
[^:]+: a160e3c8 stnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[x30\]
|
||||
[^:]+: a160e3e8 stnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[sp\]
|
||||
[^:]+: a168e008 stnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[x0, #-32, mul vl\]
|
||||
[^:]+: a167e008 stnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[x0, #28, mul vl\]
|
||||
[^:]+: a162fbaa stnt1d {z2\.d, z6\.d, z10\.d, z14\.d}, pn14, \[x29, #8, mul vl\]
|
||||
[^:]+: a0216001 stnt1d {z0\.d-z1\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a0216001 stnt1d {z0\.d-z1\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a0216001 stnt1d {z0\.d-z1\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a021601f stnt1d {z30\.d-z31\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a0217c01 stnt1d {z0\.d-z1\.d}, pn15, \[x0, x1, lsl #3\]
|
||||
[^:]+: a02163c1 stnt1d {z0\.d-z1\.d}, pn8, \[x30, x1, lsl #3\]
|
||||
[^:]+: a02163e1 stnt1d {z0\.d-z1\.d}, pn8, \[sp, x1, lsl #3\]
|
||||
[^:]+: a03e6001 stnt1d {z0\.d-z1\.d}, pn8, \[x0, x30, lsl #3\]
|
||||
[^:]+: a03f6001 stnt1d {z0\.d-z1\.d}, pn8, \[x0, xzr, lsl #3\]
|
||||
[^:]+: a023674f stnt1d {z14\.d-z15\.d}, pn9, \[x26, x3, lsl #3\]
|
||||
[^:]+: a021e001 stnt1d {z0\.d-z3\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a021e001 stnt1d {z0\.d-z3\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a021e001 stnt1d {z0\.d-z3\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a021e01d stnt1d {z28\.d-z31\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a021fc01 stnt1d {z0\.d-z3\.d}, pn15, \[x0, x1, lsl #3\]
|
||||
[^:]+: a021e3c1 stnt1d {z0\.d-z3\.d}, pn8, \[x30, x1, lsl #3\]
|
||||
[^:]+: a021e3e1 stnt1d {z0\.d-z3\.d}, pn8, \[sp, x1, lsl #3\]
|
||||
[^:]+: a03ee001 stnt1d {z0\.d-z3\.d}, pn8, \[x0, x30, lsl #3\]
|
||||
[^:]+: a03fe001 stnt1d {z0\.d-z3\.d}, pn8, \[x0, xzr, lsl #3\]
|
||||
[^:]+: a021ef69 stnt1d {z8\.d-z11\.d}, pn11, \[x27, x1, lsl #3\]
|
||||
[^:]+: a1216008 stnt1d {z0\.d, z8\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1216008 stnt1d {z0\.d, z8\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1216008 stnt1d {z0\.d, z8\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1216009 stnt1d {z1\.d, z9\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a121600a stnt1d {z2\.d, z10\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a121600b stnt1d {z3\.d, z11\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a121600c stnt1d {z4\.d, z12\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a121600d stnt1d {z5\.d, z13\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a121600e stnt1d {z6\.d, z14\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a121600f stnt1d {z7\.d, z15\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1216018 stnt1d {z16\.d, z24\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1216019 stnt1d {z17\.d, z25\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a121601a stnt1d {z18\.d, z26\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a121601b stnt1d {z19\.d, z27\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a121601c stnt1d {z20\.d, z28\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a121601d stnt1d {z21\.d, z29\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a121601e stnt1d {z22\.d, z30\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a121601f stnt1d {z23\.d, z31\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a1217c08 stnt1d {z0\.d, z8\.d}, pn15, \[x0, x1, lsl #3\]
|
||||
[^:]+: a12163c8 stnt1d {z0\.d, z8\.d}, pn8, \[x30, x1, lsl #3\]
|
||||
[^:]+: a12163e8 stnt1d {z0\.d, z8\.d}, pn8, \[sp, x1, lsl #3\]
|
||||
[^:]+: a13e6008 stnt1d {z0\.d, z8\.d}, pn8, \[x0, x30, lsl #3\]
|
||||
[^:]+: a13f6008 stnt1d {z0\.d, z8\.d}, pn8, \[x0, xzr, lsl #3\]
|
||||
[^:]+: a13879ed stnt1d {z5\.d, z13\.d}, pn14, \[x15, x24, lsl #3\]
|
||||
[^:]+: a121e008 stnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a121e008 stnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a121e008 stnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a121e009 stnt1d {z1\.d, z5\.d, z9\.d, z13\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a121e00a stnt1d {z2\.d, z6\.d, z10\.d, z14\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a121e00b stnt1d {z3\.d, z7\.d, z11\.d, z15\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a121e018 stnt1d {z16\.d, z20\.d, z24\.d, z28\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a121e019 stnt1d {z17\.d, z21\.d, z25\.d, z29\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a121e01a stnt1d {z18\.d, z22\.d, z26\.d, z30\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a121e01b stnt1d {z19\.d, z23\.d, z27\.d, z31\.d}, pn8, \[x0, x1, lsl #3\]
|
||||
[^:]+: a121fc08 stnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn15, \[x0, x1, lsl #3\]
|
||||
[^:]+: a121e3c8 stnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[x30, x1, lsl #3\]
|
||||
[^:]+: a121e3e8 stnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[sp, x1, lsl #3\]
|
||||
[^:]+: a13ee008 stnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[x0, x30, lsl #3\]
|
||||
[^:]+: a13fe008 stnt1d {z0\.d, z4\.d, z8\.d, z12\.d}, pn8, \[x0, xzr, lsl #3\]
|
||||
[^:]+: a126ec99 stnt1d {z17\.d, z21\.d, z25\.d, z29\.d}, pn11, \[x4, x6, lsl #3\]
|
||||
511
gas/testsuite/gas/aarch64/sme2-3.s
Normal file
511
gas/testsuite/gas/aarch64/sme2-3.s
Normal file
@ -0,0 +1,511 @@
|
||||
ld1d { z0.d - z1.d }, pn8/z, [x0]
|
||||
ld1d { z0.d - z1.d }, pn8/z, [x0, #0, mul vl]
|
||||
LD1D { Z0.D - Z1.D }, PN8/Z, [X0]
|
||||
ld1d { z30.d - z31.d }, pn8/z, [x0]
|
||||
ld1d { z0.d - z1.d }, pn15/z, [x0]
|
||||
ld1d { z0.d - z1.d }, pn8/z, [x30]
|
||||
ld1d { z0.d - z1.d }, pn8/z, [sp]
|
||||
ld1d { z0.d - z1.d }, pn8/z, [x0, #-16, mul vl]
|
||||
ld1d { z0.d - z1.d }, pn8/z, [x0, #14, mul vl]
|
||||
ld1d { z12.d - z13.d }, pn13/z, [x11, #-10, mul vl]
|
||||
|
||||
ld1d { z0.d - z3.d }, pn8/z, [x0]
|
||||
ld1d { z0.d - z3.d }, pn8/z, [x0, #0, mul vl]
|
||||
LD1D { Z0.D - Z3.D }, PN8/Z, [X0]
|
||||
ld1d { z28.d - z31.d }, pn8/z, [x0]
|
||||
ld1d { z0.d - z3.d }, pn15/z, [x0]
|
||||
ld1d { z0.d - z3.d }, pn8/z, [x30]
|
||||
ld1d { z0.d - z3.d }, pn8/z, [sp]
|
||||
ld1d { z0.d - z3.d }, pn8/z, [x0, #-32, mul vl]
|
||||
ld1d { z0.d - z3.d }, pn8/z, [x0, #28, mul vl]
|
||||
ld1d { z8.d - z11.d }, pn11/z, [x17, #20, mul vl]
|
||||
|
||||
ld1d { z0.d, z8.d }, pn8/z, [x0]
|
||||
ld1d { z0.d, z8.d }, pn8/z, [x0, #0, mul vl]
|
||||
LD1D { Z0.D, Z8.D }, PN8/Z, [X0]
|
||||
ld1d { z1.d, z9.d }, pn8/z, [x0]
|
||||
ld1d { z2.d, z10.d }, pn8/z, [x0]
|
||||
ld1d { z3.d, z11.d }, pn8/z, [x0]
|
||||
ld1d { z4.d, z12.d }, pn8/z, [x0]
|
||||
ld1d { z5.d, z13.d }, pn8/z, [x0]
|
||||
ld1d { z6.d, z14.d }, pn8/z, [x0]
|
||||
ld1d { z7.d, z15.d }, pn8/z, [x0]
|
||||
ld1d { z16.d, z24.d }, pn8/z, [x0]
|
||||
ld1d { z17.d, z25.d }, pn8/z, [x0]
|
||||
ld1d { z18.d, z26.d }, pn8/z, [x0]
|
||||
ld1d { z19.d, z27.d }, pn8/z, [x0]
|
||||
ld1d { z20.d, z28.d }, pn8/z, [x0]
|
||||
ld1d { z21.d, z29.d }, pn8/z, [x0]
|
||||
ld1d { z22.d, z30.d }, pn8/z, [x0]
|
||||
ld1d { z23.d, z31.d }, pn8/z, [x0]
|
||||
ld1d { z0.d, z8.d }, pn15/z, [x0]
|
||||
ld1d { z0.d, z8.d }, pn8/z, [x30]
|
||||
ld1d { z0.d, z8.d }, pn8/z, [sp]
|
||||
ld1d { z0.d, z8.d }, pn8/z, [x0, #-16, mul vl]
|
||||
ld1d { z0.d, z8.d }, pn8/z, [x0, #14, mul vl]
|
||||
ld1d { z3.d, z11.d }, pn10/z, [x22, #6, mul vl]
|
||||
|
||||
ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0]
|
||||
ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, #0, mul vl]
|
||||
LD1D { Z0.D, Z4.D, Z8.D, Z12.D }, PN8/Z, [X0]
|
||||
ld1d { z1.d, z5.d, z9.d, z13.d }, pn8/z, [x0]
|
||||
ld1d { z2.d, z6.d, z10.d, z14.d }, pn8/z, [x0]
|
||||
ld1d { z3.d, z7.d, z11.d, z15.d }, pn8/z, [x0]
|
||||
ld1d { z16.d, z20.d, z24.d, z28.d }, pn8/z, [x0]
|
||||
ld1d { z17.d, z21.d, z25.d, z29.d }, pn8/z, [x0]
|
||||
ld1d { z18.d, z22.d, z26.d, z30.d }, pn8/z, [x0]
|
||||
ld1d { z19.d, z23.d, z27.d, z31.d }, pn8/z, [x0]
|
||||
ld1d { z0.d, z4.d, z8.d, z12.d }, pn15/z, [x0]
|
||||
ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x30]
|
||||
ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [sp]
|
||||
ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, #-32, mul vl]
|
||||
ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, #28, mul vl]
|
||||
ld1d { z2.d, z6.d, z10.d, z14.d }, pn14/z, [x29, #8, mul vl]
|
||||
|
||||
ld1d { z0.d - z1.d }, pn8/z, [x0, x1, lsl 3]
|
||||
ld1d { z0.d - z1.d }, pn8/z, [x0, x1, lsl #3]
|
||||
LD1D { Z0.D - Z1.D }, PN8/Z, [X0, X1, LSL #3]
|
||||
ld1d { z30.d - z31.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z0.d - z1.d }, pn15/z, [x0, x1, lsl #3]
|
||||
ld1d { z0.d - z1.d }, pn8/z, [x30, x1, lsl #3]
|
||||
ld1d { z0.d - z1.d }, pn8/z, [sp, x1, lsl #3]
|
||||
ld1d { z0.d - z1.d }, pn8/z, [x0, x30, lsl #3]
|
||||
ld1d { z0.d - z1.d }, pn8/z, [x0, xzr, lsl #3]
|
||||
ld1d { z14.d - z15.d }, pn9/z, [x26, x3, lsl #3]
|
||||
|
||||
ld1d { z0.d - z3.d }, pn8/z, [x0, x1, lsl 3]
|
||||
ld1d { z0.d - z3.d }, pn8/z, [x0, x1, lsl #3]
|
||||
LD1D { Z0.D - Z3.D }, PN8/Z, [X0, X1, LSL #3]
|
||||
ld1d { z28.d - z31.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z0.d - z3.d }, pn15/z, [x0, x1, lsl #3]
|
||||
ld1d { z0.d - z3.d }, pn8/z, [x30, x1, lsl #3]
|
||||
ld1d { z0.d - z3.d }, pn8/z, [sp, x1, lsl #3]
|
||||
ld1d { z0.d - z3.d }, pn8/z, [x0, x30, lsl #3]
|
||||
ld1d { z0.d - z3.d }, pn8/z, [x0, xzr, lsl #3]
|
||||
ld1d { z8.d - z11.d }, pn11/z, [x27, x1, lsl #3]
|
||||
|
||||
ld1d { z0.d, z8.d }, pn8/z, [x0, x1, lsl 3]
|
||||
ld1d { z0.d, z8.d }, pn8/z, [x0, x1, lsl #3]
|
||||
LD1D { Z0.D, Z8.D }, PN8/Z, [X0, X1, LSL #3]
|
||||
ld1d { z1.d, z9.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z2.d, z10.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z3.d, z11.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z4.d, z12.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z5.d, z13.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z6.d, z14.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z7.d, z15.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z16.d, z24.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z17.d, z25.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z18.d, z26.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z19.d, z27.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z20.d, z28.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z21.d, z29.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z22.d, z30.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z23.d, z31.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z0.d, z8.d }, pn15/z, [x0, x1, lsl #3]
|
||||
ld1d { z0.d, z8.d }, pn8/z, [x30, x1, lsl #3]
|
||||
ld1d { z0.d, z8.d }, pn8/z, [sp, x1, lsl #3]
|
||||
ld1d { z0.d, z8.d }, pn8/z, [x0, x30, lsl #3]
|
||||
ld1d { z0.d, z8.d }, pn8/z, [x0, xzr, lsl #3]
|
||||
ld1d { z5.d, z13.d }, pn14/z, [x15, x24, lsl #3]
|
||||
|
||||
ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, x1, lsl 3]
|
||||
ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, x1, lsl #3]
|
||||
LD1D { Z0.D, Z4.D, Z8.D, Z12.D }, PN8/Z, [X0, X1, LSL #3]
|
||||
ld1d { z1.d, z5.d, z9.d, z13.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z2.d, z6.d, z10.d, z14.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z3.d, z7.d, z11.d, z15.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z16.d, z20.d, z24.d, z28.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z17.d, z21.d, z25.d, z29.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z18.d, z22.d, z26.d, z30.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z19.d, z23.d, z27.d, z31.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1d { z0.d, z4.d, z8.d, z12.d }, pn15/z, [x0, x1, lsl #3]
|
||||
ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x30, x1, lsl #3]
|
||||
ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [sp, x1, lsl #3]
|
||||
ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, x30, lsl #3]
|
||||
ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, xzr, lsl #3]
|
||||
ld1d { z17.d, z21.d, z25.d, z29.d }, pn11/z, [x4, x6, lsl #3]
|
||||
|
||||
ldnt1d { z0.d - z1.d }, pn8/z, [x0]
|
||||
ldnt1d { z0.d - z1.d }, pn8/z, [x0, #0, mul vl]
|
||||
LDNT1D { Z0.D - Z1.D }, PN8/Z, [X0]
|
||||
ldnt1d { z30.d - z31.d }, pn8/z, [x0]
|
||||
ldnt1d { z0.d - z1.d }, pn15/z, [x0]
|
||||
ldnt1d { z0.d - z1.d }, pn8/z, [x30]
|
||||
ldnt1d { z0.d - z1.d }, pn8/z, [sp]
|
||||
ldnt1d { z0.d - z1.d }, pn8/z, [x0, #-16, mul vl]
|
||||
ldnt1d { z0.d - z1.d }, pn8/z, [x0, #14, mul vl]
|
||||
ldnt1d { z12.d - z13.d }, pn13/z, [x11, #-10, mul vl]
|
||||
|
||||
ldnt1d { z0.d - z3.d }, pn8/z, [x0]
|
||||
ldnt1d { z0.d - z3.d }, pn8/z, [x0, #0, mul vl]
|
||||
LDNT1D { Z0.D - Z3.D }, PN8/Z, [X0]
|
||||
ldnt1d { z28.d - z31.d }, pn8/z, [x0]
|
||||
ldnt1d { z0.d - z3.d }, pn15/z, [x0]
|
||||
ldnt1d { z0.d - z3.d }, pn8/z, [x30]
|
||||
ldnt1d { z0.d - z3.d }, pn8/z, [sp]
|
||||
ldnt1d { z0.d - z3.d }, pn8/z, [x0, #-32, mul vl]
|
||||
ldnt1d { z0.d - z3.d }, pn8/z, [x0, #28, mul vl]
|
||||
ldnt1d { z8.d - z11.d }, pn11/z, [x17, #20, mul vl]
|
||||
|
||||
ldnt1d { z0.d, z8.d }, pn8/z, [x0]
|
||||
ldnt1d { z0.d, z8.d }, pn8/z, [x0, #0, mul vl]
|
||||
LDNT1D { Z0.D, Z8.D }, PN8/Z, [X0]
|
||||
ldnt1d { z1.d, z9.d }, pn8/z, [x0]
|
||||
ldnt1d { z2.d, z10.d }, pn8/z, [x0]
|
||||
ldnt1d { z3.d, z11.d }, pn8/z, [x0]
|
||||
ldnt1d { z4.d, z12.d }, pn8/z, [x0]
|
||||
ldnt1d { z5.d, z13.d }, pn8/z, [x0]
|
||||
ldnt1d { z6.d, z14.d }, pn8/z, [x0]
|
||||
ldnt1d { z7.d, z15.d }, pn8/z, [x0]
|
||||
ldnt1d { z16.d, z24.d }, pn8/z, [x0]
|
||||
ldnt1d { z17.d, z25.d }, pn8/z, [x0]
|
||||
ldnt1d { z18.d, z26.d }, pn8/z, [x0]
|
||||
ldnt1d { z19.d, z27.d }, pn8/z, [x0]
|
||||
ldnt1d { z20.d, z28.d }, pn8/z, [x0]
|
||||
ldnt1d { z21.d, z29.d }, pn8/z, [x0]
|
||||
ldnt1d { z22.d, z30.d }, pn8/z, [x0]
|
||||
ldnt1d { z23.d, z31.d }, pn8/z, [x0]
|
||||
ldnt1d { z0.d, z8.d }, pn15/z, [x0]
|
||||
ldnt1d { z0.d, z8.d }, pn8/z, [x30]
|
||||
ldnt1d { z0.d, z8.d }, pn8/z, [sp]
|
||||
ldnt1d { z0.d, z8.d }, pn8/z, [x0, #-16, mul vl]
|
||||
ldnt1d { z0.d, z8.d }, pn8/z, [x0, #14, mul vl]
|
||||
ldnt1d { z3.d, z11.d }, pn10/z, [x22, #6, mul vl]
|
||||
|
||||
ldnt1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0]
|
||||
ldnt1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, #0, mul vl]
|
||||
LDNT1D { Z0.D, Z4.D, Z8.D, Z12.D }, PN8/Z, [X0]
|
||||
ldnt1d { z1.d, z5.d, z9.d, z13.d }, pn8/z, [x0]
|
||||
ldnt1d { z2.d, z6.d, z10.d, z14.d }, pn8/z, [x0]
|
||||
ldnt1d { z3.d, z7.d, z11.d, z15.d }, pn8/z, [x0]
|
||||
ldnt1d { z16.d, z20.d, z24.d, z28.d }, pn8/z, [x0]
|
||||
ldnt1d { z17.d, z21.d, z25.d, z29.d }, pn8/z, [x0]
|
||||
ldnt1d { z18.d, z22.d, z26.d, z30.d }, pn8/z, [x0]
|
||||
ldnt1d { z19.d, z23.d, z27.d, z31.d }, pn8/z, [x0]
|
||||
ldnt1d { z0.d, z4.d, z8.d, z12.d }, pn15/z, [x0]
|
||||
ldnt1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x30]
|
||||
ldnt1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [sp]
|
||||
ldnt1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, #-32, mul vl]
|
||||
ldnt1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, #28, mul vl]
|
||||
ldnt1d { z2.d, z6.d, z10.d, z14.d }, pn14/z, [x29, #8, mul vl]
|
||||
|
||||
ldnt1d { z0.d - z1.d }, pn8/z, [x0, x1, lsl 3]
|
||||
ldnt1d { z0.d - z1.d }, pn8/z, [x0, x1, lsl #3]
|
||||
LDNT1D { Z0.D - Z1.D }, PN8/Z, [X0, X1, LSL #3]
|
||||
ldnt1d { z30.d - z31.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ldnt1d { z0.d - z1.d }, pn15/z, [x0, x1, lsl #3]
|
||||
ldnt1d { z0.d - z1.d }, pn8/z, [x30, x1, lsl #3]
|
||||
ldnt1d { z0.d - z1.d }, pn8/z, [sp, x1, lsl #3]
|
||||
ldnt1d { z0.d - z1.d }, pn8/z, [x0, x30, lsl #3]
|
||||
ldnt1d { z0.d - z1.d }, pn8/z, [x0, xzr, lsl #3]
|
||||
ldnt1d { z14.d - z15.d }, pn9/z, [x26, x3, lsl #3]
|
||||
|
||||
ldnt1d { z0.d - z3.d }, pn8/z, [x0, x1, lsl 3]
|
||||
ldnt1d { z0.d - z3.d }, pn8/z, [x0, x1, lsl #3]
|
||||
LDNT1D { Z0.D - Z3.D }, PN8/Z, [X0, X1, LSL #3]
|
||||
ldnt1d { z28.d - z31.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ldnt1d { z0.d - z3.d }, pn15/z, [x0, x1, lsl #3]
|
||||
ldnt1d { z0.d - z3.d }, pn8/z, [x30, x1, lsl #3]
|
||||
ldnt1d { z0.d - z3.d }, pn8/z, [sp, x1, lsl #3]
|
||||
ldnt1d { z0.d - z3.d }, pn8/z, [x0, x30, lsl #3]
|
||||
ldnt1d { z0.d - z3.d }, pn8/z, [x0, xzr, lsl #3]
|
||||
ldnt1d { z8.d - z11.d }, pn11/z, [x27, x1, lsl #3]
|
||||
|
||||
ldnt1d { z0.d, z8.d }, pn8/z, [x0, x1, lsl 3]
|
||||
ldnt1d { z0.d, z8.d }, pn8/z, [x0, x1, lsl #3]
|
||||
LDNT1D { Z0.D, Z8.D }, PN8/Z, [X0, X1, LSL #3]
|
||||
ldnt1d { z1.d, z9.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ldnt1d { z2.d, z10.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ldnt1d { z3.d, z11.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ldnt1d { z4.d, z12.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ldnt1d { z5.d, z13.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ldnt1d { z6.d, z14.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ldnt1d { z7.d, z15.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ldnt1d { z16.d, z24.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ldnt1d { z17.d, z25.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ldnt1d { z18.d, z26.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ldnt1d { z19.d, z27.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ldnt1d { z20.d, z28.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ldnt1d { z21.d, z29.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ldnt1d { z22.d, z30.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ldnt1d { z23.d, z31.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ldnt1d { z0.d, z8.d }, pn15/z, [x0, x1, lsl #3]
|
||||
ldnt1d { z0.d, z8.d }, pn8/z, [x30, x1, lsl #3]
|
||||
ldnt1d { z0.d, z8.d }, pn8/z, [sp, x1, lsl #3]
|
||||
ldnt1d { z0.d, z8.d }, pn8/z, [x0, x30, lsl #3]
|
||||
ldnt1d { z0.d, z8.d }, pn8/z, [x0, xzr, lsl #3]
|
||||
ldnt1d { z5.d, z13.d }, pn14/z, [x15, x24, lsl #3]
|
||||
|
||||
ldnt1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, x1, lsl 3]
|
||||
ldnt1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, x1, lsl #3]
|
||||
LDNT1D { Z0.D, Z4.D, Z8.D, Z12.D }, PN8/Z, [X0, X1, LSL #3]
|
||||
ldnt1d { z1.d, z5.d, z9.d, z13.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ldnt1d { z2.d, z6.d, z10.d, z14.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ldnt1d { z3.d, z7.d, z11.d, z15.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ldnt1d { z16.d, z20.d, z24.d, z28.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ldnt1d { z17.d, z21.d, z25.d, z29.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ldnt1d { z18.d, z22.d, z26.d, z30.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ldnt1d { z19.d, z23.d, z27.d, z31.d }, pn8/z, [x0, x1, lsl #3]
|
||||
ldnt1d { z0.d, z4.d, z8.d, z12.d }, pn15/z, [x0, x1, lsl #3]
|
||||
ldnt1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x30, x1, lsl #3]
|
||||
ldnt1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [sp, x1, lsl #3]
|
||||
ldnt1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, x30, lsl #3]
|
||||
ldnt1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, xzr, lsl #3]
|
||||
ldnt1d { z17.d, z21.d, z25.d, z29.d }, pn11/z, [x4, x6, lsl #3]
|
||||
|
||||
st1d { z0.d - z1.d }, pn8, [x0]
|
||||
st1d { z0.d - z1.d }, pn8, [x0, #0, mul vl]
|
||||
ST1D { Z0.D - Z1.D }, PN8, [X0]
|
||||
st1d { z30.d - z31.d }, pn8, [x0]
|
||||
st1d { z0.d - z1.d }, pn15, [x0]
|
||||
st1d { z0.d - z1.d }, pn8, [x30]
|
||||
st1d { z0.d - z1.d }, pn8, [sp]
|
||||
st1d { z0.d - z1.d }, pn8, [x0, #-16, mul vl]
|
||||
st1d { z0.d - z1.d }, pn8, [x0, #14, mul vl]
|
||||
st1d { z12.d - z13.d }, pn13, [x11, #-10, mul vl]
|
||||
|
||||
st1d { z0.d - z3.d }, pn8, [x0]
|
||||
st1d { z0.d - z3.d }, pn8, [x0, #0, mul vl]
|
||||
ST1D { Z0.D - Z3.D }, PN8, [X0]
|
||||
st1d { z28.d - z31.d }, pn8, [x0]
|
||||
st1d { z0.d - z3.d }, pn15, [x0]
|
||||
st1d { z0.d - z3.d }, pn8, [x30]
|
||||
st1d { z0.d - z3.d }, pn8, [sp]
|
||||
st1d { z0.d - z3.d }, pn8, [x0, #-32, mul vl]
|
||||
st1d { z0.d - z3.d }, pn8, [x0, #28, mul vl]
|
||||
st1d { z8.d - z11.d }, pn11, [x17, #20, mul vl]
|
||||
|
||||
st1d { z0.d, z8.d }, pn8, [x0]
|
||||
st1d { z0.d, z8.d }, pn8, [x0, #0, mul vl]
|
||||
ST1D { Z0.D, Z8.D }, PN8, [X0]
|
||||
st1d { z1.d, z9.d }, pn8, [x0]
|
||||
st1d { z2.d, z10.d }, pn8, [x0]
|
||||
st1d { z3.d, z11.d }, pn8, [x0]
|
||||
st1d { z4.d, z12.d }, pn8, [x0]
|
||||
st1d { z5.d, z13.d }, pn8, [x0]
|
||||
st1d { z6.d, z14.d }, pn8, [x0]
|
||||
st1d { z7.d, z15.d }, pn8, [x0]
|
||||
st1d { z16.d, z24.d }, pn8, [x0]
|
||||
st1d { z17.d, z25.d }, pn8, [x0]
|
||||
st1d { z18.d, z26.d }, pn8, [x0]
|
||||
st1d { z19.d, z27.d }, pn8, [x0]
|
||||
st1d { z20.d, z28.d }, pn8, [x0]
|
||||
st1d { z21.d, z29.d }, pn8, [x0]
|
||||
st1d { z22.d, z30.d }, pn8, [x0]
|
||||
st1d { z23.d, z31.d }, pn8, [x0]
|
||||
st1d { z0.d, z8.d }, pn15, [x0]
|
||||
st1d { z0.d, z8.d }, pn8, [x30]
|
||||
st1d { z0.d, z8.d }, pn8, [sp]
|
||||
st1d { z0.d, z8.d }, pn8, [x0, #-16, mul vl]
|
||||
st1d { z0.d, z8.d }, pn8, [x0, #14, mul vl]
|
||||
st1d { z3.d, z11.d }, pn10, [x22, #6, mul vl]
|
||||
|
||||
st1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0]
|
||||
st1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, #0, mul vl]
|
||||
ST1D { Z0.D, Z4.D, Z8.D, Z12.D }, PN8, [X0]
|
||||
st1d { z1.d, z5.d, z9.d, z13.d }, pn8, [x0]
|
||||
st1d { z2.d, z6.d, z10.d, z14.d }, pn8, [x0]
|
||||
st1d { z3.d, z7.d, z11.d, z15.d }, pn8, [x0]
|
||||
st1d { z16.d, z20.d, z24.d, z28.d }, pn8, [x0]
|
||||
st1d { z17.d, z21.d, z25.d, z29.d }, pn8, [x0]
|
||||
st1d { z18.d, z22.d, z26.d, z30.d }, pn8, [x0]
|
||||
st1d { z19.d, z23.d, z27.d, z31.d }, pn8, [x0]
|
||||
st1d { z0.d, z4.d, z8.d, z12.d }, pn15, [x0]
|
||||
st1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x30]
|
||||
st1d { z0.d, z4.d, z8.d, z12.d }, pn8, [sp]
|
||||
st1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, #-32, mul vl]
|
||||
st1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, #28, mul vl]
|
||||
st1d { z2.d, z6.d, z10.d, z14.d }, pn14, [x29, #8, mul vl]
|
||||
|
||||
st1d { z0.d - z1.d }, pn8, [x0, x1, lsl 3]
|
||||
st1d { z0.d - z1.d }, pn8, [x0, x1, lsl #3]
|
||||
ST1D { Z0.D - Z1.D }, PN8, [X0, X1, LSL #3]
|
||||
st1d { z30.d - z31.d }, pn8, [x0, x1, lsl #3]
|
||||
st1d { z0.d - z1.d }, pn15, [x0, x1, lsl #3]
|
||||
st1d { z0.d - z1.d }, pn8, [x30, x1, lsl #3]
|
||||
st1d { z0.d - z1.d }, pn8, [sp, x1, lsl #3]
|
||||
st1d { z0.d - z1.d }, pn8, [x0, x30, lsl #3]
|
||||
st1d { z0.d - z1.d }, pn8, [x0, xzr, lsl #3]
|
||||
st1d { z14.d - z15.d }, pn9, [x26, x3, lsl #3]
|
||||
|
||||
st1d { z0.d - z3.d }, pn8, [x0, x1, lsl 3]
|
||||
st1d { z0.d - z3.d }, pn8, [x0, x1, lsl #3]
|
||||
ST1D { Z0.D - Z3.D }, PN8, [X0, X1, LSL #3]
|
||||
st1d { z28.d - z31.d }, pn8, [x0, x1, lsl #3]
|
||||
st1d { z0.d - z3.d }, pn15, [x0, x1, lsl #3]
|
||||
st1d { z0.d - z3.d }, pn8, [x30, x1, lsl #3]
|
||||
st1d { z0.d - z3.d }, pn8, [sp, x1, lsl #3]
|
||||
st1d { z0.d - z3.d }, pn8, [x0, x30, lsl #3]
|
||||
st1d { z0.d - z3.d }, pn8, [x0, xzr, lsl #3]
|
||||
st1d { z8.d - z11.d }, pn11, [x27, x1, lsl #3]
|
||||
|
||||
st1d { z0.d, z8.d }, pn8, [x0, x1, lsl 3]
|
||||
st1d { z0.d, z8.d }, pn8, [x0, x1, lsl #3]
|
||||
ST1D { Z0.D, Z8.D }, PN8, [X0, X1, LSL #3]
|
||||
st1d { z1.d, z9.d }, pn8, [x0, x1, lsl #3]
|
||||
st1d { z2.d, z10.d }, pn8, [x0, x1, lsl #3]
|
||||
st1d { z3.d, z11.d }, pn8, [x0, x1, lsl #3]
|
||||
st1d { z4.d, z12.d }, pn8, [x0, x1, lsl #3]
|
||||
st1d { z5.d, z13.d }, pn8, [x0, x1, lsl #3]
|
||||
st1d { z6.d, z14.d }, pn8, [x0, x1, lsl #3]
|
||||
st1d { z7.d, z15.d }, pn8, [x0, x1, lsl #3]
|
||||
st1d { z16.d, z24.d }, pn8, [x0, x1, lsl #3]
|
||||
st1d { z17.d, z25.d }, pn8, [x0, x1, lsl #3]
|
||||
st1d { z18.d, z26.d }, pn8, [x0, x1, lsl #3]
|
||||
st1d { z19.d, z27.d }, pn8, [x0, x1, lsl #3]
|
||||
st1d { z20.d, z28.d }, pn8, [x0, x1, lsl #3]
|
||||
st1d { z21.d, z29.d }, pn8, [x0, x1, lsl #3]
|
||||
st1d { z22.d, z30.d }, pn8, [x0, x1, lsl #3]
|
||||
st1d { z23.d, z31.d }, pn8, [x0, x1, lsl #3]
|
||||
st1d { z0.d, z8.d }, pn15, [x0, x1, lsl #3]
|
||||
st1d { z0.d, z8.d }, pn8, [x30, x1, lsl #3]
|
||||
st1d { z0.d, z8.d }, pn8, [sp, x1, lsl #3]
|
||||
st1d { z0.d, z8.d }, pn8, [x0, x30, lsl #3]
|
||||
st1d { z0.d, z8.d }, pn8, [x0, xzr, lsl #3]
|
||||
st1d { z5.d, z13.d }, pn14, [x15, x24, lsl #3]
|
||||
|
||||
st1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, x1, lsl 3]
|
||||
st1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, x1, lsl #3]
|
||||
ST1D { Z0.D, Z4.D, Z8.D, Z12.D }, PN8, [X0, X1, LSL #3]
|
||||
st1d { z1.d, z5.d, z9.d, z13.d }, pn8, [x0, x1, lsl #3]
|
||||
st1d { z2.d, z6.d, z10.d, z14.d }, pn8, [x0, x1, lsl #3]
|
||||
st1d { z3.d, z7.d, z11.d, z15.d }, pn8, [x0, x1, lsl #3]
|
||||
st1d { z16.d, z20.d, z24.d, z28.d }, pn8, [x0, x1, lsl #3]
|
||||
st1d { z17.d, z21.d, z25.d, z29.d }, pn8, [x0, x1, lsl #3]
|
||||
st1d { z18.d, z22.d, z26.d, z30.d }, pn8, [x0, x1, lsl #3]
|
||||
st1d { z19.d, z23.d, z27.d, z31.d }, pn8, [x0, x1, lsl #3]
|
||||
st1d { z0.d, z4.d, z8.d, z12.d }, pn15, [x0, x1, lsl #3]
|
||||
st1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x30, x1, lsl #3]
|
||||
st1d { z0.d, z4.d, z8.d, z12.d }, pn8, [sp, x1, lsl #3]
|
||||
st1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, x30, lsl #3]
|
||||
st1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, xzr, lsl #3]
|
||||
st1d { z17.d, z21.d, z25.d, z29.d }, pn11, [x4, x6, lsl #3]
|
||||
|
||||
stnt1d { z0.d - z1.d }, pn8, [x0]
|
||||
stnt1d { z0.d - z1.d }, pn8, [x0, #0, mul vl]
|
||||
STNT1D { Z0.D - Z1.D }, PN8, [X0]
|
||||
stnt1d { z30.d - z31.d }, pn8, [x0]
|
||||
stnt1d { z0.d - z1.d }, pn15, [x0]
|
||||
stnt1d { z0.d - z1.d }, pn8, [x30]
|
||||
stnt1d { z0.d - z1.d }, pn8, [sp]
|
||||
stnt1d { z0.d - z1.d }, pn8, [x0, #-16, mul vl]
|
||||
stnt1d { z0.d - z1.d }, pn8, [x0, #14, mul vl]
|
||||
stnt1d { z12.d - z13.d }, pn13, [x11, #-10, mul vl]
|
||||
|
||||
stnt1d { z0.d - z3.d }, pn8, [x0]
|
||||
stnt1d { z0.d - z3.d }, pn8, [x0, #0, mul vl]
|
||||
STNT1D { Z0.D - Z3.D }, PN8, [X0]
|
||||
stnt1d { z28.d - z31.d }, pn8, [x0]
|
||||
stnt1d { z0.d - z3.d }, pn15, [x0]
|
||||
stnt1d { z0.d - z3.d }, pn8, [x30]
|
||||
stnt1d { z0.d - z3.d }, pn8, [sp]
|
||||
stnt1d { z0.d - z3.d }, pn8, [x0, #-32, mul vl]
|
||||
stnt1d { z0.d - z3.d }, pn8, [x0, #28, mul vl]
|
||||
stnt1d { z8.d - z11.d }, pn11, [x17, #20, mul vl]
|
||||
|
||||
stnt1d { z0.d, z8.d }, pn8, [x0]
|
||||
stnt1d { z0.d, z8.d }, pn8, [x0, #0, mul vl]
|
||||
STNT1D { Z0.D, Z8.D }, PN8, [X0]
|
||||
stnt1d { z1.d, z9.d }, pn8, [x0]
|
||||
stnt1d { z2.d, z10.d }, pn8, [x0]
|
||||
stnt1d { z3.d, z11.d }, pn8, [x0]
|
||||
stnt1d { z4.d, z12.d }, pn8, [x0]
|
||||
stnt1d { z5.d, z13.d }, pn8, [x0]
|
||||
stnt1d { z6.d, z14.d }, pn8, [x0]
|
||||
stnt1d { z7.d, z15.d }, pn8, [x0]
|
||||
stnt1d { z16.d, z24.d }, pn8, [x0]
|
||||
stnt1d { z17.d, z25.d }, pn8, [x0]
|
||||
stnt1d { z18.d, z26.d }, pn8, [x0]
|
||||
stnt1d { z19.d, z27.d }, pn8, [x0]
|
||||
stnt1d { z20.d, z28.d }, pn8, [x0]
|
||||
stnt1d { z21.d, z29.d }, pn8, [x0]
|
||||
stnt1d { z22.d, z30.d }, pn8, [x0]
|
||||
stnt1d { z23.d, z31.d }, pn8, [x0]
|
||||
stnt1d { z0.d, z8.d }, pn15, [x0]
|
||||
stnt1d { z0.d, z8.d }, pn8, [x30]
|
||||
stnt1d { z0.d, z8.d }, pn8, [sp]
|
||||
stnt1d { z0.d, z8.d }, pn8, [x0, #-16, mul vl]
|
||||
stnt1d { z0.d, z8.d }, pn8, [x0, #14, mul vl]
|
||||
stnt1d { z3.d, z11.d }, pn10, [x22, #6, mul vl]
|
||||
|
||||
stnt1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0]
|
||||
stnt1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, #0, mul vl]
|
||||
STNT1D { Z0.D, Z4.D, Z8.D, Z12.D }, PN8, [X0]
|
||||
stnt1d { z1.d, z5.d, z9.d, z13.d }, pn8, [x0]
|
||||
stnt1d { z2.d, z6.d, z10.d, z14.d }, pn8, [x0]
|
||||
stnt1d { z3.d, z7.d, z11.d, z15.d }, pn8, [x0]
|
||||
stnt1d { z16.d, z20.d, z24.d, z28.d }, pn8, [x0]
|
||||
stnt1d { z17.d, z21.d, z25.d, z29.d }, pn8, [x0]
|
||||
stnt1d { z18.d, z22.d, z26.d, z30.d }, pn8, [x0]
|
||||
stnt1d { z19.d, z23.d, z27.d, z31.d }, pn8, [x0]
|
||||
stnt1d { z0.d, z4.d, z8.d, z12.d }, pn15, [x0]
|
||||
stnt1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x30]
|
||||
stnt1d { z0.d, z4.d, z8.d, z12.d }, pn8, [sp]
|
||||
stnt1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, #-32, mul vl]
|
||||
stnt1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, #28, mul vl]
|
||||
stnt1d { z2.d, z6.d, z10.d, z14.d }, pn14, [x29, #8, mul vl]
|
||||
|
||||
stnt1d { z0.d - z1.d }, pn8, [x0, x1, lsl 3]
|
||||
stnt1d { z0.d - z1.d }, pn8, [x0, x1, lsl #3]
|
||||
STNT1D { Z0.D - Z1.D }, PN8, [X0, X1, LSL #3]
|
||||
stnt1d { z30.d - z31.d }, pn8, [x0, x1, lsl #3]
|
||||
stnt1d { z0.d - z1.d }, pn15, [x0, x1, lsl #3]
|
||||
stnt1d { z0.d - z1.d }, pn8, [x30, x1, lsl #3]
|
||||
stnt1d { z0.d - z1.d }, pn8, [sp, x1, lsl #3]
|
||||
stnt1d { z0.d - z1.d }, pn8, [x0, x30, lsl #3]
|
||||
stnt1d { z0.d - z1.d }, pn8, [x0, xzr, lsl #3]
|
||||
stnt1d { z14.d - z15.d }, pn9, [x26, x3, lsl #3]
|
||||
|
||||
stnt1d { z0.d - z3.d }, pn8, [x0, x1, lsl 3]
|
||||
stnt1d { z0.d - z3.d }, pn8, [x0, x1, lsl #3]
|
||||
STNT1D { Z0.D - Z3.D }, PN8, [X0, X1, LSL #3]
|
||||
stnt1d { z28.d - z31.d }, pn8, [x0, x1, lsl #3]
|
||||
stnt1d { z0.d - z3.d }, pn15, [x0, x1, lsl #3]
|
||||
stnt1d { z0.d - z3.d }, pn8, [x30, x1, lsl #3]
|
||||
stnt1d { z0.d - z3.d }, pn8, [sp, x1, lsl #3]
|
||||
stnt1d { z0.d - z3.d }, pn8, [x0, x30, lsl #3]
|
||||
stnt1d { z0.d - z3.d }, pn8, [x0, xzr, lsl #3]
|
||||
stnt1d { z8.d - z11.d }, pn11, [x27, x1, lsl #3]
|
||||
|
||||
stnt1d { z0.d, z8.d }, pn8, [x0, x1, lsl 3]
|
||||
stnt1d { z0.d, z8.d }, pn8, [x0, x1, lsl #3]
|
||||
STNT1D { Z0.D, Z8.D }, PN8, [X0, X1, LSL #3]
|
||||
stnt1d { z1.d, z9.d }, pn8, [x0, x1, lsl #3]
|
||||
stnt1d { z2.d, z10.d }, pn8, [x0, x1, lsl #3]
|
||||
stnt1d { z3.d, z11.d }, pn8, [x0, x1, lsl #3]
|
||||
stnt1d { z4.d, z12.d }, pn8, [x0, x1, lsl #3]
|
||||
stnt1d { z5.d, z13.d }, pn8, [x0, x1, lsl #3]
|
||||
stnt1d { z6.d, z14.d }, pn8, [x0, x1, lsl #3]
|
||||
stnt1d { z7.d, z15.d }, pn8, [x0, x1, lsl #3]
|
||||
stnt1d { z16.d, z24.d }, pn8, [x0, x1, lsl #3]
|
||||
stnt1d { z17.d, z25.d }, pn8, [x0, x1, lsl #3]
|
||||
stnt1d { z18.d, z26.d }, pn8, [x0, x1, lsl #3]
|
||||
stnt1d { z19.d, z27.d }, pn8, [x0, x1, lsl #3]
|
||||
stnt1d { z20.d, z28.d }, pn8, [x0, x1, lsl #3]
|
||||
stnt1d { z21.d, z29.d }, pn8, [x0, x1, lsl #3]
|
||||
stnt1d { z22.d, z30.d }, pn8, [x0, x1, lsl #3]
|
||||
stnt1d { z23.d, z31.d }, pn8, [x0, x1, lsl #3]
|
||||
stnt1d { z0.d, z8.d }, pn15, [x0, x1, lsl #3]
|
||||
stnt1d { z0.d, z8.d }, pn8, [x30, x1, lsl #3]
|
||||
stnt1d { z0.d, z8.d }, pn8, [sp, x1, lsl #3]
|
||||
stnt1d { z0.d, z8.d }, pn8, [x0, x30, lsl #3]
|
||||
stnt1d { z0.d, z8.d }, pn8, [x0, xzr, lsl #3]
|
||||
stnt1d { z5.d, z13.d }, pn14, [x15, x24, lsl #3]
|
||||
|
||||
stnt1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, x1, lsl 3]
|
||||
stnt1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, x1, lsl #3]
|
||||
STNT1D { Z0.D, Z4.D, Z8.D, Z12.D }, PN8, [X0, X1, LSL #3]
|
||||
stnt1d { z1.d, z5.d, z9.d, z13.d }, pn8, [x0, x1, lsl #3]
|
||||
stnt1d { z2.d, z6.d, z10.d, z14.d }, pn8, [x0, x1, lsl #3]
|
||||
stnt1d { z3.d, z7.d, z11.d, z15.d }, pn8, [x0, x1, lsl #3]
|
||||
stnt1d { z16.d, z20.d, z24.d, z28.d }, pn8, [x0, x1, lsl #3]
|
||||
stnt1d { z17.d, z21.d, z25.d, z29.d }, pn8, [x0, x1, lsl #3]
|
||||
stnt1d { z18.d, z22.d, z26.d, z30.d }, pn8, [x0, x1, lsl #3]
|
||||
stnt1d { z19.d, z23.d, z27.d, z31.d }, pn8, [x0, x1, lsl #3]
|
||||
stnt1d { z0.d, z4.d, z8.d, z12.d }, pn15, [x0, x1, lsl #3]
|
||||
stnt1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x30, x1, lsl #3]
|
||||
stnt1d { z0.d, z4.d, z8.d, z12.d }, pn8, [sp, x1, lsl #3]
|
||||
stnt1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, x30, lsl #3]
|
||||
stnt1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, xzr, lsl #3]
|
||||
stnt1d { z17.d, z21.d, z25.d, z29.d }, pn11, [x4, x6, lsl #3]
|
||||
3
gas/testsuite/gas/aarch64/sme2-4-invalid.d
Normal file
3
gas/testsuite/gas/aarch64/sme2-4-invalid.d
Normal file
@ -0,0 +1,3 @@
|
||||
#as: -march=armv8-a
|
||||
#source: sme2-4-invalid.s
|
||||
#error_output: sme2-4-invalid.l
|
||||
75
gas/testsuite/gas/aarch64/sme2-4-invalid.l
Normal file
75
gas/testsuite/gas/aarch64/sme2-4-invalid.l
Normal file
@ -0,0 +1,75 @@
|
||||
[^ :]+: Assembler messages:
|
||||
[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `ld1h 0,pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 2 -- `ld1h {z0\.h-z1\.h},0,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {z0\.h-z1\.h},pn8/z,0'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 1 -- `ld1h {z0\.h-z2\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1h {z1\.h-z2\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1h {z0\.h-z1\.h},p8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `ld1h {z0\.h-z1\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: ld1h {z0\.h-z1\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `ld1h {z0\.h-z1\.h},pn8/m,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: ld1h {z0\.h-z1\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `ld1h {z0\.h-z1\.h},pn8\.h,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: ld1h {z0\.h-z1\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1h {z0\.h-z1\.h},pn0/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1h {z0\.h-z1\.h},pn7/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1h {z0\.h-z1\.h},pn8/z,\[w0,w1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1h {z0\.h-z1\.h},pn8/z,\[xzr,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ld1h {z0\.h-z1\.h},pn8/z,\[sp,sp,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {z0\.h-z1\.h},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {z0\.h-z1\.h},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {z0\.h-z1\.h},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {z0\.h-z1\.h},pn8/z,\[x0,x1,lsl#4\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {z0\.h-z1\.h},pn8/z,\[x0,w1,sxtw#1\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {z0\.h-z1\.h},pn8/z,\[x0,w1,uxtw#1\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1h {z1\.h-z4\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1h {z2\.h-z5\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1h {z3\.h-z6\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1h {z0\.h-z3\.h},p8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `ld1h {z0\.h-z3\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: ld1h {z0\.h-z3\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `ld1h {z0\.h-z3\.h},pn8/m,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: ld1h {z0\.h-z3\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `ld1h {z0\.h-z3\.h},pn8\.h,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: ld1h {z0\.h-z3\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1h {z0\.h-z3\.h},pn0/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1h {z0\.h-z3\.h},pn7/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1h {z0\.h-z3\.h},pn8/z,\[w0,w1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1h {z0\.h-z3\.h},pn8/z,\[xzr,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ld1h {z0\.h-z3\.h},pn8/z,\[sp,sp,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {z0\.h-z3\.h},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {z0\.h-z3\.h},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {z0\.h-z3\.h},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {z0\.h-z3\.h},pn8/z,\[x0,x1,lsl#4\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {z0\.h-z3\.h},pn8/z,\[x0,w1,sxtw#1\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {z0\.h-z3\.h},pn8/z,\[x0,w1,uxtw#1\]'
|
||||
[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1h {z0\.h,z2\.h},pn8/z,\[x0,x1,lsl#1\]`
|
||||
[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1h {z0\.h,z3\.h},pn8/z,\[x0,x1,lsl#1\]`
|
||||
[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1h {z0\.h,z4\.h},pn8/z,\[x0,x1,lsl#1\]`
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1h {z8\.h,z16\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1h {z24\.h,z0\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1h {z8\.h,z0\.h},pn8/z,\[x0,x1,lsl#1\]`
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `ld1h {z0\.d,z8\.d},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: ld1h {z0\.h, z8\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1h {z0\.h,z8\.h},p8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1h {z0\.h,z8\.h},pn8/z,\[w0,w30,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1h {z0\.h,z8\.h},pn8/z,\[xzr,xzr,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ld1h {z0\.h,z8\.h},pn8/z,\[x0,sp,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {z0\.h,z8\.h},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1h {z4\.h,z8\.h,z12\.h,z16\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1h {z20\.h,z24\.h,z28\.h,z0\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `ld1h {z0\.d,z4\.d,z8\.d,z12\.d},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: ld1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},p8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[w0,w30,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[xzr,xzr,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,sp,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,x1,lsl#3\]'
|
||||
62
gas/testsuite/gas/aarch64/sme2-4-invalid.s
Normal file
62
gas/testsuite/gas/aarch64/sme2-4-invalid.s
Normal file
@ -0,0 +1,62 @@
|
||||
ld1h 0, pn8/z, [x0]
|
||||
ld1h { z0.h - z1.h }, 0, [x0]
|
||||
ld1h { z0.h - z1.h }, pn8/z, 0
|
||||
|
||||
ld1h { z0.h - z2.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z1.h - z2.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z0.h - z1.h }, p8/z, [x0, x1, lsl #1]
|
||||
ld1h { z0.h - z1.h }, pn8, [x0, x1, lsl #1]
|
||||
ld1h { z0.h - z1.h }, pn8/m, [x0, x1, lsl #1]
|
||||
ld1h { z0.h - z1.h }, pn8.h, [x0, x1, lsl #1]
|
||||
ld1h { z0.h - z1.h }, pn0/z, [x0, x1, lsl #1]
|
||||
ld1h { z0.h - z1.h }, pn7/z, [x0, x1, lsl #1]
|
||||
ld1h { z0.h - z1.h }, pn8/z, [w0, w1, lsl #1]
|
||||
ld1h { z0.h - z1.h }, pn8/z, [xzr, x1, lsl #1]
|
||||
ld1h { z0.h - z1.h }, pn8/z, [sp, sp, lsl #1]
|
||||
ld1h { z0.h - z1.h }, pn8/z, [x0, x1]
|
||||
ld1h { z0.h - z1.h }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1h { z0.h - z1.h }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1h { z0.h - z1.h }, pn8/z, [x0, x1, lsl #4]
|
||||
ld1h { z0.h - z1.h }, pn8/z, [x0, w1, sxtw #1]
|
||||
ld1h { z0.h - z1.h }, pn8/z, [x0, w1, uxtw #1]
|
||||
|
||||
ld1h { z1.h - z4.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z2.h - z5.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z3.h - z6.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z0.h - z3.h }, p8/z, [x0, x1, lsl #1]
|
||||
ld1h { z0.h - z3.h }, pn8, [x0, x1, lsl #1]
|
||||
ld1h { z0.h - z3.h }, pn8/m, [x0, x1, lsl #1]
|
||||
ld1h { z0.h - z3.h }, pn8.h, [x0, x1, lsl #1]
|
||||
ld1h { z0.h - z3.h }, pn0/z, [x0, x1, lsl #1]
|
||||
ld1h { z0.h - z3.h }, pn7/z, [x0, x1, lsl #1]
|
||||
ld1h { z0.h - z3.h }, pn8/z, [w0, w1, lsl #1]
|
||||
ld1h { z0.h - z3.h }, pn8/z, [xzr, x1, lsl #1]
|
||||
ld1h { z0.h - z3.h }, pn8/z, [sp, sp, lsl #1]
|
||||
ld1h { z0.h - z3.h }, pn8/z, [x0, x1]
|
||||
ld1h { z0.h - z3.h }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1h { z0.h - z3.h }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1h { z0.h - z3.h }, pn8/z, [x0, x1, lsl #4]
|
||||
ld1h { z0.h - z3.h }, pn8/z, [x0, w1, sxtw #1]
|
||||
ld1h { z0.h - z3.h }, pn8/z, [x0, w1, uxtw #1]
|
||||
|
||||
ld1h { z0.h, z2.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z0.h, z3.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z0.h, z4.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z8.h, z16.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z24.h, z0.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z8.h, z0.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z0.d, z8.d }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z0.h, z8.h }, p8/z, [x0, x1, lsl #1]
|
||||
ld1h { z0.h, z8.h }, pn8/z, [w0, w30, lsl #1]
|
||||
ld1h { z0.h, z8.h }, pn8/z, [xzr, xzr, lsl #1]
|
||||
ld1h { z0.h, z8.h }, pn8/z, [x0, sp, lsl #1]
|
||||
ld1h { z0.h, z8.h }, pn8/z, [x0, x1, lsl #2]
|
||||
|
||||
ld1h { z4.h, z8.h, z12.h, z16.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z20.h, z24.h, z28.h, z0.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z0.h, z4.h, z8.h, z12.h }, p8/z, [x0, x1, lsl #1]
|
||||
ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [w0, w30, lsl #1]
|
||||
ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [xzr, xzr, lsl #1]
|
||||
ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, sp, lsl #1]
|
||||
ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, x1, lsl #3]
|
||||
3
gas/testsuite/gas/aarch64/sme2-4-noarch.d
Normal file
3
gas/testsuite/gas/aarch64/sme2-4-noarch.d
Normal file
@ -0,0 +1,3 @@
|
||||
#as: -march=armv8-a+sme
|
||||
#source: sme2-4.s
|
||||
#error_output: sme2-4-noarch.l
|
||||
481
gas/testsuite/gas/aarch64/sme2-4-noarch.l
Normal file
481
gas/testsuite/gas/aarch64/sme2-4-noarch.l
Normal file
@ -0,0 +1,481 @@
|
||||
[^ :]+: Assembler messages:
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z1\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z1\.h},pn8/z,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {Z0\.H-Z1\.H},PN8/Z,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z30\.h-z31\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z1\.h},pn15/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z1\.h},pn8/z,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z1\.h},pn8/z,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z1\.h},pn8/z,\[x0,#-16,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z1\.h},pn8/z,\[x0,#14,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z12\.h-z13\.h},pn13/z,\[x11,#-10,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z3\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z3\.h},pn8/z,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {Z0\.H-Z3\.H},PN8/Z,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z28\.h-z31\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z3\.h},pn15/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z3\.h},pn8/z,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z3\.h},pn8/z,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z3\.h},pn8/z,\[x0,#-32,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z3\.h},pn8/z,\[x0,#28,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z8\.h-z11\.h},pn11/z,\[x17,#20,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z8\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z8\.h},pn8/z,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {Z0\.H,Z8\.H},PN8/Z,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z1\.h,z9\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z2\.h,z10\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z3\.h,z11\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z4\.h,z12\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z5\.h,z13\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z6\.h,z14\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z7\.h,z15\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z16\.h,z24\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z17\.h,z25\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z18\.h,z26\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z19\.h,z27\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z20\.h,z28\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z21\.h,z29\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z22\.h,z30\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z23\.h,z31\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z8\.h},pn15/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z8\.h},pn8/z,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z8\.h},pn8/z,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z8\.h},pn8/z,\[x0,#-16,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z8\.h},pn8/z,\[x0,#14,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z3\.h,z11\.h},pn10/z,\[x22,#6,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {Z0\.H,Z4\.H,Z8\.H,Z12\.H},PN8/Z,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z1\.h,z5\.h,z9\.h,z13\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z2\.h,z6\.h,z10\.h,z14\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z3\.h,z7\.h,z11\.h,z15\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z16\.h,z20\.h,z24\.h,z28\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z17\.h,z21\.h,z25\.h,z29\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z18\.h,z22\.h,z26\.h,z30\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z19\.h,z23\.h,z27\.h,z31\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},pn15/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,#-32,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,#28,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z2\.h,z6\.h,z10\.h,z14\.h},pn14/z,\[x29,#8,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z1\.h},pn8/z,\[x0,x1,lsl 1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z1\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {Z0\.H-Z1\.H},PN8/Z,\[X0,X1,LSL#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z30\.h-z31\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z1\.h},pn15/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z1\.h},pn8/z,\[x30,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z1\.h},pn8/z,\[sp,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z1\.h},pn8/z,\[x0,x30,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z1\.h},pn8/z,\[x0,xzr,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z14\.h-z15\.h},pn9/z,\[x26,x3,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z3\.h},pn8/z,\[x0,x1,lsl 1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z3\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {Z0\.H-Z3\.H},PN8/Z,\[X0,X1,LSL#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z28\.h-z31\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z3\.h},pn15/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z3\.h},pn8/z,\[x30,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z3\.h},pn8/z,\[sp,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z3\.h},pn8/z,\[x0,x30,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h-z3\.h},pn8/z,\[x0,xzr,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z8\.h-z11\.h},pn11/z,\[x27,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z8\.h},pn8/z,\[x0,x1,lsl 1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z8\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {Z0\.H,Z8\.H},PN8/Z,\[X0,X1,LSL#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z1\.h,z9\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z2\.h,z10\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z3\.h,z11\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z4\.h,z12\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z5\.h,z13\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z6\.h,z14\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z7\.h,z15\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z16\.h,z24\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z17\.h,z25\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z18\.h,z26\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z19\.h,z27\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z20\.h,z28\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z21\.h,z29\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z22\.h,z30\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z23\.h,z31\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z8\.h},pn15/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z8\.h},pn8/z,\[x30,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z8\.h},pn8/z,\[sp,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z8\.h},pn8/z,\[x0,x30,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z8\.h},pn8/z,\[x0,xzr,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z5\.h,z13\.h},pn14/z,\[x15,x24,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,x1,lsl 1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {Z0\.H,Z4\.H,Z8\.H,Z12\.H},PN8/Z,\[X0,X1,LSL#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z1\.h,z5\.h,z9\.h,z13\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z2\.h,z6\.h,z10\.h,z14\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z3\.h,z7\.h,z11\.h,z15\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z16\.h,z20\.h,z24\.h,z28\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z17\.h,z21\.h,z25\.h,z29\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z18\.h,z22\.h,z26\.h,z30\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z19\.h,z23\.h,z27\.h,z31\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},pn15/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x30,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[sp,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,x30,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,xzr,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1h {z17\.h,z21\.h,z25\.h,z29\.h},pn11/z,\[x4,x6,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z1\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z1\.h},pn8/z,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {Z0\.H-Z1\.H},PN8/Z,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z30\.h-z31\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z1\.h},pn15/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z1\.h},pn8/z,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z1\.h},pn8/z,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z1\.h},pn8/z,\[x0,#-16,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z1\.h},pn8/z,\[x0,#14,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z12\.h-z13\.h},pn13/z,\[x11,#-10,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z3\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z3\.h},pn8/z,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {Z0\.H-Z3\.H},PN8/Z,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z28\.h-z31\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z3\.h},pn15/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z3\.h},pn8/z,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z3\.h},pn8/z,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z3\.h},pn8/z,\[x0,#-32,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z3\.h},pn8/z,\[x0,#28,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z8\.h-z11\.h},pn11/z,\[x17,#20,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z8\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z8\.h},pn8/z,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {Z0\.H,Z8\.H},PN8/Z,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z1\.h,z9\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z2\.h,z10\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z3\.h,z11\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z4\.h,z12\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z5\.h,z13\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z6\.h,z14\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z7\.h,z15\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z16\.h,z24\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z17\.h,z25\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z18\.h,z26\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z19\.h,z27\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z20\.h,z28\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z21\.h,z29\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z22\.h,z30\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z23\.h,z31\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z8\.h},pn15/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z8\.h},pn8/z,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z8\.h},pn8/z,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z8\.h},pn8/z,\[x0,#-16,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z8\.h},pn8/z,\[x0,#14,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z3\.h,z11\.h},pn10/z,\[x22,#6,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {Z0\.H,Z4\.H,Z8\.H,Z12\.H},PN8/Z,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z1\.h,z5\.h,z9\.h,z13\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z2\.h,z6\.h,z10\.h,z14\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z3\.h,z7\.h,z11\.h,z15\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z16\.h,z20\.h,z24\.h,z28\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z17\.h,z21\.h,z25\.h,z29\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z18\.h,z22\.h,z26\.h,z30\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z19\.h,z23\.h,z27\.h,z31\.h},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn15/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,#-32,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,#28,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z2\.h,z6\.h,z10\.h,z14\.h},pn14/z,\[x29,#8,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z1\.h},pn8/z,\[x0,x1,lsl 1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z1\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {Z0\.H-Z1\.H},PN8/Z,\[X0,X1,LSL#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z30\.h-z31\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z1\.h},pn15/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z1\.h},pn8/z,\[x30,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z1\.h},pn8/z,\[sp,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z1\.h},pn8/z,\[x0,x30,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z1\.h},pn8/z,\[x0,xzr,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z14\.h-z15\.h},pn9/z,\[x26,x3,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z3\.h},pn8/z,\[x0,x1,lsl 1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z3\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {Z0\.H-Z3\.H},PN8/Z,\[X0,X1,LSL#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z28\.h-z31\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z3\.h},pn15/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z3\.h},pn8/z,\[x30,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z3\.h},pn8/z,\[sp,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z3\.h},pn8/z,\[x0,x30,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h-z3\.h},pn8/z,\[x0,xzr,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z8\.h-z11\.h},pn11/z,\[x27,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z8\.h},pn8/z,\[x0,x1,lsl 1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z8\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {Z0\.H,Z8\.H},PN8/Z,\[X0,X1,LSL#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z1\.h,z9\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z2\.h,z10\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z3\.h,z11\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z4\.h,z12\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z5\.h,z13\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z6\.h,z14\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z7\.h,z15\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z16\.h,z24\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z17\.h,z25\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z18\.h,z26\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z19\.h,z27\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z20\.h,z28\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z21\.h,z29\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z22\.h,z30\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z23\.h,z31\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z8\.h},pn15/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z8\.h},pn8/z,\[x30,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z8\.h},pn8/z,\[sp,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z8\.h},pn8/z,\[x0,x30,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z8\.h},pn8/z,\[x0,xzr,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z5\.h,z13\.h},pn14/z,\[x15,x24,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,x1,lsl 1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {Z0\.H,Z4\.H,Z8\.H,Z12\.H},PN8/Z,\[X0,X1,LSL#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z1\.h,z5\.h,z9\.h,z13\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z2\.h,z6\.h,z10\.h,z14\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z3\.h,z7\.h,z11\.h,z15\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z16\.h,z20\.h,z24\.h,z28\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z17\.h,z21\.h,z25\.h,z29\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z18\.h,z22\.h,z26\.h,z30\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z19\.h,z23\.h,z27\.h,z31\.h},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn15/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x30,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[sp,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,x30,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,xzr,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z17\.h,z21\.h,z25\.h,z29\.h},pn11/z,\[x4,x6,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z1\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z1\.h},pn8,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {Z0\.H-Z1\.H},PN8,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z30\.h-z31\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z1\.h},pn15,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z1\.h},pn8,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z1\.h},pn8,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z1\.h},pn8,\[x0,#-16,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z1\.h},pn8,\[x0,#14,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z12\.h-z13\.h},pn13,\[x11,#-10,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z3\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z3\.h},pn8,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {Z0\.H-Z3\.H},PN8,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z28\.h-z31\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z3\.h},pn15,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z3\.h},pn8,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z3\.h},pn8,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z3\.h},pn8,\[x0,#-32,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z3\.h},pn8,\[x0,#28,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z8\.h-z11\.h},pn11,\[x17,#20,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z8\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z8\.h},pn8,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {Z0\.H,Z8\.H},PN8,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z1\.h,z9\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z2\.h,z10\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z3\.h,z11\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z4\.h,z12\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z5\.h,z13\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z6\.h,z14\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z7\.h,z15\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z16\.h,z24\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z17\.h,z25\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z18\.h,z26\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z19\.h,z27\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z20\.h,z28\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z21\.h,z29\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z22\.h,z30\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z23\.h,z31\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z8\.h},pn15,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z8\.h},pn8,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z8\.h},pn8,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z8\.h},pn8,\[x0,#-16,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z8\.h},pn8,\[x0,#14,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z3\.h,z11\.h},pn10,\[x22,#6,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {Z0\.H,Z4\.H,Z8\.H,Z12\.H},PN8,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z1\.h,z5\.h,z9\.h,z13\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z2\.h,z6\.h,z10\.h,z14\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z3\.h,z7\.h,z11\.h,z15\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z16\.h,z20\.h,z24\.h,z28\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z17\.h,z21\.h,z25\.h,z29\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z18\.h,z22\.h,z26\.h,z30\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z19\.h,z23\.h,z27\.h,z31\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z4\.h,z8\.h,z12\.h},pn15,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x0,#-32,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x0,#28,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z2\.h,z6\.h,z10\.h,z14\.h},pn14,\[x29,#8,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z1\.h},pn8,\[x0,x1,lsl 1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z1\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {Z0\.H-Z1\.H},PN8,\[X0,X1,LSL#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z30\.h-z31\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z1\.h},pn15,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z1\.h},pn8,\[x30,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z1\.h},pn8,\[sp,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z1\.h},pn8,\[x0,x30,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z1\.h},pn8,\[x0,xzr,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z14\.h-z15\.h},pn9,\[x26,x3,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z3\.h},pn8,\[x0,x1,lsl 1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z3\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {Z0\.H-Z3\.H},PN8,\[X0,X1,LSL#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z28\.h-z31\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z3\.h},pn15,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z3\.h},pn8,\[x30,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z3\.h},pn8,\[sp,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z3\.h},pn8,\[x0,x30,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h-z3\.h},pn8,\[x0,xzr,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z8\.h-z11\.h},pn11,\[x27,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z8\.h},pn8,\[x0,x1,lsl 1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z8\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {Z0\.H,Z8\.H},PN8,\[X0,X1,LSL#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z1\.h,z9\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z2\.h,z10\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z3\.h,z11\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z4\.h,z12\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z5\.h,z13\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z6\.h,z14\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z7\.h,z15\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z16\.h,z24\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z17\.h,z25\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z18\.h,z26\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z19\.h,z27\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z20\.h,z28\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z21\.h,z29\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z22\.h,z30\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z23\.h,z31\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z8\.h},pn15,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z8\.h},pn8,\[x30,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z8\.h},pn8,\[sp,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z8\.h},pn8,\[x0,x30,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z8\.h},pn8,\[x0,xzr,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z5\.h,z13\.h},pn14,\[x15,x24,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x0,x1,lsl 1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {Z0\.H,Z4\.H,Z8\.H,Z12\.H},PN8,\[X0,X1,LSL#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z1\.h,z5\.h,z9\.h,z13\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z2\.h,z6\.h,z10\.h,z14\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z3\.h,z7\.h,z11\.h,z15\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z16\.h,z20\.h,z24\.h,z28\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z17\.h,z21\.h,z25\.h,z29\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z18\.h,z22\.h,z26\.h,z30\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z19\.h,z23\.h,z27\.h,z31\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z4\.h,z8\.h,z12\.h},pn15,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x30,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[sp,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x0,x30,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x0,xzr,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1h {z17\.h,z21\.h,z25\.h,z29\.h},pn11,\[x4,x6,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z1\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z1\.h},pn8,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {Z0\.H-Z1\.H},PN8,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z30\.h-z31\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z1\.h},pn15,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z1\.h},pn8,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z1\.h},pn8,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z1\.h},pn8,\[x0,#-16,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z1\.h},pn8,\[x0,#14,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z12\.h-z13\.h},pn13,\[x11,#-10,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z3\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z3\.h},pn8,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {Z0\.H-Z3\.H},PN8,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z28\.h-z31\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z3\.h},pn15,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z3\.h},pn8,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z3\.h},pn8,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z3\.h},pn8,\[x0,#-32,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z3\.h},pn8,\[x0,#28,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z8\.h-z11\.h},pn11,\[x17,#20,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z8\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z8\.h},pn8,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {Z0\.H,Z8\.H},PN8,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z1\.h,z9\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z2\.h,z10\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z3\.h,z11\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z4\.h,z12\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z5\.h,z13\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z6\.h,z14\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z7\.h,z15\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z16\.h,z24\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z17\.h,z25\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z18\.h,z26\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z19\.h,z27\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z20\.h,z28\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z21\.h,z29\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z22\.h,z30\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z23\.h,z31\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z8\.h},pn15,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z8\.h},pn8,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z8\.h},pn8,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z8\.h},pn8,\[x0,#-16,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z8\.h},pn8,\[x0,#14,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z3\.h,z11\.h},pn10,\[x22,#6,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {Z0\.H,Z4\.H,Z8\.H,Z12\.H},PN8,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z1\.h,z5\.h,z9\.h,z13\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z2\.h,z6\.h,z10\.h,z14\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z3\.h,z7\.h,z11\.h,z15\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z16\.h,z20\.h,z24\.h,z28\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z17\.h,z21\.h,z25\.h,z29\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z18\.h,z22\.h,z26\.h,z30\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z19\.h,z23\.h,z27\.h,z31\.h},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn15,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x0,#-32,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x0,#28,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z2\.h,z6\.h,z10\.h,z14\.h},pn14,\[x29,#8,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z1\.h},pn8,\[x0,x1,lsl 1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z1\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {Z0\.H-Z1\.H},PN8,\[X0,X1,LSL#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z30\.h-z31\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z1\.h},pn15,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z1\.h},pn8,\[x30,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z1\.h},pn8,\[sp,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z1\.h},pn8,\[x0,x30,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z1\.h},pn8,\[x0,xzr,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z14\.h-z15\.h},pn9,\[x26,x3,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z3\.h},pn8,\[x0,x1,lsl 1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z3\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {Z0\.H-Z3\.H},PN8,\[X0,X1,LSL#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z28\.h-z31\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z3\.h},pn15,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z3\.h},pn8,\[x30,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z3\.h},pn8,\[sp,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z3\.h},pn8,\[x0,x30,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h-z3\.h},pn8,\[x0,xzr,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z8\.h-z11\.h},pn11,\[x27,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z8\.h},pn8,\[x0,x1,lsl 1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z8\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {Z0\.H,Z8\.H},PN8,\[X0,X1,LSL#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z1\.h,z9\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z2\.h,z10\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z3\.h,z11\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z4\.h,z12\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z5\.h,z13\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z6\.h,z14\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z7\.h,z15\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z16\.h,z24\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z17\.h,z25\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z18\.h,z26\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z19\.h,z27\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z20\.h,z28\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z21\.h,z29\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z22\.h,z30\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z23\.h,z31\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z8\.h},pn15,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z8\.h},pn8,\[x30,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z8\.h},pn8,\[sp,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z8\.h},pn8,\[x0,x30,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z8\.h},pn8,\[x0,xzr,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z5\.h,z13\.h},pn14,\[x15,x24,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x0,x1,lsl 1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {Z0\.H,Z4\.H,Z8\.H,Z12\.H},PN8,\[X0,X1,LSL#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z1\.h,z5\.h,z9\.h,z13\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z2\.h,z6\.h,z10\.h,z14\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z3\.h,z7\.h,z11\.h,z15\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z16\.h,z20\.h,z24\.h,z28\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z17\.h,z21\.h,z25\.h,z29\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z18\.h,z22\.h,z26\.h,z30\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z19\.h,z23\.h,z27\.h,z31\.h},pn8,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn15,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x30,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[sp,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x0,x30,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.h,z4\.h,z8\.h,z12\.h},pn8,\[x0,xzr,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z17\.h,z21\.h,z25\.h,z29\.h},pn11,\[x4,x6,lsl#1\]'
|
||||
489
gas/testsuite/gas/aarch64/sme2-4.d
Normal file
489
gas/testsuite/gas/aarch64/sme2-4.d
Normal file
@ -0,0 +1,489 @@
|
||||
#as: -march=armv8-a+sme2
|
||||
#objdump: -dr
|
||||
|
||||
[^:]+: file format .*
|
||||
|
||||
|
||||
[^:]+:
|
||||
|
||||
[^:]+:
|
||||
[^:]+: a0402000 ld1h {z0\.h-z1\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a0402000 ld1h {z0\.h-z1\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a0402000 ld1h {z0\.h-z1\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a040201e ld1h {z30\.h-z31\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a0403c00 ld1h {z0\.h-z1\.h}, pn15/z, \[x0\]
|
||||
[^:]+: a04023c0 ld1h {z0\.h-z1\.h}, pn8/z, \[x30\]
|
||||
[^:]+: a04023e0 ld1h {z0\.h-z1\.h}, pn8/z, \[sp\]
|
||||
[^:]+: a0482000 ld1h {z0\.h-z1\.h}, pn8/z, \[x0, #-16, mul vl\]
|
||||
[^:]+: a0472000 ld1h {z0\.h-z1\.h}, pn8/z, \[x0, #14, mul vl\]
|
||||
[^:]+: a04b356c ld1h {z12\.h-z13\.h}, pn13/z, \[x11, #-10, mul vl\]
|
||||
[^:]+: a040a000 ld1h {z0\.h-z3\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a040a000 ld1h {z0\.h-z3\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a040a000 ld1h {z0\.h-z3\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a040a01c ld1h {z28\.h-z31\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a040bc00 ld1h {z0\.h-z3\.h}, pn15/z, \[x0\]
|
||||
[^:]+: a040a3c0 ld1h {z0\.h-z3\.h}, pn8/z, \[x30\]
|
||||
[^:]+: a040a3e0 ld1h {z0\.h-z3\.h}, pn8/z, \[sp\]
|
||||
[^:]+: a048a000 ld1h {z0\.h-z3\.h}, pn8/z, \[x0, #-32, mul vl\]
|
||||
[^:]+: a047a000 ld1h {z0\.h-z3\.h}, pn8/z, \[x0, #28, mul vl\]
|
||||
[^:]+: a045ae28 ld1h {z8\.h-z11\.h}, pn11/z, \[x17, #20, mul vl\]
|
||||
[^:]+: a1402000 ld1h {z0\.h, z8\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a1402000 ld1h {z0\.h, z8\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a1402000 ld1h {z0\.h, z8\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a1402001 ld1h {z1\.h, z9\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a1402002 ld1h {z2\.h, z10\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a1402003 ld1h {z3\.h, z11\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a1402004 ld1h {z4\.h, z12\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a1402005 ld1h {z5\.h, z13\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a1402006 ld1h {z6\.h, z14\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a1402007 ld1h {z7\.h, z15\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a1402010 ld1h {z16\.h, z24\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a1402011 ld1h {z17\.h, z25\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a1402012 ld1h {z18\.h, z26\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a1402013 ld1h {z19\.h, z27\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a1402014 ld1h {z20\.h, z28\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a1402015 ld1h {z21\.h, z29\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a1402016 ld1h {z22\.h, z30\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a1402017 ld1h {z23\.h, z31\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a1403c00 ld1h {z0\.h, z8\.h}, pn15/z, \[x0\]
|
||||
[^:]+: a14023c0 ld1h {z0\.h, z8\.h}, pn8/z, \[x30\]
|
||||
[^:]+: a14023e0 ld1h {z0\.h, z8\.h}, pn8/z, \[sp\]
|
||||
[^:]+: a1482000 ld1h {z0\.h, z8\.h}, pn8/z, \[x0, #-16, mul vl\]
|
||||
[^:]+: a1472000 ld1h {z0\.h, z8\.h}, pn8/z, \[x0, #14, mul vl\]
|
||||
[^:]+: a1432ac3 ld1h {z3\.h, z11\.h}, pn10/z, \[x22, #6, mul vl\]
|
||||
[^:]+: a140a000 ld1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a140a000 ld1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a140a000 ld1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a140a001 ld1h {z1\.h, z5\.h, z9\.h, z13\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a140a002 ld1h {z2\.h, z6\.h, z10\.h, z14\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a140a003 ld1h {z3\.h, z7\.h, z11\.h, z15\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a140a010 ld1h {z16\.h, z20\.h, z24\.h, z28\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a140a011 ld1h {z17\.h, z21\.h, z25\.h, z29\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a140a012 ld1h {z18\.h, z22\.h, z26\.h, z30\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a140a013 ld1h {z19\.h, z23\.h, z27\.h, z31\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a140bc00 ld1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn15/z, \[x0\]
|
||||
[^:]+: a140a3c0 ld1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x30\]
|
||||
[^:]+: a140a3e0 ld1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[sp\]
|
||||
[^:]+: a148a000 ld1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x0, #-32, mul vl\]
|
||||
[^:]+: a147a000 ld1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x0, #28, mul vl\]
|
||||
[^:]+: a142bba2 ld1h {z2\.h, z6\.h, z10\.h, z14\.h}, pn14/z, \[x29, #8, mul vl\]
|
||||
[^:]+: a0012000 ld1h {z0\.h-z1\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a0012000 ld1h {z0\.h-z1\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a0012000 ld1h {z0\.h-z1\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a001201e ld1h {z30\.h-z31\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a0013c00 ld1h {z0\.h-z1\.h}, pn15/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a00123c0 ld1h {z0\.h-z1\.h}, pn8/z, \[x30, x1, lsl #1\]
|
||||
[^:]+: a00123e0 ld1h {z0\.h-z1\.h}, pn8/z, \[sp, x1, lsl #1\]
|
||||
[^:]+: a01e2000 ld1h {z0\.h-z1\.h}, pn8/z, \[x0, x30, lsl #1\]
|
||||
[^:]+: a01f2000 ld1h {z0\.h-z1\.h}, pn8/z, \[x0, xzr, lsl #1\]
|
||||
[^:]+: a003274e ld1h {z14\.h-z15\.h}, pn9/z, \[x26, x3, lsl #1\]
|
||||
[^:]+: a001a000 ld1h {z0\.h-z3\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a001a000 ld1h {z0\.h-z3\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a001a000 ld1h {z0\.h-z3\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a001a01c ld1h {z28\.h-z31\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a001bc00 ld1h {z0\.h-z3\.h}, pn15/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a001a3c0 ld1h {z0\.h-z3\.h}, pn8/z, \[x30, x1, lsl #1\]
|
||||
[^:]+: a001a3e0 ld1h {z0\.h-z3\.h}, pn8/z, \[sp, x1, lsl #1\]
|
||||
[^:]+: a01ea000 ld1h {z0\.h-z3\.h}, pn8/z, \[x0, x30, lsl #1\]
|
||||
[^:]+: a01fa000 ld1h {z0\.h-z3\.h}, pn8/z, \[x0, xzr, lsl #1\]
|
||||
[^:]+: a001af68 ld1h {z8\.h-z11\.h}, pn11/z, \[x27, x1, lsl #1\]
|
||||
[^:]+: a1012000 ld1h {z0\.h, z8\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a1012000 ld1h {z0\.h, z8\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a1012000 ld1h {z0\.h, z8\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a1012001 ld1h {z1\.h, z9\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a1012002 ld1h {z2\.h, z10\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a1012003 ld1h {z3\.h, z11\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a1012004 ld1h {z4\.h, z12\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a1012005 ld1h {z5\.h, z13\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a1012006 ld1h {z6\.h, z14\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a1012007 ld1h {z7\.h, z15\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a1012010 ld1h {z16\.h, z24\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a1012011 ld1h {z17\.h, z25\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a1012012 ld1h {z18\.h, z26\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a1012013 ld1h {z19\.h, z27\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a1012014 ld1h {z20\.h, z28\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a1012015 ld1h {z21\.h, z29\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a1012016 ld1h {z22\.h, z30\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a1012017 ld1h {z23\.h, z31\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a1013c00 ld1h {z0\.h, z8\.h}, pn15/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a10123c0 ld1h {z0\.h, z8\.h}, pn8/z, \[x30, x1, lsl #1\]
|
||||
[^:]+: a10123e0 ld1h {z0\.h, z8\.h}, pn8/z, \[sp, x1, lsl #1\]
|
||||
[^:]+: a11e2000 ld1h {z0\.h, z8\.h}, pn8/z, \[x0, x30, lsl #1\]
|
||||
[^:]+: a11f2000 ld1h {z0\.h, z8\.h}, pn8/z, \[x0, xzr, lsl #1\]
|
||||
[^:]+: a11839e5 ld1h {z5\.h, z13\.h}, pn14/z, \[x15, x24, lsl #1\]
|
||||
[^:]+: a101a000 ld1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a101a000 ld1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a101a000 ld1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a101a001 ld1h {z1\.h, z5\.h, z9\.h, z13\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a101a002 ld1h {z2\.h, z6\.h, z10\.h, z14\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a101a003 ld1h {z3\.h, z7\.h, z11\.h, z15\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a101a010 ld1h {z16\.h, z20\.h, z24\.h, z28\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a101a011 ld1h {z17\.h, z21\.h, z25\.h, z29\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a101a012 ld1h {z18\.h, z22\.h, z26\.h, z30\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a101a013 ld1h {z19\.h, z23\.h, z27\.h, z31\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a101bc00 ld1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn15/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a101a3c0 ld1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x30, x1, lsl #1\]
|
||||
[^:]+: a101a3e0 ld1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[sp, x1, lsl #1\]
|
||||
[^:]+: a11ea000 ld1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x0, x30, lsl #1\]
|
||||
[^:]+: a11fa000 ld1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x0, xzr, lsl #1\]
|
||||
[^:]+: a106ac91 ld1h {z17\.h, z21\.h, z25\.h, z29\.h}, pn11/z, \[x4, x6, lsl #1\]
|
||||
[^:]+: a0402001 ldnt1h {z0\.h-z1\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a0402001 ldnt1h {z0\.h-z1\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a0402001 ldnt1h {z0\.h-z1\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a040201f ldnt1h {z30\.h-z31\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a0403c01 ldnt1h {z0\.h-z1\.h}, pn15/z, \[x0\]
|
||||
[^:]+: a04023c1 ldnt1h {z0\.h-z1\.h}, pn8/z, \[x30\]
|
||||
[^:]+: a04023e1 ldnt1h {z0\.h-z1\.h}, pn8/z, \[sp\]
|
||||
[^:]+: a0482001 ldnt1h {z0\.h-z1\.h}, pn8/z, \[x0, #-16, mul vl\]
|
||||
[^:]+: a0472001 ldnt1h {z0\.h-z1\.h}, pn8/z, \[x0, #14, mul vl\]
|
||||
[^:]+: a04b356d ldnt1h {z12\.h-z13\.h}, pn13/z, \[x11, #-10, mul vl\]
|
||||
[^:]+: a040a001 ldnt1h {z0\.h-z3\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a040a001 ldnt1h {z0\.h-z3\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a040a001 ldnt1h {z0\.h-z3\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a040a01d ldnt1h {z28\.h-z31\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a040bc01 ldnt1h {z0\.h-z3\.h}, pn15/z, \[x0\]
|
||||
[^:]+: a040a3c1 ldnt1h {z0\.h-z3\.h}, pn8/z, \[x30\]
|
||||
[^:]+: a040a3e1 ldnt1h {z0\.h-z3\.h}, pn8/z, \[sp\]
|
||||
[^:]+: a048a001 ldnt1h {z0\.h-z3\.h}, pn8/z, \[x0, #-32, mul vl\]
|
||||
[^:]+: a047a001 ldnt1h {z0\.h-z3\.h}, pn8/z, \[x0, #28, mul vl\]
|
||||
[^:]+: a045ae29 ldnt1h {z8\.h-z11\.h}, pn11/z, \[x17, #20, mul vl\]
|
||||
[^:]+: a1402008 ldnt1h {z0\.h, z8\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a1402008 ldnt1h {z0\.h, z8\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a1402008 ldnt1h {z0\.h, z8\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a1402009 ldnt1h {z1\.h, z9\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a140200a ldnt1h {z2\.h, z10\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a140200b ldnt1h {z3\.h, z11\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a140200c ldnt1h {z4\.h, z12\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a140200d ldnt1h {z5\.h, z13\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a140200e ldnt1h {z6\.h, z14\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a140200f ldnt1h {z7\.h, z15\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a1402018 ldnt1h {z16\.h, z24\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a1402019 ldnt1h {z17\.h, z25\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a140201a ldnt1h {z18\.h, z26\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a140201b ldnt1h {z19\.h, z27\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a140201c ldnt1h {z20\.h, z28\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a140201d ldnt1h {z21\.h, z29\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a140201e ldnt1h {z22\.h, z30\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a140201f ldnt1h {z23\.h, z31\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a1403c08 ldnt1h {z0\.h, z8\.h}, pn15/z, \[x0\]
|
||||
[^:]+: a14023c8 ldnt1h {z0\.h, z8\.h}, pn8/z, \[x30\]
|
||||
[^:]+: a14023e8 ldnt1h {z0\.h, z8\.h}, pn8/z, \[sp\]
|
||||
[^:]+: a1482008 ldnt1h {z0\.h, z8\.h}, pn8/z, \[x0, #-16, mul vl\]
|
||||
[^:]+: a1472008 ldnt1h {z0\.h, z8\.h}, pn8/z, \[x0, #14, mul vl\]
|
||||
[^:]+: a1432acb ldnt1h {z3\.h, z11\.h}, pn10/z, \[x22, #6, mul vl\]
|
||||
[^:]+: a140a008 ldnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a140a008 ldnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a140a008 ldnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a140a009 ldnt1h {z1\.h, z5\.h, z9\.h, z13\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a140a00a ldnt1h {z2\.h, z6\.h, z10\.h, z14\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a140a00b ldnt1h {z3\.h, z7\.h, z11\.h, z15\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a140a018 ldnt1h {z16\.h, z20\.h, z24\.h, z28\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a140a019 ldnt1h {z17\.h, z21\.h, z25\.h, z29\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a140a01a ldnt1h {z18\.h, z22\.h, z26\.h, z30\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a140a01b ldnt1h {z19\.h, z23\.h, z27\.h, z31\.h}, pn8/z, \[x0\]
|
||||
[^:]+: a140bc08 ldnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn15/z, \[x0\]
|
||||
[^:]+: a140a3c8 ldnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x30\]
|
||||
[^:]+: a140a3e8 ldnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[sp\]
|
||||
[^:]+: a148a008 ldnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x0, #-32, mul vl\]
|
||||
[^:]+: a147a008 ldnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x0, #28, mul vl\]
|
||||
[^:]+: a142bbaa ldnt1h {z2\.h, z6\.h, z10\.h, z14\.h}, pn14/z, \[x29, #8, mul vl\]
|
||||
[^:]+: a0012001 ldnt1h {z0\.h-z1\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a0012001 ldnt1h {z0\.h-z1\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a0012001 ldnt1h {z0\.h-z1\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a001201f ldnt1h {z30\.h-z31\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a0013c01 ldnt1h {z0\.h-z1\.h}, pn15/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a00123c1 ldnt1h {z0\.h-z1\.h}, pn8/z, \[x30, x1, lsl #1\]
|
||||
[^:]+: a00123e1 ldnt1h {z0\.h-z1\.h}, pn8/z, \[sp, x1, lsl #1\]
|
||||
[^:]+: a01e2001 ldnt1h {z0\.h-z1\.h}, pn8/z, \[x0, x30, lsl #1\]
|
||||
[^:]+: a01f2001 ldnt1h {z0\.h-z1\.h}, pn8/z, \[x0, xzr, lsl #1\]
|
||||
[^:]+: a003274f ldnt1h {z14\.h-z15\.h}, pn9/z, \[x26, x3, lsl #1\]
|
||||
[^:]+: a001a001 ldnt1h {z0\.h-z3\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a001a001 ldnt1h {z0\.h-z3\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a001a001 ldnt1h {z0\.h-z3\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a001a01d ldnt1h {z28\.h-z31\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a001bc01 ldnt1h {z0\.h-z3\.h}, pn15/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a001a3c1 ldnt1h {z0\.h-z3\.h}, pn8/z, \[x30, x1, lsl #1\]
|
||||
[^:]+: a001a3e1 ldnt1h {z0\.h-z3\.h}, pn8/z, \[sp, x1, lsl #1\]
|
||||
[^:]+: a01ea001 ldnt1h {z0\.h-z3\.h}, pn8/z, \[x0, x30, lsl #1\]
|
||||
[^:]+: a01fa001 ldnt1h {z0\.h-z3\.h}, pn8/z, \[x0, xzr, lsl #1\]
|
||||
[^:]+: a001af69 ldnt1h {z8\.h-z11\.h}, pn11/z, \[x27, x1, lsl #1\]
|
||||
[^:]+: a1012008 ldnt1h {z0\.h, z8\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a1012008 ldnt1h {z0\.h, z8\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a1012008 ldnt1h {z0\.h, z8\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a1012009 ldnt1h {z1\.h, z9\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a101200a ldnt1h {z2\.h, z10\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a101200b ldnt1h {z3\.h, z11\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a101200c ldnt1h {z4\.h, z12\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a101200d ldnt1h {z5\.h, z13\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a101200e ldnt1h {z6\.h, z14\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a101200f ldnt1h {z7\.h, z15\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a1012018 ldnt1h {z16\.h, z24\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a1012019 ldnt1h {z17\.h, z25\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a101201a ldnt1h {z18\.h, z26\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a101201b ldnt1h {z19\.h, z27\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a101201c ldnt1h {z20\.h, z28\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a101201d ldnt1h {z21\.h, z29\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a101201e ldnt1h {z22\.h, z30\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a101201f ldnt1h {z23\.h, z31\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a1013c08 ldnt1h {z0\.h, z8\.h}, pn15/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a10123c8 ldnt1h {z0\.h, z8\.h}, pn8/z, \[x30, x1, lsl #1\]
|
||||
[^:]+: a10123e8 ldnt1h {z0\.h, z8\.h}, pn8/z, \[sp, x1, lsl #1\]
|
||||
[^:]+: a11e2008 ldnt1h {z0\.h, z8\.h}, pn8/z, \[x0, x30, lsl #1\]
|
||||
[^:]+: a11f2008 ldnt1h {z0\.h, z8\.h}, pn8/z, \[x0, xzr, lsl #1\]
|
||||
[^:]+: a11839ed ldnt1h {z5\.h, z13\.h}, pn14/z, \[x15, x24, lsl #1\]
|
||||
[^:]+: a101a008 ldnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a101a008 ldnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a101a008 ldnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a101a009 ldnt1h {z1\.h, z5\.h, z9\.h, z13\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a101a00a ldnt1h {z2\.h, z6\.h, z10\.h, z14\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a101a00b ldnt1h {z3\.h, z7\.h, z11\.h, z15\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a101a018 ldnt1h {z16\.h, z20\.h, z24\.h, z28\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a101a019 ldnt1h {z17\.h, z21\.h, z25\.h, z29\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a101a01a ldnt1h {z18\.h, z22\.h, z26\.h, z30\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a101a01b ldnt1h {z19\.h, z23\.h, z27\.h, z31\.h}, pn8/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a101bc08 ldnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn15/z, \[x0, x1, lsl #1\]
|
||||
[^:]+: a101a3c8 ldnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x30, x1, lsl #1\]
|
||||
[^:]+: a101a3e8 ldnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[sp, x1, lsl #1\]
|
||||
[^:]+: a11ea008 ldnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x0, x30, lsl #1\]
|
||||
[^:]+: a11fa008 ldnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8/z, \[x0, xzr, lsl #1\]
|
||||
[^:]+: a106ac99 ldnt1h {z17\.h, z21\.h, z25\.h, z29\.h}, pn11/z, \[x4, x6, lsl #1\]
|
||||
[^:]+: a0602000 st1h {z0\.h-z1\.h}, pn8, \[x0\]
|
||||
[^:]+: a0602000 st1h {z0\.h-z1\.h}, pn8, \[x0\]
|
||||
[^:]+: a0602000 st1h {z0\.h-z1\.h}, pn8, \[x0\]
|
||||
[^:]+: a060201e st1h {z30\.h-z31\.h}, pn8, \[x0\]
|
||||
[^:]+: a0603c00 st1h {z0\.h-z1\.h}, pn15, \[x0\]
|
||||
[^:]+: a06023c0 st1h {z0\.h-z1\.h}, pn8, \[x30\]
|
||||
[^:]+: a06023e0 st1h {z0\.h-z1\.h}, pn8, \[sp\]
|
||||
[^:]+: a0682000 st1h {z0\.h-z1\.h}, pn8, \[x0, #-16, mul vl\]
|
||||
[^:]+: a0672000 st1h {z0\.h-z1\.h}, pn8, \[x0, #14, mul vl\]
|
||||
[^:]+: a06b356c st1h {z12\.h-z13\.h}, pn13, \[x11, #-10, mul vl\]
|
||||
[^:]+: a060a000 st1h {z0\.h-z3\.h}, pn8, \[x0\]
|
||||
[^:]+: a060a000 st1h {z0\.h-z3\.h}, pn8, \[x0\]
|
||||
[^:]+: a060a000 st1h {z0\.h-z3\.h}, pn8, \[x0\]
|
||||
[^:]+: a060a01c st1h {z28\.h-z31\.h}, pn8, \[x0\]
|
||||
[^:]+: a060bc00 st1h {z0\.h-z3\.h}, pn15, \[x0\]
|
||||
[^:]+: a060a3c0 st1h {z0\.h-z3\.h}, pn8, \[x30\]
|
||||
[^:]+: a060a3e0 st1h {z0\.h-z3\.h}, pn8, \[sp\]
|
||||
[^:]+: a068a000 st1h {z0\.h-z3\.h}, pn8, \[x0, #-32, mul vl\]
|
||||
[^:]+: a067a000 st1h {z0\.h-z3\.h}, pn8, \[x0, #28, mul vl\]
|
||||
[^:]+: a065ae28 st1h {z8\.h-z11\.h}, pn11, \[x17, #20, mul vl\]
|
||||
[^:]+: a1602000 st1h {z0\.h, z8\.h}, pn8, \[x0\]
|
||||
[^:]+: a1602000 st1h {z0\.h, z8\.h}, pn8, \[x0\]
|
||||
[^:]+: a1602000 st1h {z0\.h, z8\.h}, pn8, \[x0\]
|
||||
[^:]+: a1602001 st1h {z1\.h, z9\.h}, pn8, \[x0\]
|
||||
[^:]+: a1602002 st1h {z2\.h, z10\.h}, pn8, \[x0\]
|
||||
[^:]+: a1602003 st1h {z3\.h, z11\.h}, pn8, \[x0\]
|
||||
[^:]+: a1602004 st1h {z4\.h, z12\.h}, pn8, \[x0\]
|
||||
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||||
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|
||||
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
[^:]+: a1212008 stnt1h {z0\.h, z8\.h}, pn8, \[x0, x1, lsl #1\]
|
||||
[^:]+: a1212008 stnt1h {z0\.h, z8\.h}, pn8, \[x0, x1, lsl #1\]
|
||||
[^:]+: a1212009 stnt1h {z1\.h, z9\.h}, pn8, \[x0, x1, lsl #1\]
|
||||
[^:]+: a121200a stnt1h {z2\.h, z10\.h}, pn8, \[x0, x1, lsl #1\]
|
||||
[^:]+: a121200b stnt1h {z3\.h, z11\.h}, pn8, \[x0, x1, lsl #1\]
|
||||
[^:]+: a121200c stnt1h {z4\.h, z12\.h}, pn8, \[x0, x1, lsl #1\]
|
||||
[^:]+: a121200d stnt1h {z5\.h, z13\.h}, pn8, \[x0, x1, lsl #1\]
|
||||
[^:]+: a121200e stnt1h {z6\.h, z14\.h}, pn8, \[x0, x1, lsl #1\]
|
||||
[^:]+: a121200f stnt1h {z7\.h, z15\.h}, pn8, \[x0, x1, lsl #1\]
|
||||
[^:]+: a1212018 stnt1h {z16\.h, z24\.h}, pn8, \[x0, x1, lsl #1\]
|
||||
[^:]+: a1212019 stnt1h {z17\.h, z25\.h}, pn8, \[x0, x1, lsl #1\]
|
||||
[^:]+: a121201a stnt1h {z18\.h, z26\.h}, pn8, \[x0, x1, lsl #1\]
|
||||
[^:]+: a121201b stnt1h {z19\.h, z27\.h}, pn8, \[x0, x1, lsl #1\]
|
||||
[^:]+: a121201c stnt1h {z20\.h, z28\.h}, pn8, \[x0, x1, lsl #1\]
|
||||
[^:]+: a121201d stnt1h {z21\.h, z29\.h}, pn8, \[x0, x1, lsl #1\]
|
||||
[^:]+: a121201e stnt1h {z22\.h, z30\.h}, pn8, \[x0, x1, lsl #1\]
|
||||
[^:]+: a121201f stnt1h {z23\.h, z31\.h}, pn8, \[x0, x1, lsl #1\]
|
||||
[^:]+: a1213c08 stnt1h {z0\.h, z8\.h}, pn15, \[x0, x1, lsl #1\]
|
||||
[^:]+: a12123c8 stnt1h {z0\.h, z8\.h}, pn8, \[x30, x1, lsl #1\]
|
||||
[^:]+: a12123e8 stnt1h {z0\.h, z8\.h}, pn8, \[sp, x1, lsl #1\]
|
||||
[^:]+: a13e2008 stnt1h {z0\.h, z8\.h}, pn8, \[x0, x30, lsl #1\]
|
||||
[^:]+: a13f2008 stnt1h {z0\.h, z8\.h}, pn8, \[x0, xzr, lsl #1\]
|
||||
[^:]+: a13839ed stnt1h {z5\.h, z13\.h}, pn14, \[x15, x24, lsl #1\]
|
||||
[^:]+: a121a008 stnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8, \[x0, x1, lsl #1\]
|
||||
[^:]+: a121a008 stnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8, \[x0, x1, lsl #1\]
|
||||
[^:]+: a121a008 stnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8, \[x0, x1, lsl #1\]
|
||||
[^:]+: a121a009 stnt1h {z1\.h, z5\.h, z9\.h, z13\.h}, pn8, \[x0, x1, lsl #1\]
|
||||
[^:]+: a121a00a stnt1h {z2\.h, z6\.h, z10\.h, z14\.h}, pn8, \[x0, x1, lsl #1\]
|
||||
[^:]+: a121a00b stnt1h {z3\.h, z7\.h, z11\.h, z15\.h}, pn8, \[x0, x1, lsl #1\]
|
||||
[^:]+: a121a018 stnt1h {z16\.h, z20\.h, z24\.h, z28\.h}, pn8, \[x0, x1, lsl #1\]
|
||||
[^:]+: a121a019 stnt1h {z17\.h, z21\.h, z25\.h, z29\.h}, pn8, \[x0, x1, lsl #1\]
|
||||
[^:]+: a121a01a stnt1h {z18\.h, z22\.h, z26\.h, z30\.h}, pn8, \[x0, x1, lsl #1\]
|
||||
[^:]+: a121a01b stnt1h {z19\.h, z23\.h, z27\.h, z31\.h}, pn8, \[x0, x1, lsl #1\]
|
||||
[^:]+: a121bc08 stnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn15, \[x0, x1, lsl #1\]
|
||||
[^:]+: a121a3c8 stnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8, \[x30, x1, lsl #1\]
|
||||
[^:]+: a121a3e8 stnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8, \[sp, x1, lsl #1\]
|
||||
[^:]+: a13ea008 stnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8, \[x0, x30, lsl #1\]
|
||||
[^:]+: a13fa008 stnt1h {z0\.h, z4\.h, z8\.h, z12\.h}, pn8, \[x0, xzr, lsl #1\]
|
||||
[^:]+: a126ac99 stnt1h {z17\.h, z21\.h, z25\.h, z29\.h}, pn11, \[x4, x6, lsl #1\]
|
||||
511
gas/testsuite/gas/aarch64/sme2-4.s
Normal file
511
gas/testsuite/gas/aarch64/sme2-4.s
Normal file
@ -0,0 +1,511 @@
|
||||
ld1h { z0.h - z1.h }, pn8/z, [x0]
|
||||
ld1h { z0.h - z1.h }, pn8/z, [x0, #0, mul vl]
|
||||
LD1H { Z0.H - Z1.H }, PN8/Z, [X0]
|
||||
ld1h { z30.h - z31.h }, pn8/z, [x0]
|
||||
ld1h { z0.h - z1.h }, pn15/z, [x0]
|
||||
ld1h { z0.h - z1.h }, pn8/z, [x30]
|
||||
ld1h { z0.h - z1.h }, pn8/z, [sp]
|
||||
ld1h { z0.h - z1.h }, pn8/z, [x0, #-16, mul vl]
|
||||
ld1h { z0.h - z1.h }, pn8/z, [x0, #14, mul vl]
|
||||
ld1h { z12.h - z13.h }, pn13/z, [x11, #-10, mul vl]
|
||||
|
||||
ld1h { z0.h - z3.h }, pn8/z, [x0]
|
||||
ld1h { z0.h - z3.h }, pn8/z, [x0, #0, mul vl]
|
||||
LD1H { Z0.H - Z3.H }, PN8/Z, [X0]
|
||||
ld1h { z28.h - z31.h }, pn8/z, [x0]
|
||||
ld1h { z0.h - z3.h }, pn15/z, [x0]
|
||||
ld1h { z0.h - z3.h }, pn8/z, [x30]
|
||||
ld1h { z0.h - z3.h }, pn8/z, [sp]
|
||||
ld1h { z0.h - z3.h }, pn8/z, [x0, #-32, mul vl]
|
||||
ld1h { z0.h - z3.h }, pn8/z, [x0, #28, mul vl]
|
||||
ld1h { z8.h - z11.h }, pn11/z, [x17, #20, mul vl]
|
||||
|
||||
ld1h { z0.h, z8.h }, pn8/z, [x0]
|
||||
ld1h { z0.h, z8.h }, pn8/z, [x0, #0, mul vl]
|
||||
LD1H { Z0.H, Z8.H }, PN8/Z, [X0]
|
||||
ld1h { z1.h, z9.h }, pn8/z, [x0]
|
||||
ld1h { z2.h, z10.h }, pn8/z, [x0]
|
||||
ld1h { z3.h, z11.h }, pn8/z, [x0]
|
||||
ld1h { z4.h, z12.h }, pn8/z, [x0]
|
||||
ld1h { z5.h, z13.h }, pn8/z, [x0]
|
||||
ld1h { z6.h, z14.h }, pn8/z, [x0]
|
||||
ld1h { z7.h, z15.h }, pn8/z, [x0]
|
||||
ld1h { z16.h, z24.h }, pn8/z, [x0]
|
||||
ld1h { z17.h, z25.h }, pn8/z, [x0]
|
||||
ld1h { z18.h, z26.h }, pn8/z, [x0]
|
||||
ld1h { z19.h, z27.h }, pn8/z, [x0]
|
||||
ld1h { z20.h, z28.h }, pn8/z, [x0]
|
||||
ld1h { z21.h, z29.h }, pn8/z, [x0]
|
||||
ld1h { z22.h, z30.h }, pn8/z, [x0]
|
||||
ld1h { z23.h, z31.h }, pn8/z, [x0]
|
||||
ld1h { z0.h, z8.h }, pn15/z, [x0]
|
||||
ld1h { z0.h, z8.h }, pn8/z, [x30]
|
||||
ld1h { z0.h, z8.h }, pn8/z, [sp]
|
||||
ld1h { z0.h, z8.h }, pn8/z, [x0, #-16, mul vl]
|
||||
ld1h { z0.h, z8.h }, pn8/z, [x0, #14, mul vl]
|
||||
ld1h { z3.h, z11.h }, pn10/z, [x22, #6, mul vl]
|
||||
|
||||
ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0]
|
||||
ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, #0, mul vl]
|
||||
LD1H { Z0.H, Z4.H, Z8.H, Z12.H }, PN8/Z, [X0]
|
||||
ld1h { z1.h, z5.h, z9.h, z13.h }, pn8/z, [x0]
|
||||
ld1h { z2.h, z6.h, z10.h, z14.h }, pn8/z, [x0]
|
||||
ld1h { z3.h, z7.h, z11.h, z15.h }, pn8/z, [x0]
|
||||
ld1h { z16.h, z20.h, z24.h, z28.h }, pn8/z, [x0]
|
||||
ld1h { z17.h, z21.h, z25.h, z29.h }, pn8/z, [x0]
|
||||
ld1h { z18.h, z22.h, z26.h, z30.h }, pn8/z, [x0]
|
||||
ld1h { z19.h, z23.h, z27.h, z31.h }, pn8/z, [x0]
|
||||
ld1h { z0.h, z4.h, z8.h, z12.h }, pn15/z, [x0]
|
||||
ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x30]
|
||||
ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [sp]
|
||||
ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, #-32, mul vl]
|
||||
ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, #28, mul vl]
|
||||
ld1h { z2.h, z6.h, z10.h, z14.h }, pn14/z, [x29, #8, mul vl]
|
||||
|
||||
ld1h { z0.h - z1.h }, pn8/z, [x0, x1, lsl 1]
|
||||
ld1h { z0.h - z1.h }, pn8/z, [x0, x1, lsl #1]
|
||||
LD1H { Z0.H - Z1.H }, PN8/Z, [X0, X1, LSL #1]
|
||||
ld1h { z30.h - z31.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z0.h - z1.h }, pn15/z, [x0, x1, lsl #1]
|
||||
ld1h { z0.h - z1.h }, pn8/z, [x30, x1, lsl #1]
|
||||
ld1h { z0.h - z1.h }, pn8/z, [sp, x1, lsl #1]
|
||||
ld1h { z0.h - z1.h }, pn8/z, [x0, x30, lsl #1]
|
||||
ld1h { z0.h - z1.h }, pn8/z, [x0, xzr, lsl #1]
|
||||
ld1h { z14.h - z15.h }, pn9/z, [x26, x3, lsl #1]
|
||||
|
||||
ld1h { z0.h - z3.h }, pn8/z, [x0, x1, lsl 1]
|
||||
ld1h { z0.h - z3.h }, pn8/z, [x0, x1, lsl #1]
|
||||
LD1H { Z0.H - Z3.H }, PN8/Z, [X0, X1, LSL #1]
|
||||
ld1h { z28.h - z31.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z0.h - z3.h }, pn15/z, [x0, x1, lsl #1]
|
||||
ld1h { z0.h - z3.h }, pn8/z, [x30, x1, lsl #1]
|
||||
ld1h { z0.h - z3.h }, pn8/z, [sp, x1, lsl #1]
|
||||
ld1h { z0.h - z3.h }, pn8/z, [x0, x30, lsl #1]
|
||||
ld1h { z0.h - z3.h }, pn8/z, [x0, xzr, lsl #1]
|
||||
ld1h { z8.h - z11.h }, pn11/z, [x27, x1, lsl #1]
|
||||
|
||||
ld1h { z0.h, z8.h }, pn8/z, [x0, x1, lsl 1]
|
||||
ld1h { z0.h, z8.h }, pn8/z, [x0, x1, lsl #1]
|
||||
LD1H { Z0.H, Z8.H }, PN8/Z, [X0, X1, LSL #1]
|
||||
ld1h { z1.h, z9.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z2.h, z10.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z3.h, z11.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z4.h, z12.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z5.h, z13.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z6.h, z14.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z7.h, z15.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z16.h, z24.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z17.h, z25.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z18.h, z26.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z19.h, z27.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z20.h, z28.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z21.h, z29.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z22.h, z30.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z23.h, z31.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z0.h, z8.h }, pn15/z, [x0, x1, lsl #1]
|
||||
ld1h { z0.h, z8.h }, pn8/z, [x30, x1, lsl #1]
|
||||
ld1h { z0.h, z8.h }, pn8/z, [sp, x1, lsl #1]
|
||||
ld1h { z0.h, z8.h }, pn8/z, [x0, x30, lsl #1]
|
||||
ld1h { z0.h, z8.h }, pn8/z, [x0, xzr, lsl #1]
|
||||
ld1h { z5.h, z13.h }, pn14/z, [x15, x24, lsl #1]
|
||||
|
||||
ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, x1, lsl 1]
|
||||
ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, x1, lsl #1]
|
||||
LD1H { Z0.H, Z4.H, Z8.H, Z12.H }, PN8/Z, [X0, X1, LSL #1]
|
||||
ld1h { z1.h, z5.h, z9.h, z13.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z2.h, z6.h, z10.h, z14.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z3.h, z7.h, z11.h, z15.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z16.h, z20.h, z24.h, z28.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z17.h, z21.h, z25.h, z29.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z18.h, z22.h, z26.h, z30.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z19.h, z23.h, z27.h, z31.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1h { z0.h, z4.h, z8.h, z12.h }, pn15/z, [x0, x1, lsl #1]
|
||||
ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x30, x1, lsl #1]
|
||||
ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [sp, x1, lsl #1]
|
||||
ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, x30, lsl #1]
|
||||
ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, xzr, lsl #1]
|
||||
ld1h { z17.h, z21.h, z25.h, z29.h }, pn11/z, [x4, x6, lsl #1]
|
||||
|
||||
ldnt1h { z0.h - z1.h }, pn8/z, [x0]
|
||||
ldnt1h { z0.h - z1.h }, pn8/z, [x0, #0, mul vl]
|
||||
LDNT1H { Z0.H - Z1.H }, PN8/Z, [X0]
|
||||
ldnt1h { z30.h - z31.h }, pn8/z, [x0]
|
||||
ldnt1h { z0.h - z1.h }, pn15/z, [x0]
|
||||
ldnt1h { z0.h - z1.h }, pn8/z, [x30]
|
||||
ldnt1h { z0.h - z1.h }, pn8/z, [sp]
|
||||
ldnt1h { z0.h - z1.h }, pn8/z, [x0, #-16, mul vl]
|
||||
ldnt1h { z0.h - z1.h }, pn8/z, [x0, #14, mul vl]
|
||||
ldnt1h { z12.h - z13.h }, pn13/z, [x11, #-10, mul vl]
|
||||
|
||||
ldnt1h { z0.h - z3.h }, pn8/z, [x0]
|
||||
ldnt1h { z0.h - z3.h }, pn8/z, [x0, #0, mul vl]
|
||||
LDNT1H { Z0.H - Z3.H }, PN8/Z, [X0]
|
||||
ldnt1h { z28.h - z31.h }, pn8/z, [x0]
|
||||
ldnt1h { z0.h - z3.h }, pn15/z, [x0]
|
||||
ldnt1h { z0.h - z3.h }, pn8/z, [x30]
|
||||
ldnt1h { z0.h - z3.h }, pn8/z, [sp]
|
||||
ldnt1h { z0.h - z3.h }, pn8/z, [x0, #-32, mul vl]
|
||||
ldnt1h { z0.h - z3.h }, pn8/z, [x0, #28, mul vl]
|
||||
ldnt1h { z8.h - z11.h }, pn11/z, [x17, #20, mul vl]
|
||||
|
||||
ldnt1h { z0.h, z8.h }, pn8/z, [x0]
|
||||
ldnt1h { z0.h, z8.h }, pn8/z, [x0, #0, mul vl]
|
||||
LDNT1H { Z0.H, Z8.H }, PN8/Z, [X0]
|
||||
ldnt1h { z1.h, z9.h }, pn8/z, [x0]
|
||||
ldnt1h { z2.h, z10.h }, pn8/z, [x0]
|
||||
ldnt1h { z3.h, z11.h }, pn8/z, [x0]
|
||||
ldnt1h { z4.h, z12.h }, pn8/z, [x0]
|
||||
ldnt1h { z5.h, z13.h }, pn8/z, [x0]
|
||||
ldnt1h { z6.h, z14.h }, pn8/z, [x0]
|
||||
ldnt1h { z7.h, z15.h }, pn8/z, [x0]
|
||||
ldnt1h { z16.h, z24.h }, pn8/z, [x0]
|
||||
ldnt1h { z17.h, z25.h }, pn8/z, [x0]
|
||||
ldnt1h { z18.h, z26.h }, pn8/z, [x0]
|
||||
ldnt1h { z19.h, z27.h }, pn8/z, [x0]
|
||||
ldnt1h { z20.h, z28.h }, pn8/z, [x0]
|
||||
ldnt1h { z21.h, z29.h }, pn8/z, [x0]
|
||||
ldnt1h { z22.h, z30.h }, pn8/z, [x0]
|
||||
ldnt1h { z23.h, z31.h }, pn8/z, [x0]
|
||||
ldnt1h { z0.h, z8.h }, pn15/z, [x0]
|
||||
ldnt1h { z0.h, z8.h }, pn8/z, [x30]
|
||||
ldnt1h { z0.h, z8.h }, pn8/z, [sp]
|
||||
ldnt1h { z0.h, z8.h }, pn8/z, [x0, #-16, mul vl]
|
||||
ldnt1h { z0.h, z8.h }, pn8/z, [x0, #14, mul vl]
|
||||
ldnt1h { z3.h, z11.h }, pn10/z, [x22, #6, mul vl]
|
||||
|
||||
ldnt1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0]
|
||||
ldnt1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, #0, mul vl]
|
||||
LDNT1H { Z0.H, Z4.H, Z8.H, Z12.H }, PN8/Z, [X0]
|
||||
ldnt1h { z1.h, z5.h, z9.h, z13.h }, pn8/z, [x0]
|
||||
ldnt1h { z2.h, z6.h, z10.h, z14.h }, pn8/z, [x0]
|
||||
ldnt1h { z3.h, z7.h, z11.h, z15.h }, pn8/z, [x0]
|
||||
ldnt1h { z16.h, z20.h, z24.h, z28.h }, pn8/z, [x0]
|
||||
ldnt1h { z17.h, z21.h, z25.h, z29.h }, pn8/z, [x0]
|
||||
ldnt1h { z18.h, z22.h, z26.h, z30.h }, pn8/z, [x0]
|
||||
ldnt1h { z19.h, z23.h, z27.h, z31.h }, pn8/z, [x0]
|
||||
ldnt1h { z0.h, z4.h, z8.h, z12.h }, pn15/z, [x0]
|
||||
ldnt1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x30]
|
||||
ldnt1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [sp]
|
||||
ldnt1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, #-32, mul vl]
|
||||
ldnt1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, #28, mul vl]
|
||||
ldnt1h { z2.h, z6.h, z10.h, z14.h }, pn14/z, [x29, #8, mul vl]
|
||||
|
||||
ldnt1h { z0.h - z1.h }, pn8/z, [x0, x1, lsl 1]
|
||||
ldnt1h { z0.h - z1.h }, pn8/z, [x0, x1, lsl #1]
|
||||
LDNT1H { Z0.H - Z1.H }, PN8/Z, [X0, X1, LSL #1]
|
||||
ldnt1h { z30.h - z31.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ldnt1h { z0.h - z1.h }, pn15/z, [x0, x1, lsl #1]
|
||||
ldnt1h { z0.h - z1.h }, pn8/z, [x30, x1, lsl #1]
|
||||
ldnt1h { z0.h - z1.h }, pn8/z, [sp, x1, lsl #1]
|
||||
ldnt1h { z0.h - z1.h }, pn8/z, [x0, x30, lsl #1]
|
||||
ldnt1h { z0.h - z1.h }, pn8/z, [x0, xzr, lsl #1]
|
||||
ldnt1h { z14.h - z15.h }, pn9/z, [x26, x3, lsl #1]
|
||||
|
||||
ldnt1h { z0.h - z3.h }, pn8/z, [x0, x1, lsl 1]
|
||||
ldnt1h { z0.h - z3.h }, pn8/z, [x0, x1, lsl #1]
|
||||
LDNT1H { Z0.H - Z3.H }, PN8/Z, [X0, X1, LSL #1]
|
||||
ldnt1h { z28.h - z31.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ldnt1h { z0.h - z3.h }, pn15/z, [x0, x1, lsl #1]
|
||||
ldnt1h { z0.h - z3.h }, pn8/z, [x30, x1, lsl #1]
|
||||
ldnt1h { z0.h - z3.h }, pn8/z, [sp, x1, lsl #1]
|
||||
ldnt1h { z0.h - z3.h }, pn8/z, [x0, x30, lsl #1]
|
||||
ldnt1h { z0.h - z3.h }, pn8/z, [x0, xzr, lsl #1]
|
||||
ldnt1h { z8.h - z11.h }, pn11/z, [x27, x1, lsl #1]
|
||||
|
||||
ldnt1h { z0.h, z8.h }, pn8/z, [x0, x1, lsl 1]
|
||||
ldnt1h { z0.h, z8.h }, pn8/z, [x0, x1, lsl #1]
|
||||
LDNT1H { Z0.H, Z8.H }, PN8/Z, [X0, X1, LSL #1]
|
||||
ldnt1h { z1.h, z9.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ldnt1h { z2.h, z10.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ldnt1h { z3.h, z11.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ldnt1h { z4.h, z12.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ldnt1h { z5.h, z13.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ldnt1h { z6.h, z14.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ldnt1h { z7.h, z15.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ldnt1h { z16.h, z24.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ldnt1h { z17.h, z25.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ldnt1h { z18.h, z26.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ldnt1h { z19.h, z27.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ldnt1h { z20.h, z28.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ldnt1h { z21.h, z29.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ldnt1h { z22.h, z30.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ldnt1h { z23.h, z31.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ldnt1h { z0.h, z8.h }, pn15/z, [x0, x1, lsl #1]
|
||||
ldnt1h { z0.h, z8.h }, pn8/z, [x30, x1, lsl #1]
|
||||
ldnt1h { z0.h, z8.h }, pn8/z, [sp, x1, lsl #1]
|
||||
ldnt1h { z0.h, z8.h }, pn8/z, [x0, x30, lsl #1]
|
||||
ldnt1h { z0.h, z8.h }, pn8/z, [x0, xzr, lsl #1]
|
||||
ldnt1h { z5.h, z13.h }, pn14/z, [x15, x24, lsl #1]
|
||||
|
||||
ldnt1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, x1, lsl 1]
|
||||
ldnt1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, x1, lsl #1]
|
||||
LDNT1H { Z0.H, Z4.H, Z8.H, Z12.H }, PN8/Z, [X0, X1, LSL #1]
|
||||
ldnt1h { z1.h, z5.h, z9.h, z13.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ldnt1h { z2.h, z6.h, z10.h, z14.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ldnt1h { z3.h, z7.h, z11.h, z15.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ldnt1h { z16.h, z20.h, z24.h, z28.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ldnt1h { z17.h, z21.h, z25.h, z29.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ldnt1h { z18.h, z22.h, z26.h, z30.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ldnt1h { z19.h, z23.h, z27.h, z31.h }, pn8/z, [x0, x1, lsl #1]
|
||||
ldnt1h { z0.h, z4.h, z8.h, z12.h }, pn15/z, [x0, x1, lsl #1]
|
||||
ldnt1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x30, x1, lsl #1]
|
||||
ldnt1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [sp, x1, lsl #1]
|
||||
ldnt1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, x30, lsl #1]
|
||||
ldnt1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, xzr, lsl #1]
|
||||
ldnt1h { z17.h, z21.h, z25.h, z29.h }, pn11/z, [x4, x6, lsl #1]
|
||||
|
||||
st1h { z0.h - z1.h }, pn8, [x0]
|
||||
st1h { z0.h - z1.h }, pn8, [x0, #0, mul vl]
|
||||
ST1H { Z0.H - Z1.H }, PN8, [X0]
|
||||
st1h { z30.h - z31.h }, pn8, [x0]
|
||||
st1h { z0.h - z1.h }, pn15, [x0]
|
||||
st1h { z0.h - z1.h }, pn8, [x30]
|
||||
st1h { z0.h - z1.h }, pn8, [sp]
|
||||
st1h { z0.h - z1.h }, pn8, [x0, #-16, mul vl]
|
||||
st1h { z0.h - z1.h }, pn8, [x0, #14, mul vl]
|
||||
st1h { z12.h - z13.h }, pn13, [x11, #-10, mul vl]
|
||||
|
||||
st1h { z0.h - z3.h }, pn8, [x0]
|
||||
st1h { z0.h - z3.h }, pn8, [x0, #0, mul vl]
|
||||
ST1H { Z0.H - Z3.H }, PN8, [X0]
|
||||
st1h { z28.h - z31.h }, pn8, [x0]
|
||||
st1h { z0.h - z3.h }, pn15, [x0]
|
||||
st1h { z0.h - z3.h }, pn8, [x30]
|
||||
st1h { z0.h - z3.h }, pn8, [sp]
|
||||
st1h { z0.h - z3.h }, pn8, [x0, #-32, mul vl]
|
||||
st1h { z0.h - z3.h }, pn8, [x0, #28, mul vl]
|
||||
st1h { z8.h - z11.h }, pn11, [x17, #20, mul vl]
|
||||
|
||||
st1h { z0.h, z8.h }, pn8, [x0]
|
||||
st1h { z0.h, z8.h }, pn8, [x0, #0, mul vl]
|
||||
ST1H { Z0.H, Z8.H }, PN8, [X0]
|
||||
st1h { z1.h, z9.h }, pn8, [x0]
|
||||
st1h { z2.h, z10.h }, pn8, [x0]
|
||||
st1h { z3.h, z11.h }, pn8, [x0]
|
||||
st1h { z4.h, z12.h }, pn8, [x0]
|
||||
st1h { z5.h, z13.h }, pn8, [x0]
|
||||
st1h { z6.h, z14.h }, pn8, [x0]
|
||||
st1h { z7.h, z15.h }, pn8, [x0]
|
||||
st1h { z16.h, z24.h }, pn8, [x0]
|
||||
st1h { z17.h, z25.h }, pn8, [x0]
|
||||
st1h { z18.h, z26.h }, pn8, [x0]
|
||||
st1h { z19.h, z27.h }, pn8, [x0]
|
||||
st1h { z20.h, z28.h }, pn8, [x0]
|
||||
st1h { z21.h, z29.h }, pn8, [x0]
|
||||
st1h { z22.h, z30.h }, pn8, [x0]
|
||||
st1h { z23.h, z31.h }, pn8, [x0]
|
||||
st1h { z0.h, z8.h }, pn15, [x0]
|
||||
st1h { z0.h, z8.h }, pn8, [x30]
|
||||
st1h { z0.h, z8.h }, pn8, [sp]
|
||||
st1h { z0.h, z8.h }, pn8, [x0, #-16, mul vl]
|
||||
st1h { z0.h, z8.h }, pn8, [x0, #14, mul vl]
|
||||
st1h { z3.h, z11.h }, pn10, [x22, #6, mul vl]
|
||||
|
||||
st1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0]
|
||||
st1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, #0, mul vl]
|
||||
ST1H { Z0.H, Z4.H, Z8.H, Z12.H }, PN8, [X0]
|
||||
st1h { z1.h, z5.h, z9.h, z13.h }, pn8, [x0]
|
||||
st1h { z2.h, z6.h, z10.h, z14.h }, pn8, [x0]
|
||||
st1h { z3.h, z7.h, z11.h, z15.h }, pn8, [x0]
|
||||
st1h { z16.h, z20.h, z24.h, z28.h }, pn8, [x0]
|
||||
st1h { z17.h, z21.h, z25.h, z29.h }, pn8, [x0]
|
||||
st1h { z18.h, z22.h, z26.h, z30.h }, pn8, [x0]
|
||||
st1h { z19.h, z23.h, z27.h, z31.h }, pn8, [x0]
|
||||
st1h { z0.h, z4.h, z8.h, z12.h }, pn15, [x0]
|
||||
st1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x30]
|
||||
st1h { z0.h, z4.h, z8.h, z12.h }, pn8, [sp]
|
||||
st1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, #-32, mul vl]
|
||||
st1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, #28, mul vl]
|
||||
st1h { z2.h, z6.h, z10.h, z14.h }, pn14, [x29, #8, mul vl]
|
||||
|
||||
st1h { z0.h - z1.h }, pn8, [x0, x1, lsl 1]
|
||||
st1h { z0.h - z1.h }, pn8, [x0, x1, lsl #1]
|
||||
ST1H { Z0.H - Z1.H }, PN8, [X0, X1, LSL #1]
|
||||
st1h { z30.h - z31.h }, pn8, [x0, x1, lsl #1]
|
||||
st1h { z0.h - z1.h }, pn15, [x0, x1, lsl #1]
|
||||
st1h { z0.h - z1.h }, pn8, [x30, x1, lsl #1]
|
||||
st1h { z0.h - z1.h }, pn8, [sp, x1, lsl #1]
|
||||
st1h { z0.h - z1.h }, pn8, [x0, x30, lsl #1]
|
||||
st1h { z0.h - z1.h }, pn8, [x0, xzr, lsl #1]
|
||||
st1h { z14.h - z15.h }, pn9, [x26, x3, lsl #1]
|
||||
|
||||
st1h { z0.h - z3.h }, pn8, [x0, x1, lsl 1]
|
||||
st1h { z0.h - z3.h }, pn8, [x0, x1, lsl #1]
|
||||
ST1H { Z0.H - Z3.H }, PN8, [X0, X1, LSL #1]
|
||||
st1h { z28.h - z31.h }, pn8, [x0, x1, lsl #1]
|
||||
st1h { z0.h - z3.h }, pn15, [x0, x1, lsl #1]
|
||||
st1h { z0.h - z3.h }, pn8, [x30, x1, lsl #1]
|
||||
st1h { z0.h - z3.h }, pn8, [sp, x1, lsl #1]
|
||||
st1h { z0.h - z3.h }, pn8, [x0, x30, lsl #1]
|
||||
st1h { z0.h - z3.h }, pn8, [x0, xzr, lsl #1]
|
||||
st1h { z8.h - z11.h }, pn11, [x27, x1, lsl #1]
|
||||
|
||||
st1h { z0.h, z8.h }, pn8, [x0, x1, lsl 1]
|
||||
st1h { z0.h, z8.h }, pn8, [x0, x1, lsl #1]
|
||||
ST1H { Z0.H, Z8.H }, PN8, [X0, X1, LSL #1]
|
||||
st1h { z1.h, z9.h }, pn8, [x0, x1, lsl #1]
|
||||
st1h { z2.h, z10.h }, pn8, [x0, x1, lsl #1]
|
||||
st1h { z3.h, z11.h }, pn8, [x0, x1, lsl #1]
|
||||
st1h { z4.h, z12.h }, pn8, [x0, x1, lsl #1]
|
||||
st1h { z5.h, z13.h }, pn8, [x0, x1, lsl #1]
|
||||
st1h { z6.h, z14.h }, pn8, [x0, x1, lsl #1]
|
||||
st1h { z7.h, z15.h }, pn8, [x0, x1, lsl #1]
|
||||
st1h { z16.h, z24.h }, pn8, [x0, x1, lsl #1]
|
||||
st1h { z17.h, z25.h }, pn8, [x0, x1, lsl #1]
|
||||
st1h { z18.h, z26.h }, pn8, [x0, x1, lsl #1]
|
||||
st1h { z19.h, z27.h }, pn8, [x0, x1, lsl #1]
|
||||
st1h { z20.h, z28.h }, pn8, [x0, x1, lsl #1]
|
||||
st1h { z21.h, z29.h }, pn8, [x0, x1, lsl #1]
|
||||
st1h { z22.h, z30.h }, pn8, [x0, x1, lsl #1]
|
||||
st1h { z23.h, z31.h }, pn8, [x0, x1, lsl #1]
|
||||
st1h { z0.h, z8.h }, pn15, [x0, x1, lsl #1]
|
||||
st1h { z0.h, z8.h }, pn8, [x30, x1, lsl #1]
|
||||
st1h { z0.h, z8.h }, pn8, [sp, x1, lsl #1]
|
||||
st1h { z0.h, z8.h }, pn8, [x0, x30, lsl #1]
|
||||
st1h { z0.h, z8.h }, pn8, [x0, xzr, lsl #1]
|
||||
st1h { z5.h, z13.h }, pn14, [x15, x24, lsl #1]
|
||||
|
||||
st1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, x1, lsl 1]
|
||||
st1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, x1, lsl #1]
|
||||
ST1H { Z0.H, Z4.H, Z8.H, Z12.H }, PN8, [X0, X1, LSL #1]
|
||||
st1h { z1.h, z5.h, z9.h, z13.h }, pn8, [x0, x1, lsl #1]
|
||||
st1h { z2.h, z6.h, z10.h, z14.h }, pn8, [x0, x1, lsl #1]
|
||||
st1h { z3.h, z7.h, z11.h, z15.h }, pn8, [x0, x1, lsl #1]
|
||||
st1h { z16.h, z20.h, z24.h, z28.h }, pn8, [x0, x1, lsl #1]
|
||||
st1h { z17.h, z21.h, z25.h, z29.h }, pn8, [x0, x1, lsl #1]
|
||||
st1h { z18.h, z22.h, z26.h, z30.h }, pn8, [x0, x1, lsl #1]
|
||||
st1h { z19.h, z23.h, z27.h, z31.h }, pn8, [x0, x1, lsl #1]
|
||||
st1h { z0.h, z4.h, z8.h, z12.h }, pn15, [x0, x1, lsl #1]
|
||||
st1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x30, x1, lsl #1]
|
||||
st1h { z0.h, z4.h, z8.h, z12.h }, pn8, [sp, x1, lsl #1]
|
||||
st1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, x30, lsl #1]
|
||||
st1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, xzr, lsl #1]
|
||||
st1h { z17.h, z21.h, z25.h, z29.h }, pn11, [x4, x6, lsl #1]
|
||||
|
||||
stnt1h { z0.h - z1.h }, pn8, [x0]
|
||||
stnt1h { z0.h - z1.h }, pn8, [x0, #0, mul vl]
|
||||
STNT1H { Z0.H - Z1.H }, PN8, [X0]
|
||||
stnt1h { z30.h - z31.h }, pn8, [x0]
|
||||
stnt1h { z0.h - z1.h }, pn15, [x0]
|
||||
stnt1h { z0.h - z1.h }, pn8, [x30]
|
||||
stnt1h { z0.h - z1.h }, pn8, [sp]
|
||||
stnt1h { z0.h - z1.h }, pn8, [x0, #-16, mul vl]
|
||||
stnt1h { z0.h - z1.h }, pn8, [x0, #14, mul vl]
|
||||
stnt1h { z12.h - z13.h }, pn13, [x11, #-10, mul vl]
|
||||
|
||||
stnt1h { z0.h - z3.h }, pn8, [x0]
|
||||
stnt1h { z0.h - z3.h }, pn8, [x0, #0, mul vl]
|
||||
STNT1H { Z0.H - Z3.H }, PN8, [X0]
|
||||
stnt1h { z28.h - z31.h }, pn8, [x0]
|
||||
stnt1h { z0.h - z3.h }, pn15, [x0]
|
||||
stnt1h { z0.h - z3.h }, pn8, [x30]
|
||||
stnt1h { z0.h - z3.h }, pn8, [sp]
|
||||
stnt1h { z0.h - z3.h }, pn8, [x0, #-32, mul vl]
|
||||
stnt1h { z0.h - z3.h }, pn8, [x0, #28, mul vl]
|
||||
stnt1h { z8.h - z11.h }, pn11, [x17, #20, mul vl]
|
||||
|
||||
stnt1h { z0.h, z8.h }, pn8, [x0]
|
||||
stnt1h { z0.h, z8.h }, pn8, [x0, #0, mul vl]
|
||||
STNT1H { Z0.H, Z8.H }, PN8, [X0]
|
||||
stnt1h { z1.h, z9.h }, pn8, [x0]
|
||||
stnt1h { z2.h, z10.h }, pn8, [x0]
|
||||
stnt1h { z3.h, z11.h }, pn8, [x0]
|
||||
stnt1h { z4.h, z12.h }, pn8, [x0]
|
||||
stnt1h { z5.h, z13.h }, pn8, [x0]
|
||||
stnt1h { z6.h, z14.h }, pn8, [x0]
|
||||
stnt1h { z7.h, z15.h }, pn8, [x0]
|
||||
stnt1h { z16.h, z24.h }, pn8, [x0]
|
||||
stnt1h { z17.h, z25.h }, pn8, [x0]
|
||||
stnt1h { z18.h, z26.h }, pn8, [x0]
|
||||
stnt1h { z19.h, z27.h }, pn8, [x0]
|
||||
stnt1h { z20.h, z28.h }, pn8, [x0]
|
||||
stnt1h { z21.h, z29.h }, pn8, [x0]
|
||||
stnt1h { z22.h, z30.h }, pn8, [x0]
|
||||
stnt1h { z23.h, z31.h }, pn8, [x0]
|
||||
stnt1h { z0.h, z8.h }, pn15, [x0]
|
||||
stnt1h { z0.h, z8.h }, pn8, [x30]
|
||||
stnt1h { z0.h, z8.h }, pn8, [sp]
|
||||
stnt1h { z0.h, z8.h }, pn8, [x0, #-16, mul vl]
|
||||
stnt1h { z0.h, z8.h }, pn8, [x0, #14, mul vl]
|
||||
stnt1h { z3.h, z11.h }, pn10, [x22, #6, mul vl]
|
||||
|
||||
stnt1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0]
|
||||
stnt1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, #0, mul vl]
|
||||
STNT1H { Z0.H, Z4.H, Z8.H, Z12.H }, PN8, [X0]
|
||||
stnt1h { z1.h, z5.h, z9.h, z13.h }, pn8, [x0]
|
||||
stnt1h { z2.h, z6.h, z10.h, z14.h }, pn8, [x0]
|
||||
stnt1h { z3.h, z7.h, z11.h, z15.h }, pn8, [x0]
|
||||
stnt1h { z16.h, z20.h, z24.h, z28.h }, pn8, [x0]
|
||||
stnt1h { z17.h, z21.h, z25.h, z29.h }, pn8, [x0]
|
||||
stnt1h { z18.h, z22.h, z26.h, z30.h }, pn8, [x0]
|
||||
stnt1h { z19.h, z23.h, z27.h, z31.h }, pn8, [x0]
|
||||
stnt1h { z0.h, z4.h, z8.h, z12.h }, pn15, [x0]
|
||||
stnt1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x30]
|
||||
stnt1h { z0.h, z4.h, z8.h, z12.h }, pn8, [sp]
|
||||
stnt1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, #-32, mul vl]
|
||||
stnt1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, #28, mul vl]
|
||||
stnt1h { z2.h, z6.h, z10.h, z14.h }, pn14, [x29, #8, mul vl]
|
||||
|
||||
stnt1h { z0.h - z1.h }, pn8, [x0, x1, lsl 1]
|
||||
stnt1h { z0.h - z1.h }, pn8, [x0, x1, lsl #1]
|
||||
STNT1H { Z0.H - Z1.H }, PN8, [X0, X1, LSL #1]
|
||||
stnt1h { z30.h - z31.h }, pn8, [x0, x1, lsl #1]
|
||||
stnt1h { z0.h - z1.h }, pn15, [x0, x1, lsl #1]
|
||||
stnt1h { z0.h - z1.h }, pn8, [x30, x1, lsl #1]
|
||||
stnt1h { z0.h - z1.h }, pn8, [sp, x1, lsl #1]
|
||||
stnt1h { z0.h - z1.h }, pn8, [x0, x30, lsl #1]
|
||||
stnt1h { z0.h - z1.h }, pn8, [x0, xzr, lsl #1]
|
||||
stnt1h { z14.h - z15.h }, pn9, [x26, x3, lsl #1]
|
||||
|
||||
stnt1h { z0.h - z3.h }, pn8, [x0, x1, lsl 1]
|
||||
stnt1h { z0.h - z3.h }, pn8, [x0, x1, lsl #1]
|
||||
STNT1H { Z0.H - Z3.H }, PN8, [X0, X1, LSL #1]
|
||||
stnt1h { z28.h - z31.h }, pn8, [x0, x1, lsl #1]
|
||||
stnt1h { z0.h - z3.h }, pn15, [x0, x1, lsl #1]
|
||||
stnt1h { z0.h - z3.h }, pn8, [x30, x1, lsl #1]
|
||||
stnt1h { z0.h - z3.h }, pn8, [sp, x1, lsl #1]
|
||||
stnt1h { z0.h - z3.h }, pn8, [x0, x30, lsl #1]
|
||||
stnt1h { z0.h - z3.h }, pn8, [x0, xzr, lsl #1]
|
||||
stnt1h { z8.h - z11.h }, pn11, [x27, x1, lsl #1]
|
||||
|
||||
stnt1h { z0.h, z8.h }, pn8, [x0, x1, lsl 1]
|
||||
stnt1h { z0.h, z8.h }, pn8, [x0, x1, lsl #1]
|
||||
STNT1H { Z0.H, Z8.H }, PN8, [X0, X1, LSL #1]
|
||||
stnt1h { z1.h, z9.h }, pn8, [x0, x1, lsl #1]
|
||||
stnt1h { z2.h, z10.h }, pn8, [x0, x1, lsl #1]
|
||||
stnt1h { z3.h, z11.h }, pn8, [x0, x1, lsl #1]
|
||||
stnt1h { z4.h, z12.h }, pn8, [x0, x1, lsl #1]
|
||||
stnt1h { z5.h, z13.h }, pn8, [x0, x1, lsl #1]
|
||||
stnt1h { z6.h, z14.h }, pn8, [x0, x1, lsl #1]
|
||||
stnt1h { z7.h, z15.h }, pn8, [x0, x1, lsl #1]
|
||||
stnt1h { z16.h, z24.h }, pn8, [x0, x1, lsl #1]
|
||||
stnt1h { z17.h, z25.h }, pn8, [x0, x1, lsl #1]
|
||||
stnt1h { z18.h, z26.h }, pn8, [x0, x1, lsl #1]
|
||||
stnt1h { z19.h, z27.h }, pn8, [x0, x1, lsl #1]
|
||||
stnt1h { z20.h, z28.h }, pn8, [x0, x1, lsl #1]
|
||||
stnt1h { z21.h, z29.h }, pn8, [x0, x1, lsl #1]
|
||||
stnt1h { z22.h, z30.h }, pn8, [x0, x1, lsl #1]
|
||||
stnt1h { z23.h, z31.h }, pn8, [x0, x1, lsl #1]
|
||||
stnt1h { z0.h, z8.h }, pn15, [x0, x1, lsl #1]
|
||||
stnt1h { z0.h, z8.h }, pn8, [x30, x1, lsl #1]
|
||||
stnt1h { z0.h, z8.h }, pn8, [sp, x1, lsl #1]
|
||||
stnt1h { z0.h, z8.h }, pn8, [x0, x30, lsl #1]
|
||||
stnt1h { z0.h, z8.h }, pn8, [x0, xzr, lsl #1]
|
||||
stnt1h { z5.h, z13.h }, pn14, [x15, x24, lsl #1]
|
||||
|
||||
stnt1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, x1, lsl 1]
|
||||
stnt1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, x1, lsl #1]
|
||||
STNT1H { Z0.H, Z4.H, Z8.H, Z12.H }, PN8, [X0, X1, LSL #1]
|
||||
stnt1h { z1.h, z5.h, z9.h, z13.h }, pn8, [x0, x1, lsl #1]
|
||||
stnt1h { z2.h, z6.h, z10.h, z14.h }, pn8, [x0, x1, lsl #1]
|
||||
stnt1h { z3.h, z7.h, z11.h, z15.h }, pn8, [x0, x1, lsl #1]
|
||||
stnt1h { z16.h, z20.h, z24.h, z28.h }, pn8, [x0, x1, lsl #1]
|
||||
stnt1h { z17.h, z21.h, z25.h, z29.h }, pn8, [x0, x1, lsl #1]
|
||||
stnt1h { z18.h, z22.h, z26.h, z30.h }, pn8, [x0, x1, lsl #1]
|
||||
stnt1h { z19.h, z23.h, z27.h, z31.h }, pn8, [x0, x1, lsl #1]
|
||||
stnt1h { z0.h, z4.h, z8.h, z12.h }, pn15, [x0, x1, lsl #1]
|
||||
stnt1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x30, x1, lsl #1]
|
||||
stnt1h { z0.h, z4.h, z8.h, z12.h }, pn8, [sp, x1, lsl #1]
|
||||
stnt1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, x30, lsl #1]
|
||||
stnt1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, xzr, lsl #1]
|
||||
stnt1h { z17.h, z21.h, z25.h, z29.h }, pn11, [x4, x6, lsl #1]
|
||||
3
gas/testsuite/gas/aarch64/sme2-5-invalid.d
Normal file
3
gas/testsuite/gas/aarch64/sme2-5-invalid.d
Normal file
@ -0,0 +1,3 @@
|
||||
#as: -march=armv8-a
|
||||
#source: sme2-5-invalid.s
|
||||
#error_output: sme2-5-invalid.l
|
||||
75
gas/testsuite/gas/aarch64/sme2-5-invalid.l
Normal file
75
gas/testsuite/gas/aarch64/sme2-5-invalid.l
Normal file
@ -0,0 +1,75 @@
|
||||
[^ :]+: Assembler messages:
|
||||
[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `ld1w 0,pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 2 -- `ld1w {z0\.s-z1\.s},0,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1w {z0\.s-z1\.s},pn8/z,0'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 1 -- `ld1w {z0\.s-z2\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1w {z1\.s-z2\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1w {z0\.s-z1\.s},p8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `ld1w {z0\.s-z1\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: ld1w {z0\.s-z1\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `ld1w {z0\.s-z1\.s},pn8/m,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: ld1w {z0\.s-z1\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `ld1w {z0\.s-z1\.s},pn8\.s,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: ld1w {z0\.s-z1\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1w {z0\.s-z1\.s},pn0/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1w {z0\.s-z1\.s},pn7/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1w {z0\.s-z1\.s},pn8/z,\[w0,w1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1w {z0\.s-z1\.s},pn8/z,\[xzr,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ld1w {z0\.s-z1\.s},pn8/z,\[sp,sp,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1w {z0\.s-z1\.s},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1w {z0\.s-z1\.s},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1w {z0\.s-z1\.s},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1w {z0\.s-z1\.s},pn8/z,\[x0,x1,lsl#4\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1w {z0\.s-z1\.s},pn8/z,\[x0,w1,sxtw#2\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1w {z0\.s-z1\.s},pn8/z,\[x0,w1,uxtw#2\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1w {z1\.s-z4\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1w {z2\.s-z5\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1w {z3\.s-z6\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1w {z0\.s-z3\.s},p8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `ld1w {z0\.s-z3\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: ld1w {z0\.s-z3\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `ld1w {z0\.s-z3\.s},pn8/m,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: ld1w {z0\.s-z3\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `ld1w {z0\.s-z3\.s},pn8\.s,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: ld1w {z0\.s-z3\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1w {z0\.s-z3\.s},pn0/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `ld1w {z0\.s-z3\.s},pn7/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1w {z0\.s-z3\.s},pn8/z,\[w0,w1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1w {z0\.s-z3\.s},pn8/z,\[xzr,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ld1w {z0\.s-z3\.s},pn8/z,\[sp,sp,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1w {z0\.s-z3\.s},pn8/z,\[x0,x1\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1w {z0\.s-z3\.s},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1w {z0\.s-z3\.s},pn8/z,\[x0,x1,lsl#3\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1w {z0\.s-z3\.s},pn8/z,\[x0,x1,lsl#4\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1w {z0\.s-z3\.s},pn8/z,\[x0,w1,sxtw#2\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1w {z0\.s-z3\.s},pn8/z,\[x0,w1,uxtw#2\]'
|
||||
[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1w {z0\.s,z2\.s},pn8/z,\[x0,x1,lsl#2\]`
|
||||
[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1w {z0\.s,z3\.s},pn8/z,\[x0,x1,lsl#2\]`
|
||||
[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1w {z0\.s,z4\.s},pn8/z,\[x0,x1,lsl#2\]`
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1w {z8\.s,z16\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1w {z24\.s,z0\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: the register list must have a stride of 1 or 8 at operand 1 -- `ld1w {z8\.s,z0\.s},pn8/z,\[x0,x1,lsl#2\]`
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `ld1w {z0\.h,z8\.h},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: ld1w {z0\.s, z8\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1w {z0\.s,z8\.s},p8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1w {z0\.s,z8\.s},pn8/z,\[w0,w30,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1w {z0\.s,z8\.s},pn8/z,\[xzr,xzr,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ld1w {z0\.s,z8\.s},pn8/z,\[x0,sp,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1w {z0\.s,z8\.s},pn8/z,\[x0,x1,lsl#1\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1w {z4\.s,z8\.s,z12\.s,z16\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `ld1w {z20\.s,z24\.s,z28\.s,z0\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `ld1w {z0\.h,z4\.h,z8\.h,z12\.h},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: ld1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^ :]+:[0-9]+: Error: expected a single-register list at operand 1 -- `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},p8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 3 -- `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[w0,w30,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[xzr,xzr,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x0,sp,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x0,x1,lsl#1\]'
|
||||
62
gas/testsuite/gas/aarch64/sme2-5-invalid.s
Normal file
62
gas/testsuite/gas/aarch64/sme2-5-invalid.s
Normal file
@ -0,0 +1,62 @@
|
||||
ld1w 0, pn8/z, [x0]
|
||||
ld1w { z0.s - z1.s }, 0, [x0]
|
||||
ld1w { z0.s - z1.s }, pn8/z, 0
|
||||
|
||||
ld1w { z0.s - z2.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z1.s - z2.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z0.s - z1.s }, p8/z, [x0, x1, lsl #2]
|
||||
ld1w { z0.s - z1.s }, pn8, [x0, x1, lsl #2]
|
||||
ld1w { z0.s - z1.s }, pn8/m, [x0, x1, lsl #2]
|
||||
ld1w { z0.s - z1.s }, pn8.s, [x0, x1, lsl #2]
|
||||
ld1w { z0.s - z1.s }, pn0/z, [x0, x1, lsl #2]
|
||||
ld1w { z0.s - z1.s }, pn7/z, [x0, x1, lsl #2]
|
||||
ld1w { z0.s - z1.s }, pn8/z, [w0, w1, lsl #2]
|
||||
ld1w { z0.s - z1.s }, pn8/z, [xzr, x1, lsl #2]
|
||||
ld1w { z0.s - z1.s }, pn8/z, [sp, sp, lsl #2]
|
||||
ld1w { z0.s - z1.s }, pn8/z, [x0, x1]
|
||||
ld1w { z0.s - z1.s }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1w { z0.s - z1.s }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1w { z0.s - z1.s }, pn8/z, [x0, x1, lsl #4]
|
||||
ld1w { z0.s - z1.s }, pn8/z, [x0, w1, sxtw #2]
|
||||
ld1w { z0.s - z1.s }, pn8/z, [x0, w1, uxtw #2]
|
||||
|
||||
ld1w { z1.s - z4.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z2.s - z5.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z3.s - z6.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z0.s - z3.s }, p8/z, [x0, x1, lsl #2]
|
||||
ld1w { z0.s - z3.s }, pn8, [x0, x1, lsl #2]
|
||||
ld1w { z0.s - z3.s }, pn8/m, [x0, x1, lsl #2]
|
||||
ld1w { z0.s - z3.s }, pn8.s, [x0, x1, lsl #2]
|
||||
ld1w { z0.s - z3.s }, pn0/z, [x0, x1, lsl #2]
|
||||
ld1w { z0.s - z3.s }, pn7/z, [x0, x1, lsl #2]
|
||||
ld1w { z0.s - z3.s }, pn8/z, [w0, w1, lsl #2]
|
||||
ld1w { z0.s - z3.s }, pn8/z, [xzr, x1, lsl #2]
|
||||
ld1w { z0.s - z3.s }, pn8/z, [sp, sp, lsl #2]
|
||||
ld1w { z0.s - z3.s }, pn8/z, [x0, x1]
|
||||
ld1w { z0.s - z3.s }, pn8/z, [x0, x1, lsl #1]
|
||||
ld1w { z0.s - z3.s }, pn8/z, [x0, x1, lsl #3]
|
||||
ld1w { z0.s - z3.s }, pn8/z, [x0, x1, lsl #4]
|
||||
ld1w { z0.s - z3.s }, pn8/z, [x0, w1, sxtw #2]
|
||||
ld1w { z0.s - z3.s }, pn8/z, [x0, w1, uxtw #2]
|
||||
|
||||
ld1w { z0.s, z2.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z0.s, z3.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z0.s, z4.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z8.s, z16.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z24.s, z0.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z8.s, z0.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z0.h, z8.h }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z0.s, z8.s }, p8/z, [x0, x1, lsl #2]
|
||||
ld1w { z0.s, z8.s }, pn8/z, [w0, w30, lsl #2]
|
||||
ld1w { z0.s, z8.s }, pn8/z, [xzr, xzr, lsl #2]
|
||||
ld1w { z0.s, z8.s }, pn8/z, [x0, sp, lsl #2]
|
||||
ld1w { z0.s, z8.s }, pn8/z, [x0, x1, lsl #1]
|
||||
|
||||
ld1w { z4.s, z8.s, z12.s, z16.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z20.s, z24.s, z28.s, z0.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z0.s, z4.s, z8.s, z12.s }, p8/z, [x0, x1, lsl #2]
|
||||
ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [w0, w30, lsl #2]
|
||||
ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [xzr, xzr, lsl #2]
|
||||
ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, sp, lsl #2]
|
||||
ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, x1, lsl #1]
|
||||
3
gas/testsuite/gas/aarch64/sme2-5-noarch.d
Normal file
3
gas/testsuite/gas/aarch64/sme2-5-noarch.d
Normal file
@ -0,0 +1,3 @@
|
||||
#as: -march=armv8-a+sme
|
||||
#source: sme2-5.s
|
||||
#error_output: sme2-5-noarch.l
|
||||
481
gas/testsuite/gas/aarch64/sme2-5-noarch.l
Normal file
481
gas/testsuite/gas/aarch64/sme2-5-noarch.l
Normal file
@ -0,0 +1,481 @@
|
||||
[^ :]+: Assembler messages:
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z1\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z1\.s},pn8/z,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {Z0\.S-Z1\.S},PN8/Z,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z30\.s-z31\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z1\.s},pn15/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z1\.s},pn8/z,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z1\.s},pn8/z,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z1\.s},pn8/z,\[x0,#-16,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z1\.s},pn8/z,\[x0,#14,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z12\.s-z13\.s},pn13/z,\[x11,#-10,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z3\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z3\.s},pn8/z,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {Z0\.S-Z3\.S},PN8/Z,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z28\.s-z31\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z3\.s},pn15/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z3\.s},pn8/z,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z3\.s},pn8/z,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z3\.s},pn8/z,\[x0,#-32,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z3\.s},pn8/z,\[x0,#28,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z8\.s-z11\.s},pn11/z,\[x17,#20,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z8\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z8\.s},pn8/z,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {Z0\.S,Z8\.S},PN8/Z,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z1\.s,z9\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z2\.s,z10\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z3\.s,z11\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z4\.s,z12\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z5\.s,z13\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z6\.s,z14\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z7\.s,z15\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z16\.s,z24\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z17\.s,z25\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z18\.s,z26\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z19\.s,z27\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z20\.s,z28\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z21\.s,z29\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z22\.s,z30\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z23\.s,z31\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z8\.s},pn15/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z8\.s},pn8/z,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z8\.s},pn8/z,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z8\.s},pn8/z,\[x0,#-16,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z8\.s},pn8/z,\[x0,#14,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z3\.s,z11\.s},pn10/z,\[x22,#6,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {Z0\.S,Z4\.S,Z8\.S,Z12\.S},PN8/Z,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z1\.s,z5\.s,z9\.s,z13\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z2\.s,z6\.s,z10\.s,z14\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z3\.s,z7\.s,z11\.s,z15\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z16\.s,z20\.s,z24\.s,z28\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z17\.s,z21\.s,z25\.s,z29\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z18\.s,z22\.s,z26\.s,z30\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z19\.s,z23\.s,z27\.s,z31\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},pn15/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x0,#-32,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x0,#28,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z2\.s,z6\.s,z10\.s,z14\.s},pn14/z,\[x29,#8,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z1\.s},pn8/z,\[x0,x1,lsl 2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z1\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {Z0\.S-Z1\.S},PN8/Z,\[X0,X1,LSL#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z30\.s-z31\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z1\.s},pn15/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z1\.s},pn8/z,\[x30,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z1\.s},pn8/z,\[sp,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z1\.s},pn8/z,\[x0,x30,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z1\.s},pn8/z,\[x0,xzr,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z14\.s-z15\.s},pn9/z,\[x26,x3,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z3\.s},pn8/z,\[x0,x1,lsl 2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z3\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {Z0\.S-Z3\.S},PN8/Z,\[X0,X1,LSL#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z28\.s-z31\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z3\.s},pn15/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z3\.s},pn8/z,\[x30,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z3\.s},pn8/z,\[sp,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z3\.s},pn8/z,\[x0,x30,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s-z3\.s},pn8/z,\[x0,xzr,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z8\.s-z11\.s},pn11/z,\[x27,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z8\.s},pn8/z,\[x0,x1,lsl 2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z8\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {Z0\.S,Z8\.S},PN8/Z,\[X0,X1,LSL#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z1\.s,z9\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z2\.s,z10\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z3\.s,z11\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z4\.s,z12\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z5\.s,z13\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z6\.s,z14\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z7\.s,z15\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z16\.s,z24\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z17\.s,z25\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z18\.s,z26\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z19\.s,z27\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z20\.s,z28\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z21\.s,z29\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z22\.s,z30\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z23\.s,z31\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z8\.s},pn15/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z8\.s},pn8/z,\[x30,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z8\.s},pn8/z,\[sp,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z8\.s},pn8/z,\[x0,x30,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z8\.s},pn8/z,\[x0,xzr,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z5\.s,z13\.s},pn14/z,\[x15,x24,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x0,x1,lsl 2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {Z0\.S,Z4\.S,Z8\.S,Z12\.S},PN8/Z,\[X0,X1,LSL#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z1\.s,z5\.s,z9\.s,z13\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z2\.s,z6\.s,z10\.s,z14\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z3\.s,z7\.s,z11\.s,z15\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z16\.s,z20\.s,z24\.s,z28\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z17\.s,z21\.s,z25\.s,z29\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z18\.s,z22\.s,z26\.s,z30\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z19\.s,z23\.s,z27\.s,z31\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},pn15/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x30,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[sp,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x0,x30,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x0,xzr,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ld1w {z17\.s,z21\.s,z25\.s,z29\.s},pn11/z,\[x4,x6,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z1\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z1\.s},pn8/z,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {Z0\.S-Z1\.S},PN8/Z,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z30\.s-z31\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z1\.s},pn15/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z1\.s},pn8/z,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z1\.s},pn8/z,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z1\.s},pn8/z,\[x0,#-16,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z1\.s},pn8/z,\[x0,#14,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z12\.s-z13\.s},pn13/z,\[x11,#-10,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z3\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z3\.s},pn8/z,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {Z0\.S-Z3\.S},PN8/Z,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z28\.s-z31\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z3\.s},pn15/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z3\.s},pn8/z,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z3\.s},pn8/z,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z3\.s},pn8/z,\[x0,#-32,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z3\.s},pn8/z,\[x0,#28,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z8\.s-z11\.s},pn11/z,\[x17,#20,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z8\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z8\.s},pn8/z,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {Z0\.S,Z8\.S},PN8/Z,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z1\.s,z9\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z2\.s,z10\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z3\.s,z11\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z4\.s,z12\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z5\.s,z13\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z6\.s,z14\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z7\.s,z15\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z16\.s,z24\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z17\.s,z25\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z18\.s,z26\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z19\.s,z27\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z20\.s,z28\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z21\.s,z29\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z22\.s,z30\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z23\.s,z31\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z8\.s},pn15/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z8\.s},pn8/z,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z8\.s},pn8/z,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z8\.s},pn8/z,\[x0,#-16,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z8\.s},pn8/z,\[x0,#14,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z3\.s,z11\.s},pn10/z,\[x22,#6,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {Z0\.S,Z4\.S,Z8\.S,Z12\.S},PN8/Z,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z1\.s,z5\.s,z9\.s,z13\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z2\.s,z6\.s,z10\.s,z14\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z3\.s,z7\.s,z11\.s,z15\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z16\.s,z20\.s,z24\.s,z28\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z17\.s,z21\.s,z25\.s,z29\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z18\.s,z22\.s,z26\.s,z30\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z19\.s,z23\.s,z27\.s,z31\.s},pn8/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn15/z,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x0,#-32,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x0,#28,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z2\.s,z6\.s,z10\.s,z14\.s},pn14/z,\[x29,#8,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z1\.s},pn8/z,\[x0,x1,lsl 2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z1\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {Z0\.S-Z1\.S},PN8/Z,\[X0,X1,LSL#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z30\.s-z31\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z1\.s},pn15/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z1\.s},pn8/z,\[x30,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z1\.s},pn8/z,\[sp,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z1\.s},pn8/z,\[x0,x30,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z1\.s},pn8/z,\[x0,xzr,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z14\.s-z15\.s},pn9/z,\[x26,x3,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z3\.s},pn8/z,\[x0,x1,lsl 2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z3\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {Z0\.S-Z3\.S},PN8/Z,\[X0,X1,LSL#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z28\.s-z31\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z3\.s},pn15/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z3\.s},pn8/z,\[x30,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z3\.s},pn8/z,\[sp,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z3\.s},pn8/z,\[x0,x30,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s-z3\.s},pn8/z,\[x0,xzr,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z8\.s-z11\.s},pn11/z,\[x27,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z8\.s},pn8/z,\[x0,x1,lsl 2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z8\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {Z0\.S,Z8\.S},PN8/Z,\[X0,X1,LSL#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z1\.s,z9\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z2\.s,z10\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z3\.s,z11\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z4\.s,z12\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z5\.s,z13\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z6\.s,z14\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z7\.s,z15\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z16\.s,z24\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z17\.s,z25\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z18\.s,z26\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z19\.s,z27\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z20\.s,z28\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z21\.s,z29\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z22\.s,z30\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z23\.s,z31\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z8\.s},pn15/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z8\.s},pn8/z,\[x30,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z8\.s},pn8/z,\[sp,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z8\.s},pn8/z,\[x0,x30,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z8\.s},pn8/z,\[x0,xzr,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z5\.s,z13\.s},pn14/z,\[x15,x24,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x0,x1,lsl 2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {Z0\.S,Z4\.S,Z8\.S,Z12\.S},PN8/Z,\[X0,X1,LSL#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z1\.s,z5\.s,z9\.s,z13\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z2\.s,z6\.s,z10\.s,z14\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z3\.s,z7\.s,z11\.s,z15\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z16\.s,z20\.s,z24\.s,z28\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z17\.s,z21\.s,z25\.s,z29\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z18\.s,z22\.s,z26\.s,z30\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z19\.s,z23\.s,z27\.s,z31\.s},pn8/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn15/z,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x30,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[sp,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x0,x30,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8/z,\[x0,xzr,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z17\.s,z21\.s,z25\.s,z29\.s},pn11/z,\[x4,x6,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z1\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z1\.s},pn8,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {Z0\.S-Z1\.S},PN8,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z30\.s-z31\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z1\.s},pn15,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z1\.s},pn8,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z1\.s},pn8,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z1\.s},pn8,\[x0,#-16,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z1\.s},pn8,\[x0,#14,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z12\.s-z13\.s},pn13,\[x11,#-10,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z3\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z3\.s},pn8,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {Z0\.S-Z3\.S},PN8,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z28\.s-z31\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z3\.s},pn15,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z3\.s},pn8,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z3\.s},pn8,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z3\.s},pn8,\[x0,#-32,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z3\.s},pn8,\[x0,#28,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z8\.s-z11\.s},pn11,\[x17,#20,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z8\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z8\.s},pn8,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {Z0\.S,Z8\.S},PN8,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z1\.s,z9\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z2\.s,z10\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z3\.s,z11\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z4\.s,z12\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z5\.s,z13\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z6\.s,z14\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z7\.s,z15\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z16\.s,z24\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z17\.s,z25\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z18\.s,z26\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z19\.s,z27\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z20\.s,z28\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z21\.s,z29\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z22\.s,z30\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z23\.s,z31\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z8\.s},pn15,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z8\.s},pn8,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z8\.s},pn8,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z8\.s},pn8,\[x0,#-16,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z8\.s},pn8,\[x0,#14,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z3\.s,z11\.s},pn10,\[x22,#6,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {Z0\.S,Z4\.S,Z8\.S,Z12\.S},PN8,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z1\.s,z5\.s,z9\.s,z13\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z2\.s,z6\.s,z10\.s,z14\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z3\.s,z7\.s,z11\.s,z15\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z16\.s,z20\.s,z24\.s,z28\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z17\.s,z21\.s,z25\.s,z29\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z18\.s,z22\.s,z26\.s,z30\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z19\.s,z23\.s,z27\.s,z31\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z4\.s,z8\.s,z12\.s},pn15,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x0,#-32,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x0,#28,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z2\.s,z6\.s,z10\.s,z14\.s},pn14,\[x29,#8,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z1\.s},pn8,\[x0,x1,lsl 2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z1\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {Z0\.S-Z1\.S},PN8,\[X0,X1,LSL#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z30\.s-z31\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z1\.s},pn15,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z1\.s},pn8,\[x30,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z1\.s},pn8,\[sp,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z1\.s},pn8,\[x0,x30,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z1\.s},pn8,\[x0,xzr,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z14\.s-z15\.s},pn9,\[x26,x3,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z3\.s},pn8,\[x0,x1,lsl 2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z3\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {Z0\.S-Z3\.S},PN8,\[X0,X1,LSL#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z28\.s-z31\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z3\.s},pn15,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z3\.s},pn8,\[x30,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z3\.s},pn8,\[sp,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z3\.s},pn8,\[x0,x30,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s-z3\.s},pn8,\[x0,xzr,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z8\.s-z11\.s},pn11,\[x27,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z8\.s},pn8,\[x0,x1,lsl 2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z8\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {Z0\.S,Z8\.S},PN8,\[X0,X1,LSL#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z1\.s,z9\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z2\.s,z10\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z3\.s,z11\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z4\.s,z12\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z5\.s,z13\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z6\.s,z14\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z7\.s,z15\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z16\.s,z24\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z17\.s,z25\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z18\.s,z26\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z19\.s,z27\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z20\.s,z28\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z21\.s,z29\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z22\.s,z30\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z23\.s,z31\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z8\.s},pn15,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z8\.s},pn8,\[x30,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z8\.s},pn8,\[sp,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z8\.s},pn8,\[x0,x30,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z8\.s},pn8,\[x0,xzr,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z5\.s,z13\.s},pn14,\[x15,x24,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x0,x1,lsl 2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {Z0\.S,Z4\.S,Z8\.S,Z12\.S},PN8,\[X0,X1,LSL#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z1\.s,z5\.s,z9\.s,z13\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z2\.s,z6\.s,z10\.s,z14\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z3\.s,z7\.s,z11\.s,z15\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z16\.s,z20\.s,z24\.s,z28\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z17\.s,z21\.s,z25\.s,z29\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z18\.s,z22\.s,z26\.s,z30\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z19\.s,z23\.s,z27\.s,z31\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z4\.s,z8\.s,z12\.s},pn15,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x30,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[sp,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x0,x30,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x0,xzr,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `st1w {z17\.s,z21\.s,z25\.s,z29\.s},pn11,\[x4,x6,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z1\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z1\.s},pn8,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {Z0\.S-Z1\.S},PN8,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z30\.s-z31\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z1\.s},pn15,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z1\.s},pn8,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z1\.s},pn8,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z1\.s},pn8,\[x0,#-16,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z1\.s},pn8,\[x0,#14,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z12\.s-z13\.s},pn13,\[x11,#-10,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z3\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z3\.s},pn8,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {Z0\.S-Z3\.S},PN8,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z28\.s-z31\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z3\.s},pn15,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z3\.s},pn8,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z3\.s},pn8,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z3\.s},pn8,\[x0,#-32,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z3\.s},pn8,\[x0,#28,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z8\.s-z11\.s},pn11,\[x17,#20,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z8\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z8\.s},pn8,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {Z0\.S,Z8\.S},PN8,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z1\.s,z9\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z2\.s,z10\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z3\.s,z11\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z4\.s,z12\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z5\.s,z13\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z6\.s,z14\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z7\.s,z15\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z16\.s,z24\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z17\.s,z25\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z18\.s,z26\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z19\.s,z27\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z20\.s,z28\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z21\.s,z29\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z22\.s,z30\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z23\.s,z31\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z8\.s},pn15,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z8\.s},pn8,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z8\.s},pn8,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z8\.s},pn8,\[x0,#-16,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z8\.s},pn8,\[x0,#14,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z3\.s,z11\.s},pn10,\[x22,#6,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x0,#0,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {Z0\.S,Z4\.S,Z8\.S,Z12\.S},PN8,\[X0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z1\.s,z5\.s,z9\.s,z13\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z2\.s,z6\.s,z10\.s,z14\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z3\.s,z7\.s,z11\.s,z15\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z16\.s,z20\.s,z24\.s,z28\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z17\.s,z21\.s,z25\.s,z29\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z18\.s,z22\.s,z26\.s,z30\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z19\.s,z23\.s,z27\.s,z31\.s},pn8,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn15,\[x0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x30\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[sp\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x0,#-32,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x0,#28,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z2\.s,z6\.s,z10\.s,z14\.s},pn14,\[x29,#8,mul vl\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z1\.s},pn8,\[x0,x1,lsl 2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z1\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {Z0\.S-Z1\.S},PN8,\[X0,X1,LSL#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z30\.s-z31\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z1\.s},pn15,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z1\.s},pn8,\[x30,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z1\.s},pn8,\[sp,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z1\.s},pn8,\[x0,x30,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z1\.s},pn8,\[x0,xzr,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z14\.s-z15\.s},pn9,\[x26,x3,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z3\.s},pn8,\[x0,x1,lsl 2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z3\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {Z0\.S-Z3\.S},PN8,\[X0,X1,LSL#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z28\.s-z31\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z3\.s},pn15,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z3\.s},pn8,\[x30,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z3\.s},pn8,\[sp,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z3\.s},pn8,\[x0,x30,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s-z3\.s},pn8,\[x0,xzr,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z8\.s-z11\.s},pn11,\[x27,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z8\.s},pn8,\[x0,x1,lsl 2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z8\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {Z0\.S,Z8\.S},PN8,\[X0,X1,LSL#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z1\.s,z9\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z2\.s,z10\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z3\.s,z11\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z4\.s,z12\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z5\.s,z13\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z6\.s,z14\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z7\.s,z15\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z16\.s,z24\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z17\.s,z25\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z18\.s,z26\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z19\.s,z27\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z20\.s,z28\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z21\.s,z29\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z22\.s,z30\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z23\.s,z31\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z8\.s},pn15,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z8\.s},pn8,\[x30,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z8\.s},pn8,\[sp,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z8\.s},pn8,\[x0,x30,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z8\.s},pn8,\[x0,xzr,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z5\.s,z13\.s},pn14,\[x15,x24,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x0,x1,lsl 2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {Z0\.S,Z4\.S,Z8\.S,Z12\.S},PN8,\[X0,X1,LSL#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z1\.s,z5\.s,z9\.s,z13\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z2\.s,z6\.s,z10\.s,z14\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z3\.s,z7\.s,z11\.s,z15\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z16\.s,z20\.s,z24\.s,z28\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z17\.s,z21\.s,z25\.s,z29\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z18\.s,z22\.s,z26\.s,z30\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z19\.s,z23\.s,z27\.s,z31\.s},pn8,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn15,\[x0,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x30,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[sp,x1,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x0,x30,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s,z4\.s,z8\.s,z12\.s},pn8,\[x0,xzr,lsl#2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z17\.s,z21\.s,z25\.s,z29\.s},pn11,\[x4,x6,lsl#2\]'
|
||||
489
gas/testsuite/gas/aarch64/sme2-5.d
Normal file
489
gas/testsuite/gas/aarch64/sme2-5.d
Normal file
@ -0,0 +1,489 @@
|
||||
#as: -march=armv8-a+sme2
|
||||
#objdump: -dr
|
||||
|
||||
[^:]+: file format .*
|
||||
|
||||
|
||||
[^:]+:
|
||||
|
||||
[^:]+:
|
||||
[^:]+: a0404000 ld1w {z0\.s-z1\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a0404000 ld1w {z0\.s-z1\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a0404000 ld1w {z0\.s-z1\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a040401e ld1w {z30\.s-z31\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a0405c00 ld1w {z0\.s-z1\.s}, pn15/z, \[x0\]
|
||||
[^:]+: a04043c0 ld1w {z0\.s-z1\.s}, pn8/z, \[x30\]
|
||||
[^:]+: a04043e0 ld1w {z0\.s-z1\.s}, pn8/z, \[sp\]
|
||||
[^:]+: a0484000 ld1w {z0\.s-z1\.s}, pn8/z, \[x0, #-16, mul vl\]
|
||||
[^:]+: a0474000 ld1w {z0\.s-z1\.s}, pn8/z, \[x0, #14, mul vl\]
|
||||
[^:]+: a04b556c ld1w {z12\.s-z13\.s}, pn13/z, \[x11, #-10, mul vl\]
|
||||
[^:]+: a040c000 ld1w {z0\.s-z3\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a040c000 ld1w {z0\.s-z3\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a040c000 ld1w {z0\.s-z3\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a040c01c ld1w {z28\.s-z31\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a040dc00 ld1w {z0\.s-z3\.s}, pn15/z, \[x0\]
|
||||
[^:]+: a040c3c0 ld1w {z0\.s-z3\.s}, pn8/z, \[x30\]
|
||||
[^:]+: a040c3e0 ld1w {z0\.s-z3\.s}, pn8/z, \[sp\]
|
||||
[^:]+: a048c000 ld1w {z0\.s-z3\.s}, pn8/z, \[x0, #-32, mul vl\]
|
||||
[^:]+: a047c000 ld1w {z0\.s-z3\.s}, pn8/z, \[x0, #28, mul vl\]
|
||||
[^:]+: a045ce28 ld1w {z8\.s-z11\.s}, pn11/z, \[x17, #20, mul vl\]
|
||||
[^:]+: a1404000 ld1w {z0\.s, z8\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a1404000 ld1w {z0\.s, z8\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a1404000 ld1w {z0\.s, z8\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a1404001 ld1w {z1\.s, z9\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a1404002 ld1w {z2\.s, z10\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a1404003 ld1w {z3\.s, z11\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a1404004 ld1w {z4\.s, z12\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a1404005 ld1w {z5\.s, z13\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a1404006 ld1w {z6\.s, z14\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a1404007 ld1w {z7\.s, z15\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a1404010 ld1w {z16\.s, z24\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a1404011 ld1w {z17\.s, z25\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a1404012 ld1w {z18\.s, z26\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a1404013 ld1w {z19\.s, z27\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a1404014 ld1w {z20\.s, z28\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a1404015 ld1w {z21\.s, z29\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a1404016 ld1w {z22\.s, z30\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a1404017 ld1w {z23\.s, z31\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a1405c00 ld1w {z0\.s, z8\.s}, pn15/z, \[x0\]
|
||||
[^:]+: a14043c0 ld1w {z0\.s, z8\.s}, pn8/z, \[x30\]
|
||||
[^:]+: a14043e0 ld1w {z0\.s, z8\.s}, pn8/z, \[sp\]
|
||||
[^:]+: a1484000 ld1w {z0\.s, z8\.s}, pn8/z, \[x0, #-16, mul vl\]
|
||||
[^:]+: a1474000 ld1w {z0\.s, z8\.s}, pn8/z, \[x0, #14, mul vl\]
|
||||
[^:]+: a1434ac3 ld1w {z3\.s, z11\.s}, pn10/z, \[x22, #6, mul vl\]
|
||||
[^:]+: a140c000 ld1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a140c000 ld1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a140c000 ld1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a140c001 ld1w {z1\.s, z5\.s, z9\.s, z13\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a140c002 ld1w {z2\.s, z6\.s, z10\.s, z14\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a140c003 ld1w {z3\.s, z7\.s, z11\.s, z15\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a140c010 ld1w {z16\.s, z20\.s, z24\.s, z28\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a140c011 ld1w {z17\.s, z21\.s, z25\.s, z29\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a140c012 ld1w {z18\.s, z22\.s, z26\.s, z30\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a140c013 ld1w {z19\.s, z23\.s, z27\.s, z31\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a140dc00 ld1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn15/z, \[x0\]
|
||||
[^:]+: a140c3c0 ld1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x30\]
|
||||
[^:]+: a140c3e0 ld1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[sp\]
|
||||
[^:]+: a148c000 ld1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0, #-32, mul vl\]
|
||||
[^:]+: a147c000 ld1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0, #28, mul vl\]
|
||||
[^:]+: a142dba2 ld1w {z2\.s, z6\.s, z10\.s, z14\.s}, pn14/z, \[x29, #8, mul vl\]
|
||||
[^:]+: a0014000 ld1w {z0\.s-z1\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a0014000 ld1w {z0\.s-z1\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a0014000 ld1w {z0\.s-z1\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a001401e ld1w {z30\.s-z31\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a0015c00 ld1w {z0\.s-z1\.s}, pn15/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a00143c0 ld1w {z0\.s-z1\.s}, pn8/z, \[x30, x1, lsl #2\]
|
||||
[^:]+: a00143e0 ld1w {z0\.s-z1\.s}, pn8/z, \[sp, x1, lsl #2\]
|
||||
[^:]+: a01e4000 ld1w {z0\.s-z1\.s}, pn8/z, \[x0, x30, lsl #2\]
|
||||
[^:]+: a01f4000 ld1w {z0\.s-z1\.s}, pn8/z, \[x0, xzr, lsl #2\]
|
||||
[^:]+: a003474e ld1w {z14\.s-z15\.s}, pn9/z, \[x26, x3, lsl #2\]
|
||||
[^:]+: a001c000 ld1w {z0\.s-z3\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a001c000 ld1w {z0\.s-z3\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a001c000 ld1w {z0\.s-z3\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a001c01c ld1w {z28\.s-z31\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a001dc00 ld1w {z0\.s-z3\.s}, pn15/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a001c3c0 ld1w {z0\.s-z3\.s}, pn8/z, \[x30, x1, lsl #2\]
|
||||
[^:]+: a001c3e0 ld1w {z0\.s-z3\.s}, pn8/z, \[sp, x1, lsl #2\]
|
||||
[^:]+: a01ec000 ld1w {z0\.s-z3\.s}, pn8/z, \[x0, x30, lsl #2\]
|
||||
[^:]+: a01fc000 ld1w {z0\.s-z3\.s}, pn8/z, \[x0, xzr, lsl #2\]
|
||||
[^:]+: a001cf68 ld1w {z8\.s-z11\.s}, pn11/z, \[x27, x1, lsl #2\]
|
||||
[^:]+: a1014000 ld1w {z0\.s, z8\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1014000 ld1w {z0\.s, z8\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1014000 ld1w {z0\.s, z8\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1014001 ld1w {z1\.s, z9\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1014002 ld1w {z2\.s, z10\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1014003 ld1w {z3\.s, z11\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1014004 ld1w {z4\.s, z12\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1014005 ld1w {z5\.s, z13\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1014006 ld1w {z6\.s, z14\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1014007 ld1w {z7\.s, z15\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1014010 ld1w {z16\.s, z24\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1014011 ld1w {z17\.s, z25\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1014012 ld1w {z18\.s, z26\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1014013 ld1w {z19\.s, z27\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1014014 ld1w {z20\.s, z28\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1014015 ld1w {z21\.s, z29\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1014016 ld1w {z22\.s, z30\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1014017 ld1w {z23\.s, z31\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1015c00 ld1w {z0\.s, z8\.s}, pn15/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a10143c0 ld1w {z0\.s, z8\.s}, pn8/z, \[x30, x1, lsl #2\]
|
||||
[^:]+: a10143e0 ld1w {z0\.s, z8\.s}, pn8/z, \[sp, x1, lsl #2\]
|
||||
[^:]+: a11e4000 ld1w {z0\.s, z8\.s}, pn8/z, \[x0, x30, lsl #2\]
|
||||
[^:]+: a11f4000 ld1w {z0\.s, z8\.s}, pn8/z, \[x0, xzr, lsl #2\]
|
||||
[^:]+: a11859e5 ld1w {z5\.s, z13\.s}, pn14/z, \[x15, x24, lsl #2\]
|
||||
[^:]+: a101c000 ld1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a101c000 ld1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a101c000 ld1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a101c001 ld1w {z1\.s, z5\.s, z9\.s, z13\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a101c002 ld1w {z2\.s, z6\.s, z10\.s, z14\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a101c003 ld1w {z3\.s, z7\.s, z11\.s, z15\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a101c010 ld1w {z16\.s, z20\.s, z24\.s, z28\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a101c011 ld1w {z17\.s, z21\.s, z25\.s, z29\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a101c012 ld1w {z18\.s, z22\.s, z26\.s, z30\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a101c013 ld1w {z19\.s, z23\.s, z27\.s, z31\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a101dc00 ld1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn15/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a101c3c0 ld1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x30, x1, lsl #2\]
|
||||
[^:]+: a101c3e0 ld1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[sp, x1, lsl #2\]
|
||||
[^:]+: a11ec000 ld1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0, x30, lsl #2\]
|
||||
[^:]+: a11fc000 ld1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0, xzr, lsl #2\]
|
||||
[^:]+: a106cc91 ld1w {z17\.s, z21\.s, z25\.s, z29\.s}, pn11/z, \[x4, x6, lsl #2\]
|
||||
[^:]+: a0404001 ldnt1w {z0\.s-z1\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a0404001 ldnt1w {z0\.s-z1\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a0404001 ldnt1w {z0\.s-z1\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a040401f ldnt1w {z30\.s-z31\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a0405c01 ldnt1w {z0\.s-z1\.s}, pn15/z, \[x0\]
|
||||
[^:]+: a04043c1 ldnt1w {z0\.s-z1\.s}, pn8/z, \[x30\]
|
||||
[^:]+: a04043e1 ldnt1w {z0\.s-z1\.s}, pn8/z, \[sp\]
|
||||
[^:]+: a0484001 ldnt1w {z0\.s-z1\.s}, pn8/z, \[x0, #-16, mul vl\]
|
||||
[^:]+: a0474001 ldnt1w {z0\.s-z1\.s}, pn8/z, \[x0, #14, mul vl\]
|
||||
[^:]+: a04b556d ldnt1w {z12\.s-z13\.s}, pn13/z, \[x11, #-10, mul vl\]
|
||||
[^:]+: a040c001 ldnt1w {z0\.s-z3\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a040c001 ldnt1w {z0\.s-z3\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a040c001 ldnt1w {z0\.s-z3\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a040c01d ldnt1w {z28\.s-z31\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a040dc01 ldnt1w {z0\.s-z3\.s}, pn15/z, \[x0\]
|
||||
[^:]+: a040c3c1 ldnt1w {z0\.s-z3\.s}, pn8/z, \[x30\]
|
||||
[^:]+: a040c3e1 ldnt1w {z0\.s-z3\.s}, pn8/z, \[sp\]
|
||||
[^:]+: a048c001 ldnt1w {z0\.s-z3\.s}, pn8/z, \[x0, #-32, mul vl\]
|
||||
[^:]+: a047c001 ldnt1w {z0\.s-z3\.s}, pn8/z, \[x0, #28, mul vl\]
|
||||
[^:]+: a045ce29 ldnt1w {z8\.s-z11\.s}, pn11/z, \[x17, #20, mul vl\]
|
||||
[^:]+: a1404008 ldnt1w {z0\.s, z8\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a1404008 ldnt1w {z0\.s, z8\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a1404008 ldnt1w {z0\.s, z8\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a1404009 ldnt1w {z1\.s, z9\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a140400a ldnt1w {z2\.s, z10\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a140400b ldnt1w {z3\.s, z11\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a140400c ldnt1w {z4\.s, z12\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a140400d ldnt1w {z5\.s, z13\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a140400e ldnt1w {z6\.s, z14\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a140400f ldnt1w {z7\.s, z15\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a1404018 ldnt1w {z16\.s, z24\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a1404019 ldnt1w {z17\.s, z25\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a140401a ldnt1w {z18\.s, z26\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a140401b ldnt1w {z19\.s, z27\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a140401c ldnt1w {z20\.s, z28\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a140401d ldnt1w {z21\.s, z29\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a140401e ldnt1w {z22\.s, z30\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a140401f ldnt1w {z23\.s, z31\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a1405c08 ldnt1w {z0\.s, z8\.s}, pn15/z, \[x0\]
|
||||
[^:]+: a14043c8 ldnt1w {z0\.s, z8\.s}, pn8/z, \[x30\]
|
||||
[^:]+: a14043e8 ldnt1w {z0\.s, z8\.s}, pn8/z, \[sp\]
|
||||
[^:]+: a1484008 ldnt1w {z0\.s, z8\.s}, pn8/z, \[x0, #-16, mul vl\]
|
||||
[^:]+: a1474008 ldnt1w {z0\.s, z8\.s}, pn8/z, \[x0, #14, mul vl\]
|
||||
[^:]+: a1434acb ldnt1w {z3\.s, z11\.s}, pn10/z, \[x22, #6, mul vl\]
|
||||
[^:]+: a140c008 ldnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a140c008 ldnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a140c008 ldnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a140c009 ldnt1w {z1\.s, z5\.s, z9\.s, z13\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a140c00a ldnt1w {z2\.s, z6\.s, z10\.s, z14\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a140c00b ldnt1w {z3\.s, z7\.s, z11\.s, z15\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a140c018 ldnt1w {z16\.s, z20\.s, z24\.s, z28\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a140c019 ldnt1w {z17\.s, z21\.s, z25\.s, z29\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a140c01a ldnt1w {z18\.s, z22\.s, z26\.s, z30\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a140c01b ldnt1w {z19\.s, z23\.s, z27\.s, z31\.s}, pn8/z, \[x0\]
|
||||
[^:]+: a140dc08 ldnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn15/z, \[x0\]
|
||||
[^:]+: a140c3c8 ldnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x30\]
|
||||
[^:]+: a140c3e8 ldnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[sp\]
|
||||
[^:]+: a148c008 ldnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0, #-32, mul vl\]
|
||||
[^:]+: a147c008 ldnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0, #28, mul vl\]
|
||||
[^:]+: a142dbaa ldnt1w {z2\.s, z6\.s, z10\.s, z14\.s}, pn14/z, \[x29, #8, mul vl\]
|
||||
[^:]+: a0014001 ldnt1w {z0\.s-z1\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a0014001 ldnt1w {z0\.s-z1\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a0014001 ldnt1w {z0\.s-z1\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a001401f ldnt1w {z30\.s-z31\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a0015c01 ldnt1w {z0\.s-z1\.s}, pn15/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a00143c1 ldnt1w {z0\.s-z1\.s}, pn8/z, \[x30, x1, lsl #2\]
|
||||
[^:]+: a00143e1 ldnt1w {z0\.s-z1\.s}, pn8/z, \[sp, x1, lsl #2\]
|
||||
[^:]+: a01e4001 ldnt1w {z0\.s-z1\.s}, pn8/z, \[x0, x30, lsl #2\]
|
||||
[^:]+: a01f4001 ldnt1w {z0\.s-z1\.s}, pn8/z, \[x0, xzr, lsl #2\]
|
||||
[^:]+: a003474f ldnt1w {z14\.s-z15\.s}, pn9/z, \[x26, x3, lsl #2\]
|
||||
[^:]+: a001c001 ldnt1w {z0\.s-z3\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a001c001 ldnt1w {z0\.s-z3\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a001c001 ldnt1w {z0\.s-z3\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a001c01d ldnt1w {z28\.s-z31\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a001dc01 ldnt1w {z0\.s-z3\.s}, pn15/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a001c3c1 ldnt1w {z0\.s-z3\.s}, pn8/z, \[x30, x1, lsl #2\]
|
||||
[^:]+: a001c3e1 ldnt1w {z0\.s-z3\.s}, pn8/z, \[sp, x1, lsl #2\]
|
||||
[^:]+: a01ec001 ldnt1w {z0\.s-z3\.s}, pn8/z, \[x0, x30, lsl #2\]
|
||||
[^:]+: a01fc001 ldnt1w {z0\.s-z3\.s}, pn8/z, \[x0, xzr, lsl #2\]
|
||||
[^:]+: a001cf69 ldnt1w {z8\.s-z11\.s}, pn11/z, \[x27, x1, lsl #2\]
|
||||
[^:]+: a1014008 ldnt1w {z0\.s, z8\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1014008 ldnt1w {z0\.s, z8\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1014008 ldnt1w {z0\.s, z8\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1014009 ldnt1w {z1\.s, z9\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a101400a ldnt1w {z2\.s, z10\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a101400b ldnt1w {z3\.s, z11\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a101400c ldnt1w {z4\.s, z12\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a101400d ldnt1w {z5\.s, z13\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a101400e ldnt1w {z6\.s, z14\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a101400f ldnt1w {z7\.s, z15\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1014018 ldnt1w {z16\.s, z24\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1014019 ldnt1w {z17\.s, z25\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a101401a ldnt1w {z18\.s, z26\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a101401b ldnt1w {z19\.s, z27\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a101401c ldnt1w {z20\.s, z28\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a101401d ldnt1w {z21\.s, z29\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a101401e ldnt1w {z22\.s, z30\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a101401f ldnt1w {z23\.s, z31\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1015c08 ldnt1w {z0\.s, z8\.s}, pn15/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a10143c8 ldnt1w {z0\.s, z8\.s}, pn8/z, \[x30, x1, lsl #2\]
|
||||
[^:]+: a10143e8 ldnt1w {z0\.s, z8\.s}, pn8/z, \[sp, x1, lsl #2\]
|
||||
[^:]+: a11e4008 ldnt1w {z0\.s, z8\.s}, pn8/z, \[x0, x30, lsl #2\]
|
||||
[^:]+: a11f4008 ldnt1w {z0\.s, z8\.s}, pn8/z, \[x0, xzr, lsl #2\]
|
||||
[^:]+: a11859ed ldnt1w {z5\.s, z13\.s}, pn14/z, \[x15, x24, lsl #2\]
|
||||
[^:]+: a101c008 ldnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a101c008 ldnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a101c008 ldnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a101c009 ldnt1w {z1\.s, z5\.s, z9\.s, z13\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a101c00a ldnt1w {z2\.s, z6\.s, z10\.s, z14\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a101c00b ldnt1w {z3\.s, z7\.s, z11\.s, z15\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a101c018 ldnt1w {z16\.s, z20\.s, z24\.s, z28\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a101c019 ldnt1w {z17\.s, z21\.s, z25\.s, z29\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a101c01a ldnt1w {z18\.s, z22\.s, z26\.s, z30\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a101c01b ldnt1w {z19\.s, z23\.s, z27\.s, z31\.s}, pn8/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a101dc08 ldnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn15/z, \[x0, x1, lsl #2\]
|
||||
[^:]+: a101c3c8 ldnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x30, x1, lsl #2\]
|
||||
[^:]+: a101c3e8 ldnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[sp, x1, lsl #2\]
|
||||
[^:]+: a11ec008 ldnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0, x30, lsl #2\]
|
||||
[^:]+: a11fc008 ldnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8/z, \[x0, xzr, lsl #2\]
|
||||
[^:]+: a106cc99 ldnt1w {z17\.s, z21\.s, z25\.s, z29\.s}, pn11/z, \[x4, x6, lsl #2\]
|
||||
[^:]+: a0604000 st1w {z0\.s-z1\.s}, pn8, \[x0\]
|
||||
[^:]+: a0604000 st1w {z0\.s-z1\.s}, pn8, \[x0\]
|
||||
[^:]+: a0604000 st1w {z0\.s-z1\.s}, pn8, \[x0\]
|
||||
[^:]+: a060401e st1w {z30\.s-z31\.s}, pn8, \[x0\]
|
||||
[^:]+: a0605c00 st1w {z0\.s-z1\.s}, pn15, \[x0\]
|
||||
[^:]+: a06043c0 st1w {z0\.s-z1\.s}, pn8, \[x30\]
|
||||
[^:]+: a06043e0 st1w {z0\.s-z1\.s}, pn8, \[sp\]
|
||||
[^:]+: a0684000 st1w {z0\.s-z1\.s}, pn8, \[x0, #-16, mul vl\]
|
||||
[^:]+: a0674000 st1w {z0\.s-z1\.s}, pn8, \[x0, #14, mul vl\]
|
||||
[^:]+: a06b556c st1w {z12\.s-z13\.s}, pn13, \[x11, #-10, mul vl\]
|
||||
[^:]+: a060c000 st1w {z0\.s-z3\.s}, pn8, \[x0\]
|
||||
[^:]+: a060c000 st1w {z0\.s-z3\.s}, pn8, \[x0\]
|
||||
[^:]+: a060c000 st1w {z0\.s-z3\.s}, pn8, \[x0\]
|
||||
[^:]+: a060c01c st1w {z28\.s-z31\.s}, pn8, \[x0\]
|
||||
[^:]+: a060dc00 st1w {z0\.s-z3\.s}, pn15, \[x0\]
|
||||
[^:]+: a060c3c0 st1w {z0\.s-z3\.s}, pn8, \[x30\]
|
||||
[^:]+: a060c3e0 st1w {z0\.s-z3\.s}, pn8, \[sp\]
|
||||
[^:]+: a068c000 st1w {z0\.s-z3\.s}, pn8, \[x0, #-32, mul vl\]
|
||||
[^:]+: a067c000 st1w {z0\.s-z3\.s}, pn8, \[x0, #28, mul vl\]
|
||||
[^:]+: a065ce28 st1w {z8\.s-z11\.s}, pn11, \[x17, #20, mul vl\]
|
||||
[^:]+: a1604000 st1w {z0\.s, z8\.s}, pn8, \[x0\]
|
||||
[^:]+: a1604000 st1w {z0\.s, z8\.s}, pn8, \[x0\]
|
||||
[^:]+: a1604000 st1w {z0\.s, z8\.s}, pn8, \[x0\]
|
||||
[^:]+: a1604001 st1w {z1\.s, z9\.s}, pn8, \[x0\]
|
||||
[^:]+: a1604002 st1w {z2\.s, z10\.s}, pn8, \[x0\]
|
||||
[^:]+: a1604003 st1w {z3\.s, z11\.s}, pn8, \[x0\]
|
||||
[^:]+: a1604004 st1w {z4\.s, z12\.s}, pn8, \[x0\]
|
||||
[^:]+: a1604005 st1w {z5\.s, z13\.s}, pn8, \[x0\]
|
||||
[^:]+: a1604006 st1w {z6\.s, z14\.s}, pn8, \[x0\]
|
||||
[^:]+: a1604007 st1w {z7\.s, z15\.s}, pn8, \[x0\]
|
||||
[^:]+: a1604010 st1w {z16\.s, z24\.s}, pn8, \[x0\]
|
||||
[^:]+: a1604011 st1w {z17\.s, z25\.s}, pn8, \[x0\]
|
||||
[^:]+: a1604012 st1w {z18\.s, z26\.s}, pn8, \[x0\]
|
||||
[^:]+: a1604013 st1w {z19\.s, z27\.s}, pn8, \[x0\]
|
||||
[^:]+: a1604014 st1w {z20\.s, z28\.s}, pn8, \[x0\]
|
||||
[^:]+: a1604015 st1w {z21\.s, z29\.s}, pn8, \[x0\]
|
||||
[^:]+: a1604016 st1w {z22\.s, z30\.s}, pn8, \[x0\]
|
||||
[^:]+: a1604017 st1w {z23\.s, z31\.s}, pn8, \[x0\]
|
||||
[^:]+: a1605c00 st1w {z0\.s, z8\.s}, pn15, \[x0\]
|
||||
[^:]+: a16043c0 st1w {z0\.s, z8\.s}, pn8, \[x30\]
|
||||
[^:]+: a16043e0 st1w {z0\.s, z8\.s}, pn8, \[sp\]
|
||||
[^:]+: a1684000 st1w {z0\.s, z8\.s}, pn8, \[x0, #-16, mul vl\]
|
||||
[^:]+: a1674000 st1w {z0\.s, z8\.s}, pn8, \[x0, #14, mul vl\]
|
||||
[^:]+: a1634ac3 st1w {z3\.s, z11\.s}, pn10, \[x22, #6, mul vl\]
|
||||
[^:]+: a160c000 st1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0\]
|
||||
[^:]+: a160c000 st1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0\]
|
||||
[^:]+: a160c000 st1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0\]
|
||||
[^:]+: a160c001 st1w {z1\.s, z5\.s, z9\.s, z13\.s}, pn8, \[x0\]
|
||||
[^:]+: a160c002 st1w {z2\.s, z6\.s, z10\.s, z14\.s}, pn8, \[x0\]
|
||||
[^:]+: a160c003 st1w {z3\.s, z7\.s, z11\.s, z15\.s}, pn8, \[x0\]
|
||||
[^:]+: a160c010 st1w {z16\.s, z20\.s, z24\.s, z28\.s}, pn8, \[x0\]
|
||||
[^:]+: a160c011 st1w {z17\.s, z21\.s, z25\.s, z29\.s}, pn8, \[x0\]
|
||||
[^:]+: a160c012 st1w {z18\.s, z22\.s, z26\.s, z30\.s}, pn8, \[x0\]
|
||||
[^:]+: a160c013 st1w {z19\.s, z23\.s, z27\.s, z31\.s}, pn8, \[x0\]
|
||||
[^:]+: a160dc00 st1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn15, \[x0\]
|
||||
[^:]+: a160c3c0 st1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x30\]
|
||||
[^:]+: a160c3e0 st1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[sp\]
|
||||
[^:]+: a168c000 st1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0, #-32, mul vl\]
|
||||
[^:]+: a167c000 st1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0, #28, mul vl\]
|
||||
[^:]+: a162dba2 st1w {z2\.s, z6\.s, z10\.s, z14\.s}, pn14, \[x29, #8, mul vl\]
|
||||
[^:]+: a0214000 st1w {z0\.s-z1\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a0214000 st1w {z0\.s-z1\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a0214000 st1w {z0\.s-z1\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a021401e st1w {z30\.s-z31\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a0215c00 st1w {z0\.s-z1\.s}, pn15, \[x0, x1, lsl #2\]
|
||||
[^:]+: a02143c0 st1w {z0\.s-z1\.s}, pn8, \[x30, x1, lsl #2\]
|
||||
[^:]+: a02143e0 st1w {z0\.s-z1\.s}, pn8, \[sp, x1, lsl #2\]
|
||||
[^:]+: a03e4000 st1w {z0\.s-z1\.s}, pn8, \[x0, x30, lsl #2\]
|
||||
[^:]+: a03f4000 st1w {z0\.s-z1\.s}, pn8, \[x0, xzr, lsl #2\]
|
||||
[^:]+: a023474e st1w {z14\.s-z15\.s}, pn9, \[x26, x3, lsl #2\]
|
||||
[^:]+: a021c000 st1w {z0\.s-z3\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a021c000 st1w {z0\.s-z3\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a021c000 st1w {z0\.s-z3\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a021c01c st1w {z28\.s-z31\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a021dc00 st1w {z0\.s-z3\.s}, pn15, \[x0, x1, lsl #2\]
|
||||
[^:]+: a021c3c0 st1w {z0\.s-z3\.s}, pn8, \[x30, x1, lsl #2\]
|
||||
[^:]+: a021c3e0 st1w {z0\.s-z3\.s}, pn8, \[sp, x1, lsl #2\]
|
||||
[^:]+: a03ec000 st1w {z0\.s-z3\.s}, pn8, \[x0, x30, lsl #2\]
|
||||
[^:]+: a03fc000 st1w {z0\.s-z3\.s}, pn8, \[x0, xzr, lsl #2\]
|
||||
[^:]+: a021cf68 st1w {z8\.s-z11\.s}, pn11, \[x27, x1, lsl #2\]
|
||||
[^:]+: a1214000 st1w {z0\.s, z8\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1214000 st1w {z0\.s, z8\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1214000 st1w {z0\.s, z8\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1214001 st1w {z1\.s, z9\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1214002 st1w {z2\.s, z10\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1214003 st1w {z3\.s, z11\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1214004 st1w {z4\.s, z12\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1214005 st1w {z5\.s, z13\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1214006 st1w {z6\.s, z14\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1214007 st1w {z7\.s, z15\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1214010 st1w {z16\.s, z24\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1214011 st1w {z17\.s, z25\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1214012 st1w {z18\.s, z26\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1214013 st1w {z19\.s, z27\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1214014 st1w {z20\.s, z28\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1214015 st1w {z21\.s, z29\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1214016 st1w {z22\.s, z30\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1214017 st1w {z23\.s, z31\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1215c00 st1w {z0\.s, z8\.s}, pn15, \[x0, x1, lsl #2\]
|
||||
[^:]+: a12143c0 st1w {z0\.s, z8\.s}, pn8, \[x30, x1, lsl #2\]
|
||||
[^:]+: a12143e0 st1w {z0\.s, z8\.s}, pn8, \[sp, x1, lsl #2\]
|
||||
[^:]+: a13e4000 st1w {z0\.s, z8\.s}, pn8, \[x0, x30, lsl #2\]
|
||||
[^:]+: a13f4000 st1w {z0\.s, z8\.s}, pn8, \[x0, xzr, lsl #2\]
|
||||
[^:]+: a13859e5 st1w {z5\.s, z13\.s}, pn14, \[x15, x24, lsl #2\]
|
||||
[^:]+: a121c000 st1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a121c000 st1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a121c000 st1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a121c001 st1w {z1\.s, z5\.s, z9\.s, z13\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a121c002 st1w {z2\.s, z6\.s, z10\.s, z14\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a121c003 st1w {z3\.s, z7\.s, z11\.s, z15\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a121c010 st1w {z16\.s, z20\.s, z24\.s, z28\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a121c011 st1w {z17\.s, z21\.s, z25\.s, z29\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a121c012 st1w {z18\.s, z22\.s, z26\.s, z30\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a121c013 st1w {z19\.s, z23\.s, z27\.s, z31\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a121dc00 st1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn15, \[x0, x1, lsl #2\]
|
||||
[^:]+: a121c3c0 st1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x30, x1, lsl #2\]
|
||||
[^:]+: a121c3e0 st1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[sp, x1, lsl #2\]
|
||||
[^:]+: a13ec000 st1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0, x30, lsl #2\]
|
||||
[^:]+: a13fc000 st1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0, xzr, lsl #2\]
|
||||
[^:]+: a126cc91 st1w {z17\.s, z21\.s, z25\.s, z29\.s}, pn11, \[x4, x6, lsl #2\]
|
||||
[^:]+: a0604001 stnt1w {z0\.s-z1\.s}, pn8, \[x0\]
|
||||
[^:]+: a0604001 stnt1w {z0\.s-z1\.s}, pn8, \[x0\]
|
||||
[^:]+: a0604001 stnt1w {z0\.s-z1\.s}, pn8, \[x0\]
|
||||
[^:]+: a060401f stnt1w {z30\.s-z31\.s}, pn8, \[x0\]
|
||||
[^:]+: a0605c01 stnt1w {z0\.s-z1\.s}, pn15, \[x0\]
|
||||
[^:]+: a06043c1 stnt1w {z0\.s-z1\.s}, pn8, \[x30\]
|
||||
[^:]+: a06043e1 stnt1w {z0\.s-z1\.s}, pn8, \[sp\]
|
||||
[^:]+: a0684001 stnt1w {z0\.s-z1\.s}, pn8, \[x0, #-16, mul vl\]
|
||||
[^:]+: a0674001 stnt1w {z0\.s-z1\.s}, pn8, \[x0, #14, mul vl\]
|
||||
[^:]+: a06b556d stnt1w {z12\.s-z13\.s}, pn13, \[x11, #-10, mul vl\]
|
||||
[^:]+: a060c001 stnt1w {z0\.s-z3\.s}, pn8, \[x0\]
|
||||
[^:]+: a060c001 stnt1w {z0\.s-z3\.s}, pn8, \[x0\]
|
||||
[^:]+: a060c001 stnt1w {z0\.s-z3\.s}, pn8, \[x0\]
|
||||
[^:]+: a060c01d stnt1w {z28\.s-z31\.s}, pn8, \[x0\]
|
||||
[^:]+: a060dc01 stnt1w {z0\.s-z3\.s}, pn15, \[x0\]
|
||||
[^:]+: a060c3c1 stnt1w {z0\.s-z3\.s}, pn8, \[x30\]
|
||||
[^:]+: a060c3e1 stnt1w {z0\.s-z3\.s}, pn8, \[sp\]
|
||||
[^:]+: a068c001 stnt1w {z0\.s-z3\.s}, pn8, \[x0, #-32, mul vl\]
|
||||
[^:]+: a067c001 stnt1w {z0\.s-z3\.s}, pn8, \[x0, #28, mul vl\]
|
||||
[^:]+: a065ce29 stnt1w {z8\.s-z11\.s}, pn11, \[x17, #20, mul vl\]
|
||||
[^:]+: a1604008 stnt1w {z0\.s, z8\.s}, pn8, \[x0\]
|
||||
[^:]+: a1604008 stnt1w {z0\.s, z8\.s}, pn8, \[x0\]
|
||||
[^:]+: a1604008 stnt1w {z0\.s, z8\.s}, pn8, \[x0\]
|
||||
[^:]+: a1604009 stnt1w {z1\.s, z9\.s}, pn8, \[x0\]
|
||||
[^:]+: a160400a stnt1w {z2\.s, z10\.s}, pn8, \[x0\]
|
||||
[^:]+: a160400b stnt1w {z3\.s, z11\.s}, pn8, \[x0\]
|
||||
[^:]+: a160400c stnt1w {z4\.s, z12\.s}, pn8, \[x0\]
|
||||
[^:]+: a160400d stnt1w {z5\.s, z13\.s}, pn8, \[x0\]
|
||||
[^:]+: a160400e stnt1w {z6\.s, z14\.s}, pn8, \[x0\]
|
||||
[^:]+: a160400f stnt1w {z7\.s, z15\.s}, pn8, \[x0\]
|
||||
[^:]+: a1604018 stnt1w {z16\.s, z24\.s}, pn8, \[x0\]
|
||||
[^:]+: a1604019 stnt1w {z17\.s, z25\.s}, pn8, \[x0\]
|
||||
[^:]+: a160401a stnt1w {z18\.s, z26\.s}, pn8, \[x0\]
|
||||
[^:]+: a160401b stnt1w {z19\.s, z27\.s}, pn8, \[x0\]
|
||||
[^:]+: a160401c stnt1w {z20\.s, z28\.s}, pn8, \[x0\]
|
||||
[^:]+: a160401d stnt1w {z21\.s, z29\.s}, pn8, \[x0\]
|
||||
[^:]+: a160401e stnt1w {z22\.s, z30\.s}, pn8, \[x0\]
|
||||
[^:]+: a160401f stnt1w {z23\.s, z31\.s}, pn8, \[x0\]
|
||||
[^:]+: a1605c08 stnt1w {z0\.s, z8\.s}, pn15, \[x0\]
|
||||
[^:]+: a16043c8 stnt1w {z0\.s, z8\.s}, pn8, \[x30\]
|
||||
[^:]+: a16043e8 stnt1w {z0\.s, z8\.s}, pn8, \[sp\]
|
||||
[^:]+: a1684008 stnt1w {z0\.s, z8\.s}, pn8, \[x0, #-16, mul vl\]
|
||||
[^:]+: a1674008 stnt1w {z0\.s, z8\.s}, pn8, \[x0, #14, mul vl\]
|
||||
[^:]+: a1634acb stnt1w {z3\.s, z11\.s}, pn10, \[x22, #6, mul vl\]
|
||||
[^:]+: a160c008 stnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0\]
|
||||
[^:]+: a160c008 stnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0\]
|
||||
[^:]+: a160c008 stnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0\]
|
||||
[^:]+: a160c009 stnt1w {z1\.s, z5\.s, z9\.s, z13\.s}, pn8, \[x0\]
|
||||
[^:]+: a160c00a stnt1w {z2\.s, z6\.s, z10\.s, z14\.s}, pn8, \[x0\]
|
||||
[^:]+: a160c00b stnt1w {z3\.s, z7\.s, z11\.s, z15\.s}, pn8, \[x0\]
|
||||
[^:]+: a160c018 stnt1w {z16\.s, z20\.s, z24\.s, z28\.s}, pn8, \[x0\]
|
||||
[^:]+: a160c019 stnt1w {z17\.s, z21\.s, z25\.s, z29\.s}, pn8, \[x0\]
|
||||
[^:]+: a160c01a stnt1w {z18\.s, z22\.s, z26\.s, z30\.s}, pn8, \[x0\]
|
||||
[^:]+: a160c01b stnt1w {z19\.s, z23\.s, z27\.s, z31\.s}, pn8, \[x0\]
|
||||
[^:]+: a160dc08 stnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn15, \[x0\]
|
||||
[^:]+: a160c3c8 stnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x30\]
|
||||
[^:]+: a160c3e8 stnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[sp\]
|
||||
[^:]+: a168c008 stnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0, #-32, mul vl\]
|
||||
[^:]+: a167c008 stnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0, #28, mul vl\]
|
||||
[^:]+: a162dbaa stnt1w {z2\.s, z6\.s, z10\.s, z14\.s}, pn14, \[x29, #8, mul vl\]
|
||||
[^:]+: a0214001 stnt1w {z0\.s-z1\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a0214001 stnt1w {z0\.s-z1\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a0214001 stnt1w {z0\.s-z1\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a021401f stnt1w {z30\.s-z31\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a0215c01 stnt1w {z0\.s-z1\.s}, pn15, \[x0, x1, lsl #2\]
|
||||
[^:]+: a02143c1 stnt1w {z0\.s-z1\.s}, pn8, \[x30, x1, lsl #2\]
|
||||
[^:]+: a02143e1 stnt1w {z0\.s-z1\.s}, pn8, \[sp, x1, lsl #2\]
|
||||
[^:]+: a03e4001 stnt1w {z0\.s-z1\.s}, pn8, \[x0, x30, lsl #2\]
|
||||
[^:]+: a03f4001 stnt1w {z0\.s-z1\.s}, pn8, \[x0, xzr, lsl #2\]
|
||||
[^:]+: a023474f stnt1w {z14\.s-z15\.s}, pn9, \[x26, x3, lsl #2\]
|
||||
[^:]+: a021c001 stnt1w {z0\.s-z3\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a021c001 stnt1w {z0\.s-z3\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a021c001 stnt1w {z0\.s-z3\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a021c01d stnt1w {z28\.s-z31\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a021dc01 stnt1w {z0\.s-z3\.s}, pn15, \[x0, x1, lsl #2\]
|
||||
[^:]+: a021c3c1 stnt1w {z0\.s-z3\.s}, pn8, \[x30, x1, lsl #2\]
|
||||
[^:]+: a021c3e1 stnt1w {z0\.s-z3\.s}, pn8, \[sp, x1, lsl #2\]
|
||||
[^:]+: a03ec001 stnt1w {z0\.s-z3\.s}, pn8, \[x0, x30, lsl #2\]
|
||||
[^:]+: a03fc001 stnt1w {z0\.s-z3\.s}, pn8, \[x0, xzr, lsl #2\]
|
||||
[^:]+: a021cf69 stnt1w {z8\.s-z11\.s}, pn11, \[x27, x1, lsl #2\]
|
||||
[^:]+: a1214008 stnt1w {z0\.s, z8\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1214008 stnt1w {z0\.s, z8\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1214008 stnt1w {z0\.s, z8\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1214009 stnt1w {z1\.s, z9\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a121400a stnt1w {z2\.s, z10\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a121400b stnt1w {z3\.s, z11\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a121400c stnt1w {z4\.s, z12\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a121400d stnt1w {z5\.s, z13\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a121400e stnt1w {z6\.s, z14\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a121400f stnt1w {z7\.s, z15\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1214018 stnt1w {z16\.s, z24\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1214019 stnt1w {z17\.s, z25\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a121401a stnt1w {z18\.s, z26\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a121401b stnt1w {z19\.s, z27\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a121401c stnt1w {z20\.s, z28\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a121401d stnt1w {z21\.s, z29\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a121401e stnt1w {z22\.s, z30\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a121401f stnt1w {z23\.s, z31\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a1215c08 stnt1w {z0\.s, z8\.s}, pn15, \[x0, x1, lsl #2\]
|
||||
[^:]+: a12143c8 stnt1w {z0\.s, z8\.s}, pn8, \[x30, x1, lsl #2\]
|
||||
[^:]+: a12143e8 stnt1w {z0\.s, z8\.s}, pn8, \[sp, x1, lsl #2\]
|
||||
[^:]+: a13e4008 stnt1w {z0\.s, z8\.s}, pn8, \[x0, x30, lsl #2\]
|
||||
[^:]+: a13f4008 stnt1w {z0\.s, z8\.s}, pn8, \[x0, xzr, lsl #2\]
|
||||
[^:]+: a13859ed stnt1w {z5\.s, z13\.s}, pn14, \[x15, x24, lsl #2\]
|
||||
[^:]+: a121c008 stnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a121c008 stnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a121c008 stnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a121c009 stnt1w {z1\.s, z5\.s, z9\.s, z13\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a121c00a stnt1w {z2\.s, z6\.s, z10\.s, z14\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a121c00b stnt1w {z3\.s, z7\.s, z11\.s, z15\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a121c018 stnt1w {z16\.s, z20\.s, z24\.s, z28\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a121c019 stnt1w {z17\.s, z21\.s, z25\.s, z29\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a121c01a stnt1w {z18\.s, z22\.s, z26\.s, z30\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a121c01b stnt1w {z19\.s, z23\.s, z27\.s, z31\.s}, pn8, \[x0, x1, lsl #2\]
|
||||
[^:]+: a121dc08 stnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn15, \[x0, x1, lsl #2\]
|
||||
[^:]+: a121c3c8 stnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x30, x1, lsl #2\]
|
||||
[^:]+: a121c3e8 stnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[sp, x1, lsl #2\]
|
||||
[^:]+: a13ec008 stnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0, x30, lsl #2\]
|
||||
[^:]+: a13fc008 stnt1w {z0\.s, z4\.s, z8\.s, z12\.s}, pn8, \[x0, xzr, lsl #2\]
|
||||
[^:]+: a126cc99 stnt1w {z17\.s, z21\.s, z25\.s, z29\.s}, pn11, \[x4, x6, lsl #2\]
|
||||
511
gas/testsuite/gas/aarch64/sme2-5.s
Normal file
511
gas/testsuite/gas/aarch64/sme2-5.s
Normal file
@ -0,0 +1,511 @@
|
||||
ld1w { z0.s - z1.s }, pn8/z, [x0]
|
||||
ld1w { z0.s - z1.s }, pn8/z, [x0, #0, mul vl]
|
||||
LD1W { Z0.S - Z1.S }, PN8/Z, [X0]
|
||||
ld1w { z30.s - z31.s }, pn8/z, [x0]
|
||||
ld1w { z0.s - z1.s }, pn15/z, [x0]
|
||||
ld1w { z0.s - z1.s }, pn8/z, [x30]
|
||||
ld1w { z0.s - z1.s }, pn8/z, [sp]
|
||||
ld1w { z0.s - z1.s }, pn8/z, [x0, #-16, mul vl]
|
||||
ld1w { z0.s - z1.s }, pn8/z, [x0, #14, mul vl]
|
||||
ld1w { z12.s - z13.s }, pn13/z, [x11, #-10, mul vl]
|
||||
|
||||
ld1w { z0.s - z3.s }, pn8/z, [x0]
|
||||
ld1w { z0.s - z3.s }, pn8/z, [x0, #0, mul vl]
|
||||
LD1W { Z0.S - Z3.S }, PN8/Z, [X0]
|
||||
ld1w { z28.s - z31.s }, pn8/z, [x0]
|
||||
ld1w { z0.s - z3.s }, pn15/z, [x0]
|
||||
ld1w { z0.s - z3.s }, pn8/z, [x30]
|
||||
ld1w { z0.s - z3.s }, pn8/z, [sp]
|
||||
ld1w { z0.s - z3.s }, pn8/z, [x0, #-32, mul vl]
|
||||
ld1w { z0.s - z3.s }, pn8/z, [x0, #28, mul vl]
|
||||
ld1w { z8.s - z11.s }, pn11/z, [x17, #20, mul vl]
|
||||
|
||||
ld1w { z0.s, z8.s }, pn8/z, [x0]
|
||||
ld1w { z0.s, z8.s }, pn8/z, [x0, #0, mul vl]
|
||||
LD1W { Z0.S, Z8.S }, PN8/Z, [X0]
|
||||
ld1w { z1.s, z9.s }, pn8/z, [x0]
|
||||
ld1w { z2.s, z10.s }, pn8/z, [x0]
|
||||
ld1w { z3.s, z11.s }, pn8/z, [x0]
|
||||
ld1w { z4.s, z12.s }, pn8/z, [x0]
|
||||
ld1w { z5.s, z13.s }, pn8/z, [x0]
|
||||
ld1w { z6.s, z14.s }, pn8/z, [x0]
|
||||
ld1w { z7.s, z15.s }, pn8/z, [x0]
|
||||
ld1w { z16.s, z24.s }, pn8/z, [x0]
|
||||
ld1w { z17.s, z25.s }, pn8/z, [x0]
|
||||
ld1w { z18.s, z26.s }, pn8/z, [x0]
|
||||
ld1w { z19.s, z27.s }, pn8/z, [x0]
|
||||
ld1w { z20.s, z28.s }, pn8/z, [x0]
|
||||
ld1w { z21.s, z29.s }, pn8/z, [x0]
|
||||
ld1w { z22.s, z30.s }, pn8/z, [x0]
|
||||
ld1w { z23.s, z31.s }, pn8/z, [x0]
|
||||
ld1w { z0.s, z8.s }, pn15/z, [x0]
|
||||
ld1w { z0.s, z8.s }, pn8/z, [x30]
|
||||
ld1w { z0.s, z8.s }, pn8/z, [sp]
|
||||
ld1w { z0.s, z8.s }, pn8/z, [x0, #-16, mul vl]
|
||||
ld1w { z0.s, z8.s }, pn8/z, [x0, #14, mul vl]
|
||||
ld1w { z3.s, z11.s }, pn10/z, [x22, #6, mul vl]
|
||||
|
||||
ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0]
|
||||
ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, #0, mul vl]
|
||||
LD1W { Z0.S, Z4.S, Z8.S, Z12.S }, PN8/Z, [X0]
|
||||
ld1w { z1.s, z5.s, z9.s, z13.s }, pn8/z, [x0]
|
||||
ld1w { z2.s, z6.s, z10.s, z14.s }, pn8/z, [x0]
|
||||
ld1w { z3.s, z7.s, z11.s, z15.s }, pn8/z, [x0]
|
||||
ld1w { z16.s, z20.s, z24.s, z28.s }, pn8/z, [x0]
|
||||
ld1w { z17.s, z21.s, z25.s, z29.s }, pn8/z, [x0]
|
||||
ld1w { z18.s, z22.s, z26.s, z30.s }, pn8/z, [x0]
|
||||
ld1w { z19.s, z23.s, z27.s, z31.s }, pn8/z, [x0]
|
||||
ld1w { z0.s, z4.s, z8.s, z12.s }, pn15/z, [x0]
|
||||
ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x30]
|
||||
ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [sp]
|
||||
ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, #-32, mul vl]
|
||||
ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, #28, mul vl]
|
||||
ld1w { z2.s, z6.s, z10.s, z14.s }, pn14/z, [x29, #8, mul vl]
|
||||
|
||||
ld1w { z0.s - z1.s }, pn8/z, [x0, x1, lsl 2]
|
||||
ld1w { z0.s - z1.s }, pn8/z, [x0, x1, lsl #2]
|
||||
LD1W { Z0.S - Z1.S }, PN8/Z, [X0, X1, LSL #2]
|
||||
ld1w { z30.s - z31.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z0.s - z1.s }, pn15/z, [x0, x1, lsl #2]
|
||||
ld1w { z0.s - z1.s }, pn8/z, [x30, x1, lsl #2]
|
||||
ld1w { z0.s - z1.s }, pn8/z, [sp, x1, lsl #2]
|
||||
ld1w { z0.s - z1.s }, pn8/z, [x0, x30, lsl #2]
|
||||
ld1w { z0.s - z1.s }, pn8/z, [x0, xzr, lsl #2]
|
||||
ld1w { z14.s - z15.s }, pn9/z, [x26, x3, lsl #2]
|
||||
|
||||
ld1w { z0.s - z3.s }, pn8/z, [x0, x1, lsl 2]
|
||||
ld1w { z0.s - z3.s }, pn8/z, [x0, x1, lsl #2]
|
||||
LD1W { Z0.S - Z3.S }, PN8/Z, [X0, X1, LSL #2]
|
||||
ld1w { z28.s - z31.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z0.s - z3.s }, pn15/z, [x0, x1, lsl #2]
|
||||
ld1w { z0.s - z3.s }, pn8/z, [x30, x1, lsl #2]
|
||||
ld1w { z0.s - z3.s }, pn8/z, [sp, x1, lsl #2]
|
||||
ld1w { z0.s - z3.s }, pn8/z, [x0, x30, lsl #2]
|
||||
ld1w { z0.s - z3.s }, pn8/z, [x0, xzr, lsl #2]
|
||||
ld1w { z8.s - z11.s }, pn11/z, [x27, x1, lsl #2]
|
||||
|
||||
ld1w { z0.s, z8.s }, pn8/z, [x0, x1, lsl 2]
|
||||
ld1w { z0.s, z8.s }, pn8/z, [x0, x1, lsl #2]
|
||||
LD1W { Z0.S, Z8.S }, PN8/Z, [X0, X1, LSL #2]
|
||||
ld1w { z1.s, z9.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z2.s, z10.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z3.s, z11.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z4.s, z12.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z5.s, z13.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z6.s, z14.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z7.s, z15.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z16.s, z24.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z17.s, z25.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z18.s, z26.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z19.s, z27.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z20.s, z28.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z21.s, z29.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z22.s, z30.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z23.s, z31.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z0.s, z8.s }, pn15/z, [x0, x1, lsl #2]
|
||||
ld1w { z0.s, z8.s }, pn8/z, [x30, x1, lsl #2]
|
||||
ld1w { z0.s, z8.s }, pn8/z, [sp, x1, lsl #2]
|
||||
ld1w { z0.s, z8.s }, pn8/z, [x0, x30, lsl #2]
|
||||
ld1w { z0.s, z8.s }, pn8/z, [x0, xzr, lsl #2]
|
||||
ld1w { z5.s, z13.s }, pn14/z, [x15, x24, lsl #2]
|
||||
|
||||
ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, x1, lsl 2]
|
||||
ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, x1, lsl #2]
|
||||
LD1W { Z0.S, Z4.S, Z8.S, Z12.S }, PN8/Z, [X0, X1, LSL #2]
|
||||
ld1w { z1.s, z5.s, z9.s, z13.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z2.s, z6.s, z10.s, z14.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z3.s, z7.s, z11.s, z15.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z16.s, z20.s, z24.s, z28.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z17.s, z21.s, z25.s, z29.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z18.s, z22.s, z26.s, z30.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z19.s, z23.s, z27.s, z31.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ld1w { z0.s, z4.s, z8.s, z12.s }, pn15/z, [x0, x1, lsl #2]
|
||||
ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x30, x1, lsl #2]
|
||||
ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [sp, x1, lsl #2]
|
||||
ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, x30, lsl #2]
|
||||
ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, xzr, lsl #2]
|
||||
ld1w { z17.s, z21.s, z25.s, z29.s }, pn11/z, [x4, x6, lsl #2]
|
||||
|
||||
ldnt1w { z0.s - z1.s }, pn8/z, [x0]
|
||||
ldnt1w { z0.s - z1.s }, pn8/z, [x0, #0, mul vl]
|
||||
LDNT1W { Z0.S - Z1.S }, PN8/Z, [X0]
|
||||
ldnt1w { z30.s - z31.s }, pn8/z, [x0]
|
||||
ldnt1w { z0.s - z1.s }, pn15/z, [x0]
|
||||
ldnt1w { z0.s - z1.s }, pn8/z, [x30]
|
||||
ldnt1w { z0.s - z1.s }, pn8/z, [sp]
|
||||
ldnt1w { z0.s - z1.s }, pn8/z, [x0, #-16, mul vl]
|
||||
ldnt1w { z0.s - z1.s }, pn8/z, [x0, #14, mul vl]
|
||||
ldnt1w { z12.s - z13.s }, pn13/z, [x11, #-10, mul vl]
|
||||
|
||||
ldnt1w { z0.s - z3.s }, pn8/z, [x0]
|
||||
ldnt1w { z0.s - z3.s }, pn8/z, [x0, #0, mul vl]
|
||||
LDNT1W { Z0.S - Z3.S }, PN8/Z, [X0]
|
||||
ldnt1w { z28.s - z31.s }, pn8/z, [x0]
|
||||
ldnt1w { z0.s - z3.s }, pn15/z, [x0]
|
||||
ldnt1w { z0.s - z3.s }, pn8/z, [x30]
|
||||
ldnt1w { z0.s - z3.s }, pn8/z, [sp]
|
||||
ldnt1w { z0.s - z3.s }, pn8/z, [x0, #-32, mul vl]
|
||||
ldnt1w { z0.s - z3.s }, pn8/z, [x0, #28, mul vl]
|
||||
ldnt1w { z8.s - z11.s }, pn11/z, [x17, #20, mul vl]
|
||||
|
||||
ldnt1w { z0.s, z8.s }, pn8/z, [x0]
|
||||
ldnt1w { z0.s, z8.s }, pn8/z, [x0, #0, mul vl]
|
||||
LDNT1W { Z0.S, Z8.S }, PN8/Z, [X0]
|
||||
ldnt1w { z1.s, z9.s }, pn8/z, [x0]
|
||||
ldnt1w { z2.s, z10.s }, pn8/z, [x0]
|
||||
ldnt1w { z3.s, z11.s }, pn8/z, [x0]
|
||||
ldnt1w { z4.s, z12.s }, pn8/z, [x0]
|
||||
ldnt1w { z5.s, z13.s }, pn8/z, [x0]
|
||||
ldnt1w { z6.s, z14.s }, pn8/z, [x0]
|
||||
ldnt1w { z7.s, z15.s }, pn8/z, [x0]
|
||||
ldnt1w { z16.s, z24.s }, pn8/z, [x0]
|
||||
ldnt1w { z17.s, z25.s }, pn8/z, [x0]
|
||||
ldnt1w { z18.s, z26.s }, pn8/z, [x0]
|
||||
ldnt1w { z19.s, z27.s }, pn8/z, [x0]
|
||||
ldnt1w { z20.s, z28.s }, pn8/z, [x0]
|
||||
ldnt1w { z21.s, z29.s }, pn8/z, [x0]
|
||||
ldnt1w { z22.s, z30.s }, pn8/z, [x0]
|
||||
ldnt1w { z23.s, z31.s }, pn8/z, [x0]
|
||||
ldnt1w { z0.s, z8.s }, pn15/z, [x0]
|
||||
ldnt1w { z0.s, z8.s }, pn8/z, [x30]
|
||||
ldnt1w { z0.s, z8.s }, pn8/z, [sp]
|
||||
ldnt1w { z0.s, z8.s }, pn8/z, [x0, #-16, mul vl]
|
||||
ldnt1w { z0.s, z8.s }, pn8/z, [x0, #14, mul vl]
|
||||
ldnt1w { z3.s, z11.s }, pn10/z, [x22, #6, mul vl]
|
||||
|
||||
ldnt1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0]
|
||||
ldnt1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, #0, mul vl]
|
||||
LDNT1W { Z0.S, Z4.S, Z8.S, Z12.S }, PN8/Z, [X0]
|
||||
ldnt1w { z1.s, z5.s, z9.s, z13.s }, pn8/z, [x0]
|
||||
ldnt1w { z2.s, z6.s, z10.s, z14.s }, pn8/z, [x0]
|
||||
ldnt1w { z3.s, z7.s, z11.s, z15.s }, pn8/z, [x0]
|
||||
ldnt1w { z16.s, z20.s, z24.s, z28.s }, pn8/z, [x0]
|
||||
ldnt1w { z17.s, z21.s, z25.s, z29.s }, pn8/z, [x0]
|
||||
ldnt1w { z18.s, z22.s, z26.s, z30.s }, pn8/z, [x0]
|
||||
ldnt1w { z19.s, z23.s, z27.s, z31.s }, pn8/z, [x0]
|
||||
ldnt1w { z0.s, z4.s, z8.s, z12.s }, pn15/z, [x0]
|
||||
ldnt1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x30]
|
||||
ldnt1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [sp]
|
||||
ldnt1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, #-32, mul vl]
|
||||
ldnt1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, #28, mul vl]
|
||||
ldnt1w { z2.s, z6.s, z10.s, z14.s }, pn14/z, [x29, #8, mul vl]
|
||||
|
||||
ldnt1w { z0.s - z1.s }, pn8/z, [x0, x1, lsl 2]
|
||||
ldnt1w { z0.s - z1.s }, pn8/z, [x0, x1, lsl #2]
|
||||
LDNT1W { Z0.S - Z1.S }, PN8/Z, [X0, X1, LSL #2]
|
||||
ldnt1w { z30.s - z31.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ldnt1w { z0.s - z1.s }, pn15/z, [x0, x1, lsl #2]
|
||||
ldnt1w { z0.s - z1.s }, pn8/z, [x30, x1, lsl #2]
|
||||
ldnt1w { z0.s - z1.s }, pn8/z, [sp, x1, lsl #2]
|
||||
ldnt1w { z0.s - z1.s }, pn8/z, [x0, x30, lsl #2]
|
||||
ldnt1w { z0.s - z1.s }, pn8/z, [x0, xzr, lsl #2]
|
||||
ldnt1w { z14.s - z15.s }, pn9/z, [x26, x3, lsl #2]
|
||||
|
||||
ldnt1w { z0.s - z3.s }, pn8/z, [x0, x1, lsl 2]
|
||||
ldnt1w { z0.s - z3.s }, pn8/z, [x0, x1, lsl #2]
|
||||
LDNT1W { Z0.S - Z3.S }, PN8/Z, [X0, X1, LSL #2]
|
||||
ldnt1w { z28.s - z31.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ldnt1w { z0.s - z3.s }, pn15/z, [x0, x1, lsl #2]
|
||||
ldnt1w { z0.s - z3.s }, pn8/z, [x30, x1, lsl #2]
|
||||
ldnt1w { z0.s - z3.s }, pn8/z, [sp, x1, lsl #2]
|
||||
ldnt1w { z0.s - z3.s }, pn8/z, [x0, x30, lsl #2]
|
||||
ldnt1w { z0.s - z3.s }, pn8/z, [x0, xzr, lsl #2]
|
||||
ldnt1w { z8.s - z11.s }, pn11/z, [x27, x1, lsl #2]
|
||||
|
||||
ldnt1w { z0.s, z8.s }, pn8/z, [x0, x1, lsl 2]
|
||||
ldnt1w { z0.s, z8.s }, pn8/z, [x0, x1, lsl #2]
|
||||
LDNT1W { Z0.S, Z8.S }, PN8/Z, [X0, X1, LSL #2]
|
||||
ldnt1w { z1.s, z9.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ldnt1w { z2.s, z10.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ldnt1w { z3.s, z11.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ldnt1w { z4.s, z12.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ldnt1w { z5.s, z13.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ldnt1w { z6.s, z14.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ldnt1w { z7.s, z15.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ldnt1w { z16.s, z24.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ldnt1w { z17.s, z25.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ldnt1w { z18.s, z26.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ldnt1w { z19.s, z27.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ldnt1w { z20.s, z28.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ldnt1w { z21.s, z29.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ldnt1w { z22.s, z30.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ldnt1w { z23.s, z31.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ldnt1w { z0.s, z8.s }, pn15/z, [x0, x1, lsl #2]
|
||||
ldnt1w { z0.s, z8.s }, pn8/z, [x30, x1, lsl #2]
|
||||
ldnt1w { z0.s, z8.s }, pn8/z, [sp, x1, lsl #2]
|
||||
ldnt1w { z0.s, z8.s }, pn8/z, [x0, x30, lsl #2]
|
||||
ldnt1w { z0.s, z8.s }, pn8/z, [x0, xzr, lsl #2]
|
||||
ldnt1w { z5.s, z13.s }, pn14/z, [x15, x24, lsl #2]
|
||||
|
||||
ldnt1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, x1, lsl 2]
|
||||
ldnt1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, x1, lsl #2]
|
||||
LDNT1W { Z0.S, Z4.S, Z8.S, Z12.S }, PN8/Z, [X0, X1, LSL #2]
|
||||
ldnt1w { z1.s, z5.s, z9.s, z13.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ldnt1w { z2.s, z6.s, z10.s, z14.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ldnt1w { z3.s, z7.s, z11.s, z15.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ldnt1w { z16.s, z20.s, z24.s, z28.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ldnt1w { z17.s, z21.s, z25.s, z29.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ldnt1w { z18.s, z22.s, z26.s, z30.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ldnt1w { z19.s, z23.s, z27.s, z31.s }, pn8/z, [x0, x1, lsl #2]
|
||||
ldnt1w { z0.s, z4.s, z8.s, z12.s }, pn15/z, [x0, x1, lsl #2]
|
||||
ldnt1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x30, x1, lsl #2]
|
||||
ldnt1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [sp, x1, lsl #2]
|
||||
ldnt1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, x30, lsl #2]
|
||||
ldnt1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, xzr, lsl #2]
|
||||
ldnt1w { z17.s, z21.s, z25.s, z29.s }, pn11/z, [x4, x6, lsl #2]
|
||||
|
||||
st1w { z0.s - z1.s }, pn8, [x0]
|
||||
st1w { z0.s - z1.s }, pn8, [x0, #0, mul vl]
|
||||
ST1W { Z0.S - Z1.S }, PN8, [X0]
|
||||
st1w { z30.s - z31.s }, pn8, [x0]
|
||||
st1w { z0.s - z1.s }, pn15, [x0]
|
||||
st1w { z0.s - z1.s }, pn8, [x30]
|
||||
st1w { z0.s - z1.s }, pn8, [sp]
|
||||
st1w { z0.s - z1.s }, pn8, [x0, #-16, mul vl]
|
||||
st1w { z0.s - z1.s }, pn8, [x0, #14, mul vl]
|
||||
st1w { z12.s - z13.s }, pn13, [x11, #-10, mul vl]
|
||||
|
||||
st1w { z0.s - z3.s }, pn8, [x0]
|
||||
st1w { z0.s - z3.s }, pn8, [x0, #0, mul vl]
|
||||
ST1W { Z0.S - Z3.S }, PN8, [X0]
|
||||
st1w { z28.s - z31.s }, pn8, [x0]
|
||||
st1w { z0.s - z3.s }, pn15, [x0]
|
||||
st1w { z0.s - z3.s }, pn8, [x30]
|
||||
st1w { z0.s - z3.s }, pn8, [sp]
|
||||
st1w { z0.s - z3.s }, pn8, [x0, #-32, mul vl]
|
||||
st1w { z0.s - z3.s }, pn8, [x0, #28, mul vl]
|
||||
st1w { z8.s - z11.s }, pn11, [x17, #20, mul vl]
|
||||
|
||||
st1w { z0.s, z8.s }, pn8, [x0]
|
||||
st1w { z0.s, z8.s }, pn8, [x0, #0, mul vl]
|
||||
ST1W { Z0.S, Z8.S }, PN8, [X0]
|
||||
st1w { z1.s, z9.s }, pn8, [x0]
|
||||
st1w { z2.s, z10.s }, pn8, [x0]
|
||||
st1w { z3.s, z11.s }, pn8, [x0]
|
||||
st1w { z4.s, z12.s }, pn8, [x0]
|
||||
st1w { z5.s, z13.s }, pn8, [x0]
|
||||
st1w { z6.s, z14.s }, pn8, [x0]
|
||||
st1w { z7.s, z15.s }, pn8, [x0]
|
||||
st1w { z16.s, z24.s }, pn8, [x0]
|
||||
st1w { z17.s, z25.s }, pn8, [x0]
|
||||
st1w { z18.s, z26.s }, pn8, [x0]
|
||||
st1w { z19.s, z27.s }, pn8, [x0]
|
||||
st1w { z20.s, z28.s }, pn8, [x0]
|
||||
st1w { z21.s, z29.s }, pn8, [x0]
|
||||
st1w { z22.s, z30.s }, pn8, [x0]
|
||||
st1w { z23.s, z31.s }, pn8, [x0]
|
||||
st1w { z0.s, z8.s }, pn15, [x0]
|
||||
st1w { z0.s, z8.s }, pn8, [x30]
|
||||
st1w { z0.s, z8.s }, pn8, [sp]
|
||||
st1w { z0.s, z8.s }, pn8, [x0, #-16, mul vl]
|
||||
st1w { z0.s, z8.s }, pn8, [x0, #14, mul vl]
|
||||
st1w { z3.s, z11.s }, pn10, [x22, #6, mul vl]
|
||||
|
||||
st1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0]
|
||||
st1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, #0, mul vl]
|
||||
ST1W { Z0.S, Z4.S, Z8.S, Z12.S }, PN8, [X0]
|
||||
st1w { z1.s, z5.s, z9.s, z13.s }, pn8, [x0]
|
||||
st1w { z2.s, z6.s, z10.s, z14.s }, pn8, [x0]
|
||||
st1w { z3.s, z7.s, z11.s, z15.s }, pn8, [x0]
|
||||
st1w { z16.s, z20.s, z24.s, z28.s }, pn8, [x0]
|
||||
st1w { z17.s, z21.s, z25.s, z29.s }, pn8, [x0]
|
||||
st1w { z18.s, z22.s, z26.s, z30.s }, pn8, [x0]
|
||||
st1w { z19.s, z23.s, z27.s, z31.s }, pn8, [x0]
|
||||
st1w { z0.s, z4.s, z8.s, z12.s }, pn15, [x0]
|
||||
st1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x30]
|
||||
st1w { z0.s, z4.s, z8.s, z12.s }, pn8, [sp]
|
||||
st1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, #-32, mul vl]
|
||||
st1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, #28, mul vl]
|
||||
st1w { z2.s, z6.s, z10.s, z14.s }, pn14, [x29, #8, mul vl]
|
||||
|
||||
st1w { z0.s - z1.s }, pn8, [x0, x1, lsl 2]
|
||||
st1w { z0.s - z1.s }, pn8, [x0, x1, lsl #2]
|
||||
ST1W { Z0.S - Z1.S }, PN8, [X0, X1, LSL #2]
|
||||
st1w { z30.s - z31.s }, pn8, [x0, x1, lsl #2]
|
||||
st1w { z0.s - z1.s }, pn15, [x0, x1, lsl #2]
|
||||
st1w { z0.s - z1.s }, pn8, [x30, x1, lsl #2]
|
||||
st1w { z0.s - z1.s }, pn8, [sp, x1, lsl #2]
|
||||
st1w { z0.s - z1.s }, pn8, [x0, x30, lsl #2]
|
||||
st1w { z0.s - z1.s }, pn8, [x0, xzr, lsl #2]
|
||||
st1w { z14.s - z15.s }, pn9, [x26, x3, lsl #2]
|
||||
|
||||
st1w { z0.s - z3.s }, pn8, [x0, x1, lsl 2]
|
||||
st1w { z0.s - z3.s }, pn8, [x0, x1, lsl #2]
|
||||
ST1W { Z0.S - Z3.S }, PN8, [X0, X1, LSL #2]
|
||||
st1w { z28.s - z31.s }, pn8, [x0, x1, lsl #2]
|
||||
st1w { z0.s - z3.s }, pn15, [x0, x1, lsl #2]
|
||||
st1w { z0.s - z3.s }, pn8, [x30, x1, lsl #2]
|
||||
st1w { z0.s - z3.s }, pn8, [sp, x1, lsl #2]
|
||||
st1w { z0.s - z3.s }, pn8, [x0, x30, lsl #2]
|
||||
st1w { z0.s - z3.s }, pn8, [x0, xzr, lsl #2]
|
||||
st1w { z8.s - z11.s }, pn11, [x27, x1, lsl #2]
|
||||
|
||||
st1w { z0.s, z8.s }, pn8, [x0, x1, lsl 2]
|
||||
st1w { z0.s, z8.s }, pn8, [x0, x1, lsl #2]
|
||||
ST1W { Z0.S, Z8.S }, PN8, [X0, X1, LSL #2]
|
||||
st1w { z1.s, z9.s }, pn8, [x0, x1, lsl #2]
|
||||
st1w { z2.s, z10.s }, pn8, [x0, x1, lsl #2]
|
||||
st1w { z3.s, z11.s }, pn8, [x0, x1, lsl #2]
|
||||
st1w { z4.s, z12.s }, pn8, [x0, x1, lsl #2]
|
||||
st1w { z5.s, z13.s }, pn8, [x0, x1, lsl #2]
|
||||
st1w { z6.s, z14.s }, pn8, [x0, x1, lsl #2]
|
||||
st1w { z7.s, z15.s }, pn8, [x0, x1, lsl #2]
|
||||
st1w { z16.s, z24.s }, pn8, [x0, x1, lsl #2]
|
||||
st1w { z17.s, z25.s }, pn8, [x0, x1, lsl #2]
|
||||
st1w { z18.s, z26.s }, pn8, [x0, x1, lsl #2]
|
||||
st1w { z19.s, z27.s }, pn8, [x0, x1, lsl #2]
|
||||
st1w { z20.s, z28.s }, pn8, [x0, x1, lsl #2]
|
||||
st1w { z21.s, z29.s }, pn8, [x0, x1, lsl #2]
|
||||
st1w { z22.s, z30.s }, pn8, [x0, x1, lsl #2]
|
||||
st1w { z23.s, z31.s }, pn8, [x0, x1, lsl #2]
|
||||
st1w { z0.s, z8.s }, pn15, [x0, x1, lsl #2]
|
||||
st1w { z0.s, z8.s }, pn8, [x30, x1, lsl #2]
|
||||
st1w { z0.s, z8.s }, pn8, [sp, x1, lsl #2]
|
||||
st1w { z0.s, z8.s }, pn8, [x0, x30, lsl #2]
|
||||
st1w { z0.s, z8.s }, pn8, [x0, xzr, lsl #2]
|
||||
st1w { z5.s, z13.s }, pn14, [x15, x24, lsl #2]
|
||||
|
||||
st1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, x1, lsl 2]
|
||||
st1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, x1, lsl #2]
|
||||
ST1W { Z0.S, Z4.S, Z8.S, Z12.S }, PN8, [X0, X1, LSL #2]
|
||||
st1w { z1.s, z5.s, z9.s, z13.s }, pn8, [x0, x1, lsl #2]
|
||||
st1w { z2.s, z6.s, z10.s, z14.s }, pn8, [x0, x1, lsl #2]
|
||||
st1w { z3.s, z7.s, z11.s, z15.s }, pn8, [x0, x1, lsl #2]
|
||||
st1w { z16.s, z20.s, z24.s, z28.s }, pn8, [x0, x1, lsl #2]
|
||||
st1w { z17.s, z21.s, z25.s, z29.s }, pn8, [x0, x1, lsl #2]
|
||||
st1w { z18.s, z22.s, z26.s, z30.s }, pn8, [x0, x1, lsl #2]
|
||||
st1w { z19.s, z23.s, z27.s, z31.s }, pn8, [x0, x1, lsl #2]
|
||||
st1w { z0.s, z4.s, z8.s, z12.s }, pn15, [x0, x1, lsl #2]
|
||||
st1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x30, x1, lsl #2]
|
||||
st1w { z0.s, z4.s, z8.s, z12.s }, pn8, [sp, x1, lsl #2]
|
||||
st1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, x30, lsl #2]
|
||||
st1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, xzr, lsl #2]
|
||||
st1w { z17.s, z21.s, z25.s, z29.s }, pn11, [x4, x6, lsl #2]
|
||||
|
||||
stnt1w { z0.s - z1.s }, pn8, [x0]
|
||||
stnt1w { z0.s - z1.s }, pn8, [x0, #0, mul vl]
|
||||
STNT1W { Z0.S - Z1.S }, PN8, [X0]
|
||||
stnt1w { z30.s - z31.s }, pn8, [x0]
|
||||
stnt1w { z0.s - z1.s }, pn15, [x0]
|
||||
stnt1w { z0.s - z1.s }, pn8, [x30]
|
||||
stnt1w { z0.s - z1.s }, pn8, [sp]
|
||||
stnt1w { z0.s - z1.s }, pn8, [x0, #-16, mul vl]
|
||||
stnt1w { z0.s - z1.s }, pn8, [x0, #14, mul vl]
|
||||
stnt1w { z12.s - z13.s }, pn13, [x11, #-10, mul vl]
|
||||
|
||||
stnt1w { z0.s - z3.s }, pn8, [x0]
|
||||
stnt1w { z0.s - z3.s }, pn8, [x0, #0, mul vl]
|
||||
STNT1W { Z0.S - Z3.S }, PN8, [X0]
|
||||
stnt1w { z28.s - z31.s }, pn8, [x0]
|
||||
stnt1w { z0.s - z3.s }, pn15, [x0]
|
||||
stnt1w { z0.s - z3.s }, pn8, [x30]
|
||||
stnt1w { z0.s - z3.s }, pn8, [sp]
|
||||
stnt1w { z0.s - z3.s }, pn8, [x0, #-32, mul vl]
|
||||
stnt1w { z0.s - z3.s }, pn8, [x0, #28, mul vl]
|
||||
stnt1w { z8.s - z11.s }, pn11, [x17, #20, mul vl]
|
||||
|
||||
stnt1w { z0.s, z8.s }, pn8, [x0]
|
||||
stnt1w { z0.s, z8.s }, pn8, [x0, #0, mul vl]
|
||||
STNT1W { Z0.S, Z8.S }, PN8, [X0]
|
||||
stnt1w { z1.s, z9.s }, pn8, [x0]
|
||||
stnt1w { z2.s, z10.s }, pn8, [x0]
|
||||
stnt1w { z3.s, z11.s }, pn8, [x0]
|
||||
stnt1w { z4.s, z12.s }, pn8, [x0]
|
||||
stnt1w { z5.s, z13.s }, pn8, [x0]
|
||||
stnt1w { z6.s, z14.s }, pn8, [x0]
|
||||
stnt1w { z7.s, z15.s }, pn8, [x0]
|
||||
stnt1w { z16.s, z24.s }, pn8, [x0]
|
||||
stnt1w { z17.s, z25.s }, pn8, [x0]
|
||||
stnt1w { z18.s, z26.s }, pn8, [x0]
|
||||
stnt1w { z19.s, z27.s }, pn8, [x0]
|
||||
stnt1w { z20.s, z28.s }, pn8, [x0]
|
||||
stnt1w { z21.s, z29.s }, pn8, [x0]
|
||||
stnt1w { z22.s, z30.s }, pn8, [x0]
|
||||
stnt1w { z23.s, z31.s }, pn8, [x0]
|
||||
stnt1w { z0.s, z8.s }, pn15, [x0]
|
||||
stnt1w { z0.s, z8.s }, pn8, [x30]
|
||||
stnt1w { z0.s, z8.s }, pn8, [sp]
|
||||
stnt1w { z0.s, z8.s }, pn8, [x0, #-16, mul vl]
|
||||
stnt1w { z0.s, z8.s }, pn8, [x0, #14, mul vl]
|
||||
stnt1w { z3.s, z11.s }, pn10, [x22, #6, mul vl]
|
||||
|
||||
stnt1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0]
|
||||
stnt1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, #0, mul vl]
|
||||
STNT1W { Z0.S, Z4.S, Z8.S, Z12.S }, PN8, [X0]
|
||||
stnt1w { z1.s, z5.s, z9.s, z13.s }, pn8, [x0]
|
||||
stnt1w { z2.s, z6.s, z10.s, z14.s }, pn8, [x0]
|
||||
stnt1w { z3.s, z7.s, z11.s, z15.s }, pn8, [x0]
|
||||
stnt1w { z16.s, z20.s, z24.s, z28.s }, pn8, [x0]
|
||||
stnt1w { z17.s, z21.s, z25.s, z29.s }, pn8, [x0]
|
||||
stnt1w { z18.s, z22.s, z26.s, z30.s }, pn8, [x0]
|
||||
stnt1w { z19.s, z23.s, z27.s, z31.s }, pn8, [x0]
|
||||
stnt1w { z0.s, z4.s, z8.s, z12.s }, pn15, [x0]
|
||||
stnt1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x30]
|
||||
stnt1w { z0.s, z4.s, z8.s, z12.s }, pn8, [sp]
|
||||
stnt1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, #-32, mul vl]
|
||||
stnt1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, #28, mul vl]
|
||||
stnt1w { z2.s, z6.s, z10.s, z14.s }, pn14, [x29, #8, mul vl]
|
||||
|
||||
stnt1w { z0.s - z1.s }, pn8, [x0, x1, lsl 2]
|
||||
stnt1w { z0.s - z1.s }, pn8, [x0, x1, lsl #2]
|
||||
STNT1W { Z0.S - Z1.S }, PN8, [X0, X1, LSL #2]
|
||||
stnt1w { z30.s - z31.s }, pn8, [x0, x1, lsl #2]
|
||||
stnt1w { z0.s - z1.s }, pn15, [x0, x1, lsl #2]
|
||||
stnt1w { z0.s - z1.s }, pn8, [x30, x1, lsl #2]
|
||||
stnt1w { z0.s - z1.s }, pn8, [sp, x1, lsl #2]
|
||||
stnt1w { z0.s - z1.s }, pn8, [x0, x30, lsl #2]
|
||||
stnt1w { z0.s - z1.s }, pn8, [x0, xzr, lsl #2]
|
||||
stnt1w { z14.s - z15.s }, pn9, [x26, x3, lsl #2]
|
||||
|
||||
stnt1w { z0.s - z3.s }, pn8, [x0, x1, lsl 2]
|
||||
stnt1w { z0.s - z3.s }, pn8, [x0, x1, lsl #2]
|
||||
STNT1W { Z0.S - Z3.S }, PN8, [X0, X1, LSL #2]
|
||||
stnt1w { z28.s - z31.s }, pn8, [x0, x1, lsl #2]
|
||||
stnt1w { z0.s - z3.s }, pn15, [x0, x1, lsl #2]
|
||||
stnt1w { z0.s - z3.s }, pn8, [x30, x1, lsl #2]
|
||||
stnt1w { z0.s - z3.s }, pn8, [sp, x1, lsl #2]
|
||||
stnt1w { z0.s - z3.s }, pn8, [x0, x30, lsl #2]
|
||||
stnt1w { z0.s - z3.s }, pn8, [x0, xzr, lsl #2]
|
||||
stnt1w { z8.s - z11.s }, pn11, [x27, x1, lsl #2]
|
||||
|
||||
stnt1w { z0.s, z8.s }, pn8, [x0, x1, lsl 2]
|
||||
stnt1w { z0.s, z8.s }, pn8, [x0, x1, lsl #2]
|
||||
STNT1W { Z0.S, Z8.S }, PN8, [X0, X1, LSL #2]
|
||||
stnt1w { z1.s, z9.s }, pn8, [x0, x1, lsl #2]
|
||||
stnt1w { z2.s, z10.s }, pn8, [x0, x1, lsl #2]
|
||||
stnt1w { z3.s, z11.s }, pn8, [x0, x1, lsl #2]
|
||||
stnt1w { z4.s, z12.s }, pn8, [x0, x1, lsl #2]
|
||||
stnt1w { z5.s, z13.s }, pn8, [x0, x1, lsl #2]
|
||||
stnt1w { z6.s, z14.s }, pn8, [x0, x1, lsl #2]
|
||||
stnt1w { z7.s, z15.s }, pn8, [x0, x1, lsl #2]
|
||||
stnt1w { z16.s, z24.s }, pn8, [x0, x1, lsl #2]
|
||||
stnt1w { z17.s, z25.s }, pn8, [x0, x1, lsl #2]
|
||||
stnt1w { z18.s, z26.s }, pn8, [x0, x1, lsl #2]
|
||||
stnt1w { z19.s, z27.s }, pn8, [x0, x1, lsl #2]
|
||||
stnt1w { z20.s, z28.s }, pn8, [x0, x1, lsl #2]
|
||||
stnt1w { z21.s, z29.s }, pn8, [x0, x1, lsl #2]
|
||||
stnt1w { z22.s, z30.s }, pn8, [x0, x1, lsl #2]
|
||||
stnt1w { z23.s, z31.s }, pn8, [x0, x1, lsl #2]
|
||||
stnt1w { z0.s, z8.s }, pn15, [x0, x1, lsl #2]
|
||||
stnt1w { z0.s, z8.s }, pn8, [x30, x1, lsl #2]
|
||||
stnt1w { z0.s, z8.s }, pn8, [sp, x1, lsl #2]
|
||||
stnt1w { z0.s, z8.s }, pn8, [x0, x30, lsl #2]
|
||||
stnt1w { z0.s, z8.s }, pn8, [x0, xzr, lsl #2]
|
||||
stnt1w { z5.s, z13.s }, pn14, [x15, x24, lsl #2]
|
||||
|
||||
stnt1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, x1, lsl 2]
|
||||
stnt1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, x1, lsl #2]
|
||||
STNT1W { Z0.S, Z4.S, Z8.S, Z12.S }, PN8, [X0, X1, LSL #2]
|
||||
stnt1w { z1.s, z5.s, z9.s, z13.s }, pn8, [x0, x1, lsl #2]
|
||||
stnt1w { z2.s, z6.s, z10.s, z14.s }, pn8, [x0, x1, lsl #2]
|
||||
stnt1w { z3.s, z7.s, z11.s, z15.s }, pn8, [x0, x1, lsl #2]
|
||||
stnt1w { z16.s, z20.s, z24.s, z28.s }, pn8, [x0, x1, lsl #2]
|
||||
stnt1w { z17.s, z21.s, z25.s, z29.s }, pn8, [x0, x1, lsl #2]
|
||||
stnt1w { z18.s, z22.s, z26.s, z30.s }, pn8, [x0, x1, lsl #2]
|
||||
stnt1w { z19.s, z23.s, z27.s, z31.s }, pn8, [x0, x1, lsl #2]
|
||||
stnt1w { z0.s, z4.s, z8.s, z12.s }, pn15, [x0, x1, lsl #2]
|
||||
stnt1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x30, x1, lsl #2]
|
||||
stnt1w { z0.s, z4.s, z8.s, z12.s }, pn8, [sp, x1, lsl #2]
|
||||
stnt1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, x30, lsl #2]
|
||||
stnt1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, xzr, lsl #2]
|
||||
stnt1w { z17.s, z21.s, z25.s, z29.s }, pn11, [x4, x6, lsl #2]
|
||||
@ -489,6 +489,8 @@ enum aarch64_opnd
|
||||
AARCH64_OPND_SME_Zdnx4, /* SVE vector register list from [4:2]*4. */
|
||||
AARCH64_OPND_SME_Znx2, /* SVE vector register list from [9:6]*2. */
|
||||
AARCH64_OPND_SME_Znx4, /* SVE vector register list from [9:7]*4. */
|
||||
AARCH64_OPND_SME_Ztx2_STRIDED, /* SVE vector register list in [4:0]&23. */
|
||||
AARCH64_OPND_SME_Ztx4_STRIDED, /* SVE vector register list in [4:0]&19. */
|
||||
AARCH64_OPND_SME_ZAda_2b, /* SME <ZAda>.S, 2-bits. */
|
||||
AARCH64_OPND_SME_ZAda_3b, /* SME <ZAda>.D, 3-bits. */
|
||||
AARCH64_OPND_SME_ZA_HV_idx_src, /* SME source ZA tile vector. */
|
||||
@ -496,6 +498,7 @@ enum aarch64_opnd
|
||||
AARCH64_OPND_SME_ZA_HV_idx_dest, /* SME destination ZA tile vector. */
|
||||
AARCH64_OPND_SME_ZA_HV_idx_destxN, /* SME N dest ZA tile vectors. */
|
||||
AARCH64_OPND_SME_Pm, /* SME scalable predicate register, bits [15:13]. */
|
||||
AARCH64_OPND_SME_PNg3, /* Predicate-as-counter register, bits [12:10]. */
|
||||
AARCH64_OPND_SME_list_of_64bit_tiles, /* SME list of ZA tiles. */
|
||||
AARCH64_OPND_SME_ZA_HV_idx_ldstr, /* SME destination ZA tile vector. */
|
||||
AARCH64_OPND_SME_ZA_array_off3_0, /* SME ZA[<Wv>{, #<imm3>}]. */
|
||||
|
||||
@ -667,9 +667,10 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 203:
|
||||
case 209:
|
||||
case 212:
|
||||
case 218:
|
||||
case 219:
|
||||
case 224:
|
||||
case 220:
|
||||
case 221:
|
||||
case 226:
|
||||
case 227:
|
||||
return aarch64_ins_regno (self, info, code, inst, errors);
|
||||
case 15:
|
||||
return aarch64_ins_reg_extended (self, info, code, inst, errors);
|
||||
@ -681,7 +682,7 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 33:
|
||||
case 34:
|
||||
case 35:
|
||||
case 234:
|
||||
case 237:
|
||||
return aarch64_ins_reglane (self, info, code, inst, errors);
|
||||
case 36:
|
||||
return aarch64_ins_reglist (self, info, code, inst, errors);
|
||||
@ -726,10 +727,10 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 192:
|
||||
case 193:
|
||||
case 194:
|
||||
case 225:
|
||||
case 233:
|
||||
case 238:
|
||||
case 239:
|
||||
case 228:
|
||||
case 236:
|
||||
case 241:
|
||||
case 242:
|
||||
return aarch64_ins_imm (self, info, code, inst, errors);
|
||||
case 44:
|
||||
case 45:
|
||||
@ -894,26 +895,29 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 216:
|
||||
case 217:
|
||||
return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
|
||||
case 220:
|
||||
case 218:
|
||||
case 219:
|
||||
return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors);
|
||||
case 222:
|
||||
case 226:
|
||||
return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
|
||||
case 221:
|
||||
case 223:
|
||||
return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
|
||||
case 227:
|
||||
case 228:
|
||||
case 224:
|
||||
case 229:
|
||||
return aarch64_ins_sme_za_array (self, info, code, inst, errors);
|
||||
return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
|
||||
case 223:
|
||||
case 225:
|
||||
return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
|
||||
case 230:
|
||||
return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
|
||||
case 231:
|
||||
return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
|
||||
case 232:
|
||||
return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
|
||||
return aarch64_ins_sme_za_array (self, info, code, inst, errors);
|
||||
case 233:
|
||||
return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
|
||||
case 234:
|
||||
return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
|
||||
case 235:
|
||||
case 236:
|
||||
case 237:
|
||||
return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
|
||||
case 238:
|
||||
case 239:
|
||||
case 240:
|
||||
return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
|
||||
default: assert (0); abort ();
|
||||
}
|
||||
|
||||
@ -96,7 +96,8 @@ aarch64_ins_regno (const aarch64_operand *self, const aarch64_opnd_info *info,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED,
|
||||
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
|
||||
{
|
||||
insert_field (self->fields[0], code, info->reg.regno, 0);
|
||||
int val = info->reg.regno - get_operand_specific_data (self);
|
||||
insert_field (self->fields[0], code, val, 0);
|
||||
return true;
|
||||
}
|
||||
|
||||
@ -1245,6 +1246,26 @@ aarch64_ins_sve_reglist (const aarch64_operand *self,
|
||||
return true;
|
||||
}
|
||||
|
||||
/* Encode a strided register list. The first field holds the top bit
|
||||
(0 or 16) and the second field holds the lower bits. The stride is
|
||||
16 divided by the list length. */
|
||||
bool
|
||||
aarch64_ins_sve_strided_reglist (const aarch64_operand *self,
|
||||
const aarch64_opnd_info *info,
|
||||
aarch64_insn *code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED,
|
||||
aarch64_operand_error *errors
|
||||
ATTRIBUTE_UNUSED)
|
||||
{
|
||||
unsigned int num_regs = get_operand_specific_data (self);
|
||||
unsigned int mask = 16 | (16 / num_regs - 1);
|
||||
unsigned int val = info->reglist.first_regno;
|
||||
assert ((val & mask) == val);
|
||||
insert_field (self->fields[0], code, val >> 4, 0);
|
||||
insert_field (self->fields[1], code, val & 15, 0);
|
||||
return true;
|
||||
}
|
||||
|
||||
/* Encode <pattern>{, MUL #<amount>}. The fields array specifies which
|
||||
fields to use for <pattern>. <amount> - 1 is encoded in the SVE_imm4
|
||||
field. */
|
||||
|
||||
@ -96,6 +96,7 @@ AARCH64_DECL_OPD_INSERTER (ins_sve_index);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_limm_mov);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_quad_index);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_reglist);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_strided_reglist);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_scale);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_shlimm);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_sve_shrimm);
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -279,7 +279,8 @@ aarch64_ext_regno (const aarch64_operand *self, aarch64_opnd_info *info,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED,
|
||||
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
|
||||
{
|
||||
info->reg.regno = extract_field (self->fields[0], code, 0);
|
||||
info->reg.regno = (extract_field (self->fields[0], code, 0)
|
||||
+ get_operand_specific_data (self));
|
||||
return true;
|
||||
}
|
||||
|
||||
@ -2039,6 +2040,24 @@ aarch64_ext_sve_reglist (const aarch64_operand *self,
|
||||
return true;
|
||||
}
|
||||
|
||||
/* Decode a strided register list. The first field holds the top bit
|
||||
(0 or 16) and the second field holds the lower bits. The stride is
|
||||
16 divided by the list length. */
|
||||
bool
|
||||
aarch64_ext_sve_strided_reglist (const aarch64_operand *self,
|
||||
aarch64_opnd_info *info, aarch64_insn code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED,
|
||||
aarch64_operand_error *errors
|
||||
ATTRIBUTE_UNUSED)
|
||||
{
|
||||
unsigned int upper = extract_field (self->fields[0], code, 0);
|
||||
unsigned int lower = extract_field (self->fields[1], code, 0);
|
||||
info->reglist.first_regno = upper * 16 + lower;
|
||||
info->reglist.num_regs = get_operand_specific_data (self);
|
||||
info->reglist.stride = 16 / info->reglist.num_regs;
|
||||
return true;
|
||||
}
|
||||
|
||||
/* Decode <pattern>{, MUL #<amount>}. The fields array specifies which
|
||||
fields to use for <pattern>. <amount> - 1 is encoded in the SVE_imm4
|
||||
field. */
|
||||
|
||||
@ -120,6 +120,7 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_sve_index);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_limm_mov);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_quad_index);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_reglist);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_strided_reglist);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_scale);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_shlimm);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_shrimm);
|
||||
|
||||
@ -242,6 +242,8 @@ const struct aarch64_operand aarch64_operands[] =
|
||||
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zdn4}, "a list of SVE vector registers"},
|
||||
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn2}, "a list of SVE vector registers"},
|
||||
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn4}, "a list of SVE vector registers"},
|
||||
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Ztx2_STRIDED", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZtT, FLD_SME_Zt3}, "a list of SVE vector registers"},
|
||||
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Ztx4_STRIDED", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZtT, FLD_SME_Zt2}, "a list of SVE vector registers"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_2b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_2b}, "an SME ZA tile ZA0-ZA3"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_3b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_3b}, "an SME ZA tile ZA0-ZA7"},
|
||||
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_src", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_22,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_5}, "an SME horizontal or vertical vector access register"},
|
||||
@ -249,6 +251,7 @@ const struct aarch64_operand aarch64_operands[] =
|
||||
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_dest", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_22,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0}, "an SME horizontal or vertical vector access register"},
|
||||
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_destxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_imm3_0}, "an SME horizontal or vertical vector access register"},
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SME_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Pm}, "an SVE predicate register"},
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SME_PNg3", 8 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pg3}, "an SVE predicate-as-counter register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SME_list_of_64bit_tiles", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_zero_mask}, "a list of 64-bit ZA element tiles"},
|
||||
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_ldstr", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_22,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0}, "an SME horizontal or vertical vector access register"},
|
||||
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off3_0", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm3_0}, "ZA array"},
|
||||
|
||||
@ -231,6 +231,9 @@ const aarch64_field fields[] =
|
||||
{ 2, 3 }, /* SME_Zdn4: Z0-Z31, multiple of 4, bits [4:2]. */
|
||||
{ 6, 4 }, /* SME_Zn2: Z0-Z31, multiple of 2, bits [9:6]. */
|
||||
{ 7, 3 }, /* SME_Zn4: Z0-Z31, multiple of 4, bits [9:7]. */
|
||||
{ 4, 1 }, /* SME_ZtT: upper bit of Zt, bit [4]. */
|
||||
{ 0, 3 }, /* SME_Zt3: lower 3 bits of Zt, bits [2:0]. */
|
||||
{ 0, 2 }, /* SME_Zt2: lower 2 bits of Zt, bits [1:0]. */
|
||||
{ 23, 1 }, /* SME_i1: immediate field, bit 23. */
|
||||
{ 22, 2 }, /* SME_size_22: size<1>, size<0> class field, [23:22]. */
|
||||
{ 22, 1 }, /* SME_tszh: immediate and qualifier field, bit 22. */
|
||||
@ -1748,6 +1751,22 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
|
||||
}
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_SME_Ztx2_STRIDED:
|
||||
case AARCH64_OPND_SME_Ztx4_STRIDED:
|
||||
/* 2-register lists have a stride of 8 and 4-register lists
|
||||
have a stride of 4. */
|
||||
num = get_operand_specific_data (&aarch64_operands[type]);
|
||||
if (!check_reglist (opnd, mismatch_detail, idx, num, 16 / num))
|
||||
return 0;
|
||||
num = 16 | (opnd->reglist.stride - 1);
|
||||
if ((opnd->reglist.first_regno & ~num) != 0)
|
||||
{
|
||||
set_other_error (mismatch_detail, idx,
|
||||
_("start register out of range"));
|
||||
return 0;
|
||||
}
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_SVE_ZnxN:
|
||||
case AARCH64_OPND_SVE_ZtxN:
|
||||
num = get_opcode_dependent_value (opcode);
|
||||
@ -1804,11 +1823,24 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_CLASS_PRED_REG:
|
||||
if (opnd->reg.regno >= 8
|
||||
&& get_operand_fields_width (get_operand_from_code (type)) == 3)
|
||||
switch (type)
|
||||
{
|
||||
set_invalid_regno_error (mismatch_detail, idx, "p", 0, 7);
|
||||
return 0;
|
||||
case AARCH64_OPND_SME_PNg3:
|
||||
if (opnd->reg.regno < 8)
|
||||
{
|
||||
set_invalid_regno_error (mismatch_detail, idx, "pn", 8, 15);
|
||||
return 0;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
if (opnd->reg.regno >= 8
|
||||
&& get_operand_fields_width (get_operand_from_code (type)) == 3)
|
||||
{
|
||||
set_invalid_regno_error (mismatch_detail, idx, "p", 0, 7);
|
||||
return 0;
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
@ -3742,9 +3774,15 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
|
||||
case AARCH64_OPND_SVE_PNg4_10:
|
||||
case AARCH64_OPND_SVE_PNn:
|
||||
case AARCH64_OPND_SVE_PNt:
|
||||
case AARCH64_OPND_SME_PNg3:
|
||||
if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
|
||||
snprintf (buf, size, "%s",
|
||||
style_reg (styler, "pn%d", opnd->reg.regno));
|
||||
else if (opnd->qualifier == AARCH64_OPND_QLF_P_Z
|
||||
|| opnd->qualifier == AARCH64_OPND_QLF_P_M)
|
||||
snprintf (buf, size, "%s",
|
||||
style_reg (styler, "pn%d/%s", opnd->reg.regno,
|
||||
aarch64_get_qualifier_name (opnd->qualifier)));
|
||||
else
|
||||
snprintf (buf, size, "%s",
|
||||
style_reg (styler, "pn%d.%s", opnd->reg.regno,
|
||||
@ -3772,6 +3810,8 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
|
||||
case AARCH64_OPND_SME_Zdnx4:
|
||||
case AARCH64_OPND_SME_Znx2:
|
||||
case AARCH64_OPND_SME_Znx4:
|
||||
case AARCH64_OPND_SME_Ztx2_STRIDED:
|
||||
case AARCH64_OPND_SME_Ztx4_STRIDED:
|
||||
print_register_list (buf, size, opnd, "z", styler);
|
||||
break;
|
||||
|
||||
|
||||
@ -59,6 +59,9 @@ enum aarch64_field_kind
|
||||
FLD_SME_Zdn4,
|
||||
FLD_SME_Zn2,
|
||||
FLD_SME_Zn4,
|
||||
FLD_SME_ZtT,
|
||||
FLD_SME_Zt3,
|
||||
FLD_SME_Zt2,
|
||||
FLD_SME_i1,
|
||||
FLD_SME_size_22,
|
||||
FLD_SME_tszh,
|
||||
@ -227,10 +230,10 @@ verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma,
|
||||
value by 2 to get the value
|
||||
of an immediate operand. */
|
||||
#define OPD_F_MAYBE_SP 0x00000010 /* May potentially be SP. */
|
||||
#define OPD_F_OD_MASK 0x000000e0 /* Operand-dependent data. */
|
||||
#define OPD_F_OD_MASK 0x000001e0 /* Operand-dependent data. */
|
||||
#define OPD_F_OD_LSB 5
|
||||
#define OPD_F_NO_ZR 0x00000100 /* ZR index not allowed. */
|
||||
#define OPD_F_SHIFT_BY_4 0x00000200 /* Need to left shift the field
|
||||
#define OPD_F_NO_ZR 0x00000200 /* ZR index not allowed. */
|
||||
#define OPD_F_SHIFT_BY_4 0x00000400 /* Need to left shift the field
|
||||
value by 4 to get the value
|
||||
of an immediate operand. */
|
||||
|
||||
|
||||
@ -5286,6 +5286,70 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
||||
SME_INSN ("psel", 0x25204000, 0xff20c210, sme_psel, 0, OP3 (SVE_PNd, SVE_PNg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0),
|
||||
|
||||
/* SME2 extensions to SME. */
|
||||
SME2_INSN ("ld1b", 0xa0400000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, 0, 0),
|
||||
SME2_INSN ("ld1b", 0xa0408000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BZU, 0, 0),
|
||||
SME2_INSN ("ld1b", 0xa1400000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, 0, 0),
|
||||
SME2_INSN ("ld1b", 0xa1408000, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BZU, 0, 0),
|
||||
SME2_INSN ("ld1b", 0xa0000000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0),
|
||||
SME2_INSN ("ld1b", 0xa0008000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0),
|
||||
SME2_INSN ("ld1b", 0xa1000000, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0),
|
||||
SME2_INSN ("ld1b", 0xa1008000, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0),
|
||||
SME2_INSN ("ld1d", 0xa0406000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DZU, 0, 0),
|
||||
SME2_INSN ("ld1d", 0xa040e000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DZU, 0, 0),
|
||||
SME2_INSN ("ld1d", 0xa1406000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DZU, 0, 0),
|
||||
SME2_INSN ("ld1d", 0xa140e000, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DZU, 0, 0),
|
||||
SME2_INSN ("ld1d", 0xa0006000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0),
|
||||
SME2_INSN ("ld1d", 0xa000e000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0),
|
||||
SME2_INSN ("ld1d", 0xa1006000, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0),
|
||||
SME2_INSN ("ld1d", 0xa100e000, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0),
|
||||
SME2_INSN ("ld1h", 0xa0402000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HZU, 0, 0),
|
||||
SME2_INSN ("ld1h", 0xa040a000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HZU, 0, 0),
|
||||
SME2_INSN ("ld1h", 0xa1402000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HZU, 0, 0),
|
||||
SME2_INSN ("ld1h", 0xa140a000, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HZU, 0, 0),
|
||||
SME2_INSN ("ld1h", 0xa0002000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0),
|
||||
SME2_INSN ("ld1h", 0xa000a000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0),
|
||||
SME2_INSN ("ld1h", 0xa1002000, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0),
|
||||
SME2_INSN ("ld1h", 0xa100a000, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0),
|
||||
SME2_INSN ("ld1w", 0xa0404000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SZU, 0, 0),
|
||||
SME2_INSN ("ld1w", 0xa040c000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SZU, 0, 0),
|
||||
SME2_INSN ("ld1w", 0xa1404000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SZU, 0, 0),
|
||||
SME2_INSN ("ld1w", 0xa140c000, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SZU, 0, 0),
|
||||
SME2_INSN ("ld1w", 0xa0004000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0),
|
||||
SME2_INSN ("ld1w", 0xa000c000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0),
|
||||
SME2_INSN ("ld1w", 0xa1004000, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0),
|
||||
SME2_INSN ("ld1w", 0xa100c000, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0),
|
||||
SME2_INSN ("ldnt1b", 0xa0400001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, 0, 0),
|
||||
SME2_INSN ("ldnt1b", 0xa0408001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BZU, 0, 0),
|
||||
SME2_INSN ("ldnt1b", 0xa1400008, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, 0, 0),
|
||||
SME2_INSN ("ldnt1b", 0xa1408008, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BZU, 0, 0),
|
||||
SME2_INSN ("ldnt1b", 0xa0000001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0),
|
||||
SME2_INSN ("ldnt1b", 0xa0008001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0),
|
||||
SME2_INSN ("ldnt1b", 0xa1000008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0),
|
||||
SME2_INSN ("ldnt1b", 0xa1008008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR), OP_SVE_BZU, 0, 0),
|
||||
SME2_INSN ("ldnt1d", 0xa0406001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DZU, 0, 0),
|
||||
SME2_INSN ("ldnt1d", 0xa040e001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DZU, 0, 0),
|
||||
SME2_INSN ("ldnt1d", 0xa1406008, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DZU, 0, 0),
|
||||
SME2_INSN ("ldnt1d", 0xa140e008, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DZU, 0, 0),
|
||||
SME2_INSN ("ldnt1d", 0xa0006001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0),
|
||||
SME2_INSN ("ldnt1d", 0xa000e001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0),
|
||||
SME2_INSN ("ldnt1d", 0xa1006008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0),
|
||||
SME2_INSN ("ldnt1d", 0xa100e008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, 0, 0),
|
||||
SME2_INSN ("ldnt1h", 0xa0402001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HZU, 0, 0),
|
||||
SME2_INSN ("ldnt1h", 0xa040a001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HZU, 0, 0),
|
||||
SME2_INSN ("ldnt1h", 0xa1402008, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HZU, 0, 0),
|
||||
SME2_INSN ("ldnt1h", 0xa140a008, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HZU, 0, 0),
|
||||
SME2_INSN ("ldnt1h", 0xa0002001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0),
|
||||
SME2_INSN ("ldnt1h", 0xa000a001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0),
|
||||
SME2_INSN ("ldnt1h", 0xa1002008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0),
|
||||
SME2_INSN ("ldnt1h", 0xa100a008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, 0, 0),
|
||||
SME2_INSN ("ldnt1w", 0xa0404001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SZU, 0, 0),
|
||||
SME2_INSN ("ldnt1w", 0xa040c001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SZU, 0, 0),
|
||||
SME2_INSN ("ldnt1w", 0xa1404008, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SZU, 0, 0),
|
||||
SME2_INSN ("ldnt1w", 0xa140c008, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SZU, 0, 0),
|
||||
SME2_INSN ("ldnt1w", 0xa0004001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0),
|
||||
SME2_INSN ("ldnt1w", 0xa000c001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0),
|
||||
SME2_INSN ("ldnt1w", 0xa1004008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0),
|
||||
SME2_INSN ("ldnt1w", 0xa100c008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0),
|
||||
SME2_INSN ("mov", 0xc0060800, 0xffff9f01, sme2_mov, 0, OP2 (SME_Zdnx2, SME_ZA_array_off3_5), OP_SVE_VV_BHSD, F_OD (2), 0),
|
||||
SME2_INSN ("mov", 0xc0060c00, 0xffff9f03, sme2_mov, 0, OP2 (SME_Zdnx4, SME_ZA_array_off3_5), OP_SVE_VV_BHSD, F_OD (4), 0),
|
||||
SME2_INSN ("mov", 0xc0060000, 0xff3f1f01, sme_size_22, 0, OP2 (SME_Zdnx2, SME_ZA_HV_idx_srcxN), OP_SVE_VV_BHSDQ, F_OD (2), 0),
|
||||
@ -5302,6 +5366,70 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
||||
SME2_INSN ("mova", 0xc0040c00, 0xffff9c78, sme2_mov, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VV_BHSD, F_OD (4), 0),
|
||||
SME2_INSN ("mova", 0xc0040000, 0xff3f1c38, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx2), OP_SVE_VV_BHSDQ, F_OD (2), 0),
|
||||
SME2_INSN ("mova", 0xc0040400, 0xff3f1c78, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx4), OP_SVE_VV_BHSDQ, F_OD (4), 0),
|
||||
SME2_INSN ("st1b", 0xa0600000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BUU, 0, 0),
|
||||
SME2_INSN ("st1b", 0xa0608000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BUU, 0, 0),
|
||||
SME2_INSN ("st1b", 0xa1600000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BUU, 0, 0),
|
||||
SME2_INSN ("st1b", 0xa1608000, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BUU, 0, 0),
|
||||
SME2_INSN ("st1b", 0xa0200000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0),
|
||||
SME2_INSN ("st1b", 0xa0208000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0),
|
||||
SME2_INSN ("st1b", 0xa1200000, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0),
|
||||
SME2_INSN ("st1b", 0xa1208000, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0),
|
||||
SME2_INSN ("st1d", 0xa0606000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DUU, 0, 0),
|
||||
SME2_INSN ("st1d", 0xa060e000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DUU, 0, 0),
|
||||
SME2_INSN ("st1d", 0xa1606000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DUU, 0, 0),
|
||||
SME2_INSN ("st1d", 0xa160e000, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DUU, 0, 0),
|
||||
SME2_INSN ("st1d", 0xa0206000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0),
|
||||
SME2_INSN ("st1d", 0xa020e000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0),
|
||||
SME2_INSN ("st1d", 0xa1206000, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0),
|
||||
SME2_INSN ("st1d", 0xa120e000, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0),
|
||||
SME2_INSN ("st1h", 0xa0602000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HUU, 0, 0),
|
||||
SME2_INSN ("st1h", 0xa060a000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HUU, 0, 0),
|
||||
SME2_INSN ("st1h", 0xa1602000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HUU, 0, 0),
|
||||
SME2_INSN ("st1h", 0xa160a000, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HUU, 0, 0),
|
||||
SME2_INSN ("st1h", 0xa0202000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0),
|
||||
SME2_INSN ("st1h", 0xa020a000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0),
|
||||
SME2_INSN ("st1h", 0xa1202000, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0),
|
||||
SME2_INSN ("st1h", 0xa120a000, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0),
|
||||
SME2_INSN ("st1w", 0xa0604000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SUU, 0, 0),
|
||||
SME2_INSN ("st1w", 0xa060c000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SUU, 0, 0),
|
||||
SME2_INSN ("st1w", 0xa1604000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SUU, 0, 0),
|
||||
SME2_INSN ("st1w", 0xa160c000, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SUU, 0, 0),
|
||||
SME2_INSN ("st1w", 0xa0204000, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
|
||||
SME2_INSN ("st1w", 0xa020c000, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
|
||||
SME2_INSN ("st1w", 0xa1204000, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
|
||||
SME2_INSN ("st1w", 0xa120c000, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
|
||||
SME2_INSN ("stnt1b", 0xa0600001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BUU, 0, 0),
|
||||
SME2_INSN ("stnt1b", 0xa0608001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BUU, 0, 0),
|
||||
SME2_INSN ("stnt1b", 0xa1600008, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BUU, 0, 0),
|
||||
SME2_INSN ("stnt1b", 0xa1608008, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BUU, 0, 0),
|
||||
SME2_INSN ("stnt1b", 0xa0200001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0),
|
||||
SME2_INSN ("stnt1b", 0xa0208001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0),
|
||||
SME2_INSN ("stnt1b", 0xa1200008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0),
|
||||
SME2_INSN ("stnt1b", 0xa1208008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR), OP_SVE_BUU, 0, 0),
|
||||
SME2_INSN ("stnt1d", 0xa0606001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DUU, 0, 0),
|
||||
SME2_INSN ("stnt1d", 0xa060e001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DUU, 0, 0),
|
||||
SME2_INSN ("stnt1d", 0xa1606008, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_DUU, 0, 0),
|
||||
SME2_INSN ("stnt1d", 0xa160e008, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_DUU, 0, 0),
|
||||
SME2_INSN ("stnt1d", 0xa0206001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0),
|
||||
SME2_INSN ("stnt1d", 0xa020e001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0),
|
||||
SME2_INSN ("stnt1d", 0xa1206008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0),
|
||||
SME2_INSN ("stnt1d", 0xa120e008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL3), OP_SVE_DUU, 0, 0),
|
||||
SME2_INSN ("stnt1h", 0xa0602001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HUU, 0, 0),
|
||||
SME2_INSN ("stnt1h", 0xa060a001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HUU, 0, 0),
|
||||
SME2_INSN ("stnt1h", 0xa1602008, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_HUU, 0, 0),
|
||||
SME2_INSN ("stnt1h", 0xa160a008, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HUU, 0, 0),
|
||||
SME2_INSN ("stnt1h", 0xa0202001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0),
|
||||
SME2_INSN ("stnt1h", 0xa020a001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0),
|
||||
SME2_INSN ("stnt1h", 0xa1202008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0),
|
||||
SME2_INSN ("stnt1h", 0xa120a008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL1), OP_SVE_HUU, 0, 0),
|
||||
SME2_INSN ("stnt1w", 0xa0604001, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SUU, 0, 0),
|
||||
SME2_INSN ("stnt1w", 0xa060c001, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SUU, 0, 0),
|
||||
SME2_INSN ("stnt1w", 0xa1604008, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_SUU, 0, 0),
|
||||
SME2_INSN ("stnt1w", 0xa160c008, 0xfff0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SUU, 0, 0),
|
||||
SME2_INSN ("stnt1w", 0xa0204001, 0xffe0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
|
||||
SME2_INSN ("stnt1w", 0xa020c001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
|
||||
SME2_INSN ("stnt1w", 0xa1204008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
|
||||
SME2_INSN ("stnt1w", 0xa120c008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
|
||||
|
||||
/* SIMD Dot Product (optional in v8.2-A). */
|
||||
DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),
|
||||
@ -5950,6 +6078,12 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
||||
F(FLD_SME_Zn2), "a list of SVE vector registers") \
|
||||
Y(SVE_REGLIST, sve_aligned_reglist, "SME_Znx4", 4 << OPD_F_OD_LSB, \
|
||||
F(FLD_SME_Zn4), "a list of SVE vector registers") \
|
||||
Y(SVE_REGLIST, sve_strided_reglist, "SME_Ztx2_STRIDED", \
|
||||
2 << OPD_F_OD_LSB, F(FLD_SME_ZtT, FLD_SME_Zt3), \
|
||||
"a list of SVE vector registers") \
|
||||
Y(SVE_REGLIST, sve_strided_reglist, "SME_Ztx4_STRIDED", \
|
||||
4 << OPD_F_OD_LSB, F(FLD_SME_ZtT, FLD_SME_Zt2), \
|
||||
"a list of SVE vector registers") \
|
||||
Y(SVE_REG, regno, "SME_ZAda_2b", 0, F(FLD_SME_ZAda_2b), \
|
||||
"an SME ZA tile ZA0-ZA3") \
|
||||
Y(SVE_REG, regno, "SME_ZAda_3b", 0, F(FLD_SME_ZAda_3b), \
|
||||
@ -5968,6 +6102,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
||||
"an SME horizontal or vertical vector access register") \
|
||||
Y(PRED_REG, regno, "SME_Pm", 0, F(FLD_SME_Pm), \
|
||||
"an SVE predicate register") \
|
||||
Y(PRED_REG, regno, "SME_PNg3", 8 << OPD_F_OD_LSB, F(FLD_SVE_Pg3), \
|
||||
"an SVE predicate-as-counter register") \
|
||||
Y(SVE_REG, imm, "SME_list_of_64bit_tiles", 0, \
|
||||
F(FLD_SME_zero_mask), "a list of 64-bit ZA element tiles") \
|
||||
Y(ZA_ACCESS, sme_za_hv_tiles, "SME_ZA_HV_idx_ldstr", 0, \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user