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[PATCH, BINUTILS, AARCH64, 8/9] Add SCXTNUM_ELx and ID_PFR2_EL1 system registers

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This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
The encodings can be found in the System Register XML.

This patch adds the new system registers SCXTNUM_ELx and ID_PFR2_EL1.

*** include/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_SCXTNUM): New.
	(AARCH64_FEATURE_ID_PFR2): New.
	(AARCH64_ARCH_V8_5): Add both by default.

*** opcodes/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-opc.c (aarch64_sys_regs): New entries for
	scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
	(aarch64_sys_reg_supported_p): New checks for above.

*** gas/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* testsuite/gas/aarch64/sysreg-4.s: Test registers
	scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
	* testsuite/gas/aarch64/sysreg-4.d: Likewise.
	* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
This commit is contained in:
Sudakshina Das 2018-09-26 11:02:28 +01:00 committed by Richard Earnshaw
parent ff6054520c
commit a97330e723
8 changed files with 65 additions and 1 deletions
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7
gas/ChangeLog
View File

@ -1,3 +1,10 @@
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/sysreg-4.s: Test registers
scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
* testsuite/gas/aarch64/sysreg-4.d: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_bti_operand): New.

6
gas/testsuite/gas/aarch64/illegal-sysreg-4.l
View File

@ -8,3 +8,9 @@
[^:]*:[0-9]+: Error: selected processor does not support system register name 'cvadp'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'rndr'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'rndrrs'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'scxtnum_el0'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'scxtnum_el1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'scxtnum_el2'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'scxtnum_el3'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'scxtnum_el12'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'id_pfr2_el1'

6
gas/testsuite/gas/aarch64/sysreg-4.d
View File

@ -13,3 +13,9 @@ Disassembly of section \.text:
.*: d50b7d24 dc cvadp, x4
.*: d53b2405 mrs x5, rndr
.*: d53b2426 mrs x6, rndrrs
.*: d53bd0e7 mrs x7, scxtnum_el0
.*: d538d0e7 mrs x7, scxtnum_el1
.*: d53cd0e7 mrs x7, scxtnum_el2
.*: d53ed0e7 mrs x7, scxtnum_el3
.*: d53dd0e7 mrs x7, scxtnum_el12
.*: d5380388 mrs x8, id_pfr2_el1

6
gas/testsuite/gas/aarch64/sysreg-4.s
View File

@ -6,3 +6,9 @@ func:
dc cvadp, x4
mrs x5, rndr
mrs x6, rndrrs
mrs x7, scxtnum_el0
mrs x7, scxtnum_el1
mrs x7, scxtnum_el2
mrs x7, scxtnum_el3
mrs x7, scxtnum_el12
mrs x8, id_pfr2_el1

6
include/ChangeLog
View File

@ -1,3 +1,9 @@
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_SCXTNUM): New.
(AARCH64_FEATURE_ID_PFR2): New.
(AARCH64_ARCH_V8_5): Add both by default.
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_BTI): New.

9
include/opcode/aarch64.h
View File

@ -78,6 +78,11 @@ typedef uint32_t aarch64_insn;
#define AARCH64_FEATURE_RNG 0x80000000000ULL
/* BTI instructions. */
#define AARCH64_FEATURE_BTI 0x100000000000ULL
/* SCXTNUM_ELx. */
#define AARCH64_FEATURE_SCXTNUM 0x200000000000ULL
/* ID_PFR2 instructions. */
#define AARCH64_FEATURE_ID_PFR2 0x400000000000ULL
/* Architectures are the sum of the base and extensions. */
#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
@ -108,7 +113,9 @@ typedef uint32_t aarch64_insn;
| AARCH64_FEATURE_SB \
| AARCH64_FEATURE_PREDRES \
| AARCH64_FEATURE_CVADP \
| AARCH64_FEATURE_BTI)
| AARCH64_FEATURE_BTI \
| AARCH64_FEATURE_SCXTNUM \
| AARCH64_FEATURE_ID_PFR2)
#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)

6
opcodes/ChangeLog
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@ -1,3 +1,9 @@
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_sys_regs): New entries for
scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
(aarch64_sys_reg_supported_p): New checks for above.
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.

20
opcodes/aarch64-opc.c
View File

@ -3733,6 +3733,7 @@ const aarch64_sys_reg aarch64_sys_regs [] =
{ "id_dfr0_el1", CPENC(3,0,C0,C1,2), F_REG_READ }, /* RO */
{ "id_pfr0_el1", CPENC(3,0,C0,C1,0), F_REG_READ }, /* RO */
{ "id_pfr1_el1", CPENC(3,0,C0,C1,1), F_REG_READ }, /* RO */
{ "id_pfr2_el1", CPENC(3,0,C0,C3,4), F_ARCHEXT | F_REG_READ}, /* RO */
{ "id_afr0_el1", CPENC(3,0,C0,C1,3), F_REG_READ }, /* RO */
{ "id_mmfr0_el1", CPENC(3,0,C0,C1,4), F_REG_READ }, /* RO */
{ "id_mmfr1_el1", CPENC(3,0,C0,C1,5), F_REG_READ }, /* RO */
@ -3869,6 +3870,11 @@ const aarch64_sys_reg aarch64_sys_regs [] =
{ "tpidr_el1", CPENC(3,0,C13,C0,4), 0 },
{ "tpidr_el2", CPENC(3,4,C13,C0,2), 0 },
{ "tpidr_el3", CPENC(3,6,C13,C0,2), 0 },
{ "scxtnum_el0", CPENC(3,3,C13,C0,7), F_ARCHEXT },
{ "scxtnum_el1", CPENC(3,0,C13,C0,7), F_ARCHEXT },
{ "scxtnum_el2", CPENC(3,4,C13,C0,7), F_ARCHEXT },
{ "scxtnum_el12", CPENC(3,5,C13,C0,7), F_ARCHEXT },
{ "scxtnum_el3", CPENC(3,6,C13,C0,7), F_ARCHEXT },
{ "teecr32_el1", CPENC(2,2,C0, C0,0), 0 }, /* See section 3.9.7.1 */
{ "cntfrq_el0", CPENC(3,3,C14,C0,0), 0 }, /* RW */
{ "cntpct_el0", CPENC(3,3,C14,C0,1), F_REG_READ }, /* RO */
@ -4108,6 +4114,20 @@ aarch64_sys_reg_supported_p (const aarch64_feature_set features,
&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN))
return FALSE;
/* SCXTNUM_ELx registers. */
if ((reg->value == CPENC (3, 3, C13, C0, 7)
|| reg->value == CPENC (3, 0, C13, C0, 7)
|| reg->value == CPENC (3, 4, C13, C0, 7)
|| reg->value == CPENC (3, 6, C13, C0, 7)
|| reg->value == CPENC (3, 5, C13, C0, 7))
&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SCXTNUM))
return FALSE;
/* ID_PFR2_EL1 register. */
if (reg->value == CPENC(3, 0, C0, C3, 4)
&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_ID_PFR2))
return FALSE;
/* Virtualization host extensions: system registers. */
if ((reg->value == CPENC (3, 4, C2, C0, 1)
|| reg->value == CPENC (3, 4, C13, C0, 1)