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[cpu]
* m32c.cpu (lde, ste): Add dsp[a0] and [a1a] addressing. (indexb, indexbd, indexbs, indexw, indexwd, indexws, indexl, indexld, indexls): .w variants have `1' bit. (rot32.b): QI, not SI. (rot32.w): HI, not SI. (xchg16): HI for .w variant. [opcodes] * m32c-asm.c: Regenerate. * m32c-desc.c: Regenerate. * m32c-desc.h: Regenerate. * m32c-dis.c: Regenerate. * m32c-ibld.c: Regenerate. * m32c-opc.c: Regenerate. * m32c-opc.h: Regenerate.
This commit is contained in:
DJ Delorie
parent
a0ffed4b33
commit
a1a280bb84
@ -1,3 +1,12 @@
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2005-10-21 DJ Delorie <dj@redhat.com>
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* m32c.cpu (lde, ste): Add dsp[a0] and [a1a] addressing.
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(indexb, indexbd, indexbs, indexw, indexwd, indexws, indexl,
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indexld, indexls): .w variants have `1' bit.
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(rot32.b): QI, not SI.
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(rot32.w): HI, not SI.
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(xchg16): HI for .w variant.
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2005-10-19 Nick Clifton <nickc@redhat.com>
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* m32r.opc (parse_slo16): Fix bad application of previous patch.
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174
cpu/m32c.cpu
174
cpu/m32c.cpu
@ -6702,59 +6702,91 @@
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;-------------------------------------------------------------
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; lde dsp24,dst -- for m16c
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; TODO abs20[a0], [a0a1] for dsp24
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;-------------------------------------------------------------
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(define-pmacro (lde-defn mach dstgroup dsp mode wstr op encoding sem)
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(dni (.sym op mach wstr -dst-dspsp- dstgroup)
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(.str op wstr " " mach "-dsp[sp]-" dstgroup "-" dsp "-" mode)
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((machine mach))
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(.str op wstr " ${" dsp "},${dst" mach "-" dstgroup "-" mode "}")
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encoding
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(sem mode (.sym dst mach - dstgroup - mode) dsp)
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())
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)
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(define-pmacro (lde-dst mode wstr wbit op opc1 opc2 opc3 sem)
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(define-pmacro (lde-dst-dsp mode wstr wbit dstgroup srcdisp)
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(begin
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(lde-defn 16 basic Dsp-16-u20 mode wstr op
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(+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-u20)
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sem)
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(lde-defn 16 16-16 Dsp-32-u20 mode wstr op
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(+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-u20)
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sem)
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(lde-defn 16 16-8 Dsp-24-u20 mode wstr op
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(+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-u20)
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sem)
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(dni (.sym lde wstr - dstgroup -u20)
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(.str "lde" wstr "-" dstgroup "-u20")
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((machine 16))
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(.str "lde" wstr " ${" srcdisp "},${dst16-" dstgroup "-" mode "}")
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(+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x8)
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(.sym dst16- dstgroup - mode) srcdisp)
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(nop)
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())
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(dni (.sym lde wstr - dstgroup -u20a0)
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(.str "lde" wstr "-" dstgroup "-u20a0")
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((machine 16))
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(.str "lde" wstr " ${" srcdisp "}[a0],${dst16-" dstgroup "-" mode "}")
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(+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x9)
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(.sym dst16- dstgroup - mode) srcdisp)
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(nop)
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())
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(dni (.sym lde wstr - dstgroup -a1a0)
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(.str "lde" wstr "-" dstgroup "-a1a0")
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((machine 16))
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(.str "lde" wstr " [a1a0],${dst16-" dstgroup "-" mode "}")
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(+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #xa)
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(.sym dst16- dstgroup - mode))
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(nop)
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())
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)
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)
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(define-pmacro (lde-dst mode wstr wbit)
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(begin
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; like: QI .b 0
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(lde-dst-dsp mode wstr wbit basic Dsp-16-u20)
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(lde-dst-dsp mode wstr wbit 16-8 Dsp-24-u20)
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(lde-dst-dsp mode wstr wbit 16-16 Dsp-32-u20)
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)
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)
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;-------------------------------------------------------------
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; ste src,dsp24 -- for m16c
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; TODO abs20[a0], [a0a1] for dsp24
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; ste dst,dsp24 -- for m16c
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;-------------------------------------------------------------
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(define-pmacro (ste-defn mach dstgroup dsp mode wstr op encoding sem)
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(dni (.sym op mach wstr -dst-dspsp- dstgroup)
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(.str op wstr " " mach "-dsp[sp]-" dstgroup "-" dsp "-" mode)
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((machine mach))
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(.str op wstr " ${dst" mach "-" dstgroup "-" mode "},${" dsp "}")
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encoding
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(sem mode (.sym dst mach - dstgroup - mode) dsp)
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())
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)
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(define-pmacro (ste-dst mode wstr wbit op opc1 opc2 opc3 sem)
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(define-pmacro (ste-dst-dsp mode wstr wbit dstgroup srcdisp)
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(begin
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(ste-defn 16 basic Dsp-16-u20 mode wstr op
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(+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-u20)
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sem)
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(ste-defn 16 16-16 Dsp-32-u20 mode wstr op
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(+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-u20)
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sem)
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(ste-defn 16 16-8 Dsp-24-u20 mode wstr op
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(+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-u20)
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sem)
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(dni (.sym ste wstr - dstgroup -u20)
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(.str "ste" wstr "-" dstgroup "-u20")
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((machine 16))
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(.str "ste" wstr " ${dst16-" dstgroup "-" mode "},${" srcdisp "}")
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(+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x0)
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(.sym dst16- dstgroup - mode) srcdisp)
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(nop)
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())
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(dni (.sym ste wstr - dstgroup -u20a0)
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(.str "ste" wstr "-" dstgroup "-u20a0")
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((machine 16))
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(.str "ste" wstr " ${dst16-" dstgroup "-" mode "},${" srcdisp "}[a0]")
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(+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x1)
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(.sym dst16- dstgroup - mode) srcdisp)
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(nop)
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())
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(dni (.sym ste wstr - dstgroup -a1a0)
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(.str "ste" wstr "-" dstgroup "-a1a0")
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((machine 16))
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(.str "ste" wstr " ${dst16-" dstgroup "-" mode "},[a1a0]")
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(+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x2)
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(.sym dst16- dstgroup - mode))
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(nop)
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())
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)
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)
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(define-pmacro (ste-dst mode wstr wbit)
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(begin
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; like: QI .b 0
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(ste-dst-dsp mode wstr wbit basic Dsp-16-u20)
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(ste-dst-dsp mode wstr wbit 16-8 Dsp-24-u20)
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(ste-dst-dsp mode wstr wbit 16-16 Dsp-32-u20)
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)
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)
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@ -7905,31 +7937,31 @@
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; indexb src (index byte)
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(unary32-defn QI .b 0 indexb #x8 0 #x3 indexb-sem)
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(unary32-defn HI .w 0 indexb #x8 1 #x3 indexb-sem)
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(unary32-defn HI .w 1 indexb #x8 1 #x3 indexb-sem)
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; indexbd src (index byte dest)
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(unary32-defn QI .b 0 indexbd #xA 0 3 indexbd-sem)
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(unary32-defn HI .w 0 indexbd #xA 1 3 indexbd-sem)
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(unary32-defn HI .w 1 indexbd #xA 1 3 indexbd-sem)
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; indexbs src (index byte src)
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(unary32-defn QI .b 0 indexbs #xC 0 3 indexbs-sem)
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(unary32-defn HI .w 0 indexbs #xC 1 3 indexbs-sem)
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(unary32-defn HI .w 1 indexbs #xC 1 3 indexbs-sem)
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; indexl src (index long)
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(unary32-defn QI .b 0 indexl 9 2 3 indexl-sem)
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(unary32-defn HI .w 0 indexl 9 3 3 indexl-sem)
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(unary32-defn HI .w 1 indexl 9 3 3 indexl-sem)
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; indexld src (index long dest)
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(unary32-defn QI .b 0 indexld #xB 2 3 indexld-sem)
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(unary32-defn HI .w 0 indexld #xB 3 3 indexld-sem)
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(unary32-defn HI .w 1 indexld #xB 3 3 indexld-sem)
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; indexls src (index long src)
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(unary32-defn QI .b 0 indexls 9 0 3 indexls-sem)
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(unary32-defn HI .w 0 indexls 9 1 3 indexls-sem)
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(unary32-defn HI .w 1 indexls 9 1 3 indexls-sem)
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; indexw src (index word)
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(unary32-defn QI .b 0 indexw 8 2 3 indexw-sem)
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(unary32-defn HI .w 0 indexw 8 3 3 indexw-sem)
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(unary32-defn HI .w 1 indexw 8 3 3 indexw-sem)
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; indexwd src (index word dest)
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(unary32-defn QI .b 0 indexwd #xA 2 3 indexwd-sem)
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(unary32-defn HI .w 0 indexwd #xA 3 3 indexwd-sem)
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(unary32-defn HI .w 1 indexwd #xA 3 3 indexwd-sem)
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; indexws (index word src)
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(unary32-defn QI .b 0 indexws #xC 2 3 indexws-sem)
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(unary32-defn HI .w 0 indexws #xC 3 3 indexws-sem)
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(unary32-defn HI .w 1 indexws #xC 3 3 indexws-sem)
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;-------------------------------------------------------------
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; jcc - jump on condition
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@ -8450,21 +8482,11 @@
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; ste - store to extra far data area (m16)
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;-------------------------------------------------------------
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; A special variant of mem16 for lde and ste
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(define-pmacro (extra-mem16 mode address)
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(mem mode (and #xfffff address)))
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(lde-dst QI .b 0)
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(lde-dst HI .w 1)
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(define-pmacro (lde-sem mode src1 dst)
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(set mode src1 (extra-mem16 mode dst))
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)
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(lde-dst QI .b 0 lde (f-0-4 #x7) (f-4-3 2) (f-8-4 #x8) lde-sem)
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(lde-dst HI .w 1 lde (f-0-4 #x7) (f-4-3 2) (f-8-4 #x8) lde-sem)
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(define-pmacro (ste-sem mode src1 dst)
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(set (extra-mem16 mode dst) src1)
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)
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(ste-dst QI .b 0 ste (f-0-4 #x7) (f-4-3 2) (f-8-4 #x0) ste-sem)
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(ste-dst HI .w 1 ste (f-0-4 #x7) (f-4-3 2) (f-8-4 #x0) ste-sem)
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(ste-dst QI .b 0)
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(ste-dst HI .w 1)
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;-------------------------------------------------------------
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; ldipl - load interrupt permission level
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@ -9481,9 +9503,9 @@
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; rot.BW src,dst
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(dni rot16.b-dst "rot r1h,dest" ((machine 16))
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("rot.b r1h,${dst16-16-HI}")
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(+ (f-0-4 7) (f-4-4 #x4) (f-8-4 #x6) dst16-16-HI)
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(rot-2-sem QI dst16-16-HI)
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("rot.b r1h,${dst16-16-QI}")
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(+ (f-0-4 7) (f-4-4 #x4) (f-8-4 #x6) dst16-16-QI)
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(rot-2-sem QI dst16-16-QI)
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())
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(dni rot16.w-dst "rot r1h,dest" ((machine 16))
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("rot.w r1h,${dst16-16-HI}")
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@ -9492,14 +9514,14 @@
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())
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(dni rot32.b-dst "rot r1h,dest" ((machine 32))
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("rot.b r1h,${dst32-16-Unprefixed-SI}")
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(+ (f-0-4 #xA) dst32-16-Unprefixed-SI (f-7-1 0) (f-10-2 3) (f-12-4 #xF))
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(rot-2-sem QI dst32-16-Unprefixed-SI)
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("rot.b r1h,${dst32-16-Unprefixed-QI}")
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(+ (f-0-4 #xA) dst32-16-Unprefixed-QI (f-7-1 0) (f-10-2 3) (f-12-4 #xF))
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(rot-2-sem QI dst32-16-Unprefixed-QI)
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())
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(dni rot32.w-dst "rot r1h,dest" ((machine 32))
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("rot.w r1h,${dst32-16-Unprefixed-SI}")
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(+ (f-0-4 #xA) dst32-16-Unprefixed-SI (f-7-1 1) (f-10-2 3) (f-12-4 #xF))
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(rot-2-sem HI dst32-16-Unprefixed-SI)
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("rot.w r1h,${dst32-16-Unprefixed-HI}")
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(+ (f-0-4 #xA) dst32-16-Unprefixed-HI (f-7-1 1) (f-10-2 3) (f-12-4 #xF))
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(rot-2-sem HI dst32-16-Unprefixed-HI)
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())
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;-------------------------------------------------------------
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@ -10215,7 +10237,7 @@
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(xchg16-defn QI b 0 1 r0h)
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(xchg16-defn QI b 0 2 r1l)
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(xchg16-defn QI b 0 3 r1h)
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(xchg16-defn QI w 1 0 r0)
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(xchg16-defn HI w 1 0 r0)
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(xchg16-defn HI w 1 1 r1)
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(xchg16-defn HI w 1 2 r2)
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(xchg16-defn HI w 1 3 r3)
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@ -1,3 +1,13 @@
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2005-10-21 DJ Delorie <dj@redhat.com>
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* m32c-asm.c: Regenerate.
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* m32c-desc.c: Regenerate.
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* m32c-desc.h: Regenerate.
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* m32c-dis.c: Regenerate.
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* m32c-ibld.c: Regenerate.
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* m32c-opc.c: Regenerate.
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* m32c-opc.h: Regenerate.
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2005-10-21 Nick Clifton <nickc@redhat.com>
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* bfin-dis.c: Tidy up code, removing redundant constructs.
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@ -879,6 +879,9 @@ m32c_cgen_parse_operand (CGEN_CPU_DESC cd,
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case M32C_OPERAND_A1 :
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errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_a1, & junk);
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break;
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case M32C_OPERAND_A1A0 :
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errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_SI, & junk);
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break;
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case M32C_OPERAND_AN16_PUSH_S :
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errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_HI, & fields->f_4_1);
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break;
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@ -1422,6 +1422,10 @@ const CGEN_OPERAND m32c_cgen_operand_table[] =
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{ "A1", M32C_OPERAND_A1, HW_H_A1, 0, 0,
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{ 0, { (const PTR) 0 } },
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{ 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
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/* A1A0: a1a0 */
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{ "A1A0", M32C_OPERAND_A1A0, HW_H_AR_SI, 0, 0,
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{ 0, { (const PTR) 0 } },
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{ 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
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/* sb: SB register */
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{ "sb", M32C_OPERAND_SB, HW_H_SB, 0, 0,
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{ 0, { (const PTR) 0 } },
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@ -2042,6 +2046,24 @@ const CGEN_OPERAND m32c_cgen_operand_table[] =
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/* src32-24-8-An-relative-Prefixed-SI: m32c dsp:8[An] relative destination SI */
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/* src32-24-16-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
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/* src32-24-24-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
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/* dsp20-16-u20-QI: m16c dsp:20 absolute destination QI */
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/* dsp20-16-u20-A0-QI: m16c dsp:20[A0] relative destination QI */
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/* dsp20-16-A1A0-QI: m16c [A1A0] relative destination QI */
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/* dsp20-24-u20-QI: m16c dsp:20 absolute destination QI */
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/* dsp20-24-u20-A0-QI: m16c dsp:20[A0] relative destination QI */
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/* dsp20-24-A1A0-QI: m16c [A1A0] relative destination QI */
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/* dsp20-32-u20-QI: m16c dsp:20 absolute destination QI */
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/* dsp20-32-u20-A0-QI: m16c dsp:20[A0] relative destination QI */
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/* dsp20-32-A1A0-QI: m16c [A1A0] relative destination QI */
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/* dsp20-16-u20-HI: m16c dsp:20 absolute destination HI */
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/* dsp20-16-u20-A0-HI: m16c dsp:20[A0] relative destination HI */
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/* dsp20-16-A1A0-HI: m16c [A1A0] relative destination HI */
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/* dsp20-24-u20-HI: m16c dsp:20 absolute destination HI */
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/* dsp20-24-u20-A0-HI: m16c dsp:20[A0] relative destination HI */
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/* dsp20-24-A1A0-HI: m16c [A1A0] relative destination HI */
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/* dsp20-32-u20-HI: m16c dsp:20 absolute destination HI */
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/* dsp20-32-u20-A0-HI: m16c dsp:20[A0] relative destination HI */
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/* dsp20-32-A1A0-HI: m16c [A1A0] relative destination HI */
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/* src16-16-16-absolute-QI: m16c absolute address QI */
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/* src16-16-16-absolute-HI: m16c absolute address HI */
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/* src32-16-16-absolute-Unprefixed-QI: m32c absolute address QI */
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@ -7452,49 +7474,49 @@ static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] =
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M32C_INSN_XCHG16W_R1_DST16_16_16_ABSOLUTE_HI, "xchg16w-r1-dst16-16-16-absolute-HI", "xchg.w", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* xchg.w r0,$Dst16RnQI */
|
||||
/* xchg.w r0,$Dst16RnHI */
|
||||
{
|
||||
M32C_INSN_XCHG16W_R0_DST16_RN_DIRECT_QI, "xchg16w-r0-dst16-Rn-direct-QI", "xchg.w", 16,
|
||||
M32C_INSN_XCHG16W_R0_DST16_RN_DIRECT_HI, "xchg16w-r0-dst16-Rn-direct-HI", "xchg.w", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* xchg.w r0,$Dst16AnQI */
|
||||
/* xchg.w r0,$Dst16AnHI */
|
||||
{
|
||||
M32C_INSN_XCHG16W_R0_DST16_AN_DIRECT_QI, "xchg16w-r0-dst16-An-direct-QI", "xchg.w", 16,
|
||||
M32C_INSN_XCHG16W_R0_DST16_AN_DIRECT_HI, "xchg16w-r0-dst16-An-direct-HI", "xchg.w", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* xchg.w r0,[$Dst16An] */
|
||||
{
|
||||
M32C_INSN_XCHG16W_R0_DST16_AN_INDIRECT_QI, "xchg16w-r0-dst16-An-indirect-QI", "xchg.w", 16,
|
||||
M32C_INSN_XCHG16W_R0_DST16_AN_INDIRECT_HI, "xchg16w-r0-dst16-An-indirect-HI", "xchg.w", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* xchg.w r0,${Dsp-16-u8}[$Dst16An] */
|
||||
{
|
||||
M32C_INSN_XCHG16W_R0_DST16_16_8_AN_RELATIVE_QI, "xchg16w-r0-dst16-16-8-An-relative-QI", "xchg.w", 24,
|
||||
M32C_INSN_XCHG16W_R0_DST16_16_8_AN_RELATIVE_HI, "xchg16w-r0-dst16-16-8-An-relative-HI", "xchg.w", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* xchg.w r0,${Dsp-16-u16}[$Dst16An] */
|
||||
{
|
||||
M32C_INSN_XCHG16W_R0_DST16_16_16_AN_RELATIVE_QI, "xchg16w-r0-dst16-16-16-An-relative-QI", "xchg.w", 32,
|
||||
M32C_INSN_XCHG16W_R0_DST16_16_16_AN_RELATIVE_HI, "xchg16w-r0-dst16-16-16-An-relative-HI", "xchg.w", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* xchg.w r0,${Dsp-16-u8}[sb] */
|
||||
{
|
||||
M32C_INSN_XCHG16W_R0_DST16_16_8_SB_RELATIVE_QI, "xchg16w-r0-dst16-16-8-SB-relative-QI", "xchg.w", 24,
|
||||
M32C_INSN_XCHG16W_R0_DST16_16_8_SB_RELATIVE_HI, "xchg16w-r0-dst16-16-8-SB-relative-HI", "xchg.w", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* xchg.w r0,${Dsp-16-u16}[sb] */
|
||||
{
|
||||
M32C_INSN_XCHG16W_R0_DST16_16_16_SB_RELATIVE_QI, "xchg16w-r0-dst16-16-16-SB-relative-QI", "xchg.w", 32,
|
||||
M32C_INSN_XCHG16W_R0_DST16_16_16_SB_RELATIVE_HI, "xchg16w-r0-dst16-16-16-SB-relative-HI", "xchg.w", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* xchg.w r0,${Dsp-16-s8}[fb] */
|
||||
{
|
||||
M32C_INSN_XCHG16W_R0_DST16_16_8_FB_RELATIVE_QI, "xchg16w-r0-dst16-16-8-FB-relative-QI", "xchg.w", 24,
|
||||
M32C_INSN_XCHG16W_R0_DST16_16_8_FB_RELATIVE_HI, "xchg16w-r0-dst16-16-8-FB-relative-HI", "xchg.w", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* xchg.w r0,${Dsp-16-u16} */
|
||||
{
|
||||
M32C_INSN_XCHG16W_R0_DST16_16_16_ABSOLUTE_QI, "xchg16w-r0-dst16-16-16-absolute-QI", "xchg.w", 32,
|
||||
M32C_INSN_XCHG16W_R0_DST16_16_16_ABSOLUTE_HI, "xchg16w-r0-dst16-16-16-absolute-HI", "xchg.w", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* xchg.b r1h,$Dst16RnQI */
|
||||
@ -15297,124 +15319,124 @@ static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] =
|
||||
M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "sbb16.b-imm-G-16-16-dst16-16-16-absolute-QI", "sbb.b", 40,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* rot.w r1h,$Dst32RnUnprefixedSI */
|
||||
/* rot.w r1h,$Dst32RnUnprefixedHI */
|
||||
{
|
||||
M32C_INSN_ROT32_W_DST_DST32_RN_DIRECT_UNPREFIXED_SI, "rot32.w-dst-dst32-Rn-direct-Unprefixed-SI", "rot.w", 16,
|
||||
M32C_INSN_ROT32_W_DST_DST32_RN_DIRECT_UNPREFIXED_HI, "rot32.w-dst-dst32-Rn-direct-Unprefixed-HI", "rot.w", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* rot.w r1h,$Dst32AnUnprefixedSI */
|
||||
/* rot.w r1h,$Dst32AnUnprefixedHI */
|
||||
{
|
||||
M32C_INSN_ROT32_W_DST_DST32_AN_DIRECT_UNPREFIXED_SI, "rot32.w-dst-dst32-An-direct-Unprefixed-SI", "rot.w", 16,
|
||||
M32C_INSN_ROT32_W_DST_DST32_AN_DIRECT_UNPREFIXED_HI, "rot32.w-dst-dst32-An-direct-Unprefixed-HI", "rot.w", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* rot.w r1h,[$Dst32AnUnprefixed] */
|
||||
{
|
||||
M32C_INSN_ROT32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_SI, "rot32.w-dst-dst32-An-indirect-Unprefixed-SI", "rot.w", 16,
|
||||
M32C_INSN_ROT32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_HI, "rot32.w-dst-dst32-An-indirect-Unprefixed-HI", "rot.w", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* rot.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
||||
{
|
||||
M32C_INSN_ROT32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "rot32.w-dst-dst32-16-8-An-relative-Unprefixed-SI", "rot.w", 24,
|
||||
M32C_INSN_ROT32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-8-An-relative-Unprefixed-HI", "rot.w", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* rot.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
||||
{
|
||||
M32C_INSN_ROT32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "rot32.w-dst-dst32-16-16-An-relative-Unprefixed-SI", "rot.w", 32,
|
||||
M32C_INSN_ROT32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-16-An-relative-Unprefixed-HI", "rot.w", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* rot.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
||||
{
|
||||
M32C_INSN_ROT32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "rot32.w-dst-dst32-16-24-An-relative-Unprefixed-SI", "rot.w", 40,
|
||||
M32C_INSN_ROT32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-24-An-relative-Unprefixed-HI", "rot.w", 40,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* rot.w r1h,${Dsp-16-u8}[sb] */
|
||||
{
|
||||
M32C_INSN_ROT32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "rot32.w-dst-dst32-16-8-SB-relative-Unprefixed-SI", "rot.w", 24,
|
||||
M32C_INSN_ROT32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-8-SB-relative-Unprefixed-HI", "rot.w", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* rot.w r1h,${Dsp-16-u16}[sb] */
|
||||
{
|
||||
M32C_INSN_ROT32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "rot32.w-dst-dst32-16-16-SB-relative-Unprefixed-SI", "rot.w", 32,
|
||||
M32C_INSN_ROT32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-16-SB-relative-Unprefixed-HI", "rot.w", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* rot.w r1h,${Dsp-16-s8}[fb] */
|
||||
{
|
||||
M32C_INSN_ROT32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "rot32.w-dst-dst32-16-8-FB-relative-Unprefixed-SI", "rot.w", 24,
|
||||
M32C_INSN_ROT32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-8-FB-relative-Unprefixed-HI", "rot.w", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* rot.w r1h,${Dsp-16-s16}[fb] */
|
||||
{
|
||||
M32C_INSN_ROT32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "rot32.w-dst-dst32-16-16-FB-relative-Unprefixed-SI", "rot.w", 32,
|
||||
M32C_INSN_ROT32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-16-FB-relative-Unprefixed-HI", "rot.w", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* rot.w r1h,${Dsp-16-u16} */
|
||||
{
|
||||
M32C_INSN_ROT32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "rot32.w-dst-dst32-16-16-absolute-Unprefixed-SI", "rot.w", 32,
|
||||
M32C_INSN_ROT32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-16-absolute-Unprefixed-HI", "rot.w", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* rot.w r1h,${Dsp-16-u24} */
|
||||
{
|
||||
M32C_INSN_ROT32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "rot32.w-dst-dst32-16-24-absolute-Unprefixed-SI", "rot.w", 40,
|
||||
M32C_INSN_ROT32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-24-absolute-Unprefixed-HI", "rot.w", 40,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* rot.b r1h,$Dst32RnUnprefixedSI */
|
||||
/* rot.b r1h,$Dst32RnUnprefixedQI */
|
||||
{
|
||||
M32C_INSN_ROT32_B_DST_DST32_RN_DIRECT_UNPREFIXED_SI, "rot32.b-dst-dst32-Rn-direct-Unprefixed-SI", "rot.b", 16,
|
||||
M32C_INSN_ROT32_B_DST_DST32_RN_DIRECT_UNPREFIXED_QI, "rot32.b-dst-dst32-Rn-direct-Unprefixed-QI", "rot.b", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* rot.b r1h,$Dst32AnUnprefixedSI */
|
||||
/* rot.b r1h,$Dst32AnUnprefixedQI */
|
||||
{
|
||||
M32C_INSN_ROT32_B_DST_DST32_AN_DIRECT_UNPREFIXED_SI, "rot32.b-dst-dst32-An-direct-Unprefixed-SI", "rot.b", 16,
|
||||
M32C_INSN_ROT32_B_DST_DST32_AN_DIRECT_UNPREFIXED_QI, "rot32.b-dst-dst32-An-direct-Unprefixed-QI", "rot.b", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* rot.b r1h,[$Dst32AnUnprefixed] */
|
||||
{
|
||||
M32C_INSN_ROT32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_SI, "rot32.b-dst-dst32-An-indirect-Unprefixed-SI", "rot.b", 16,
|
||||
M32C_INSN_ROT32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_QI, "rot32.b-dst-dst32-An-indirect-Unprefixed-QI", "rot.b", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* rot.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
|
||||
{
|
||||
M32C_INSN_ROT32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "rot32.b-dst-dst32-16-8-An-relative-Unprefixed-SI", "rot.b", 24,
|
||||
M32C_INSN_ROT32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-8-An-relative-Unprefixed-QI", "rot.b", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* rot.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
|
||||
{
|
||||
M32C_INSN_ROT32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "rot32.b-dst-dst32-16-16-An-relative-Unprefixed-SI", "rot.b", 32,
|
||||
M32C_INSN_ROT32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-16-An-relative-Unprefixed-QI", "rot.b", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* rot.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
|
||||
{
|
||||
M32C_INSN_ROT32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "rot32.b-dst-dst32-16-24-An-relative-Unprefixed-SI", "rot.b", 40,
|
||||
M32C_INSN_ROT32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-24-An-relative-Unprefixed-QI", "rot.b", 40,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* rot.b r1h,${Dsp-16-u8}[sb] */
|
||||
{
|
||||
M32C_INSN_ROT32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "rot32.b-dst-dst32-16-8-SB-relative-Unprefixed-SI", "rot.b", 24,
|
||||
M32C_INSN_ROT32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-8-SB-relative-Unprefixed-QI", "rot.b", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* rot.b r1h,${Dsp-16-u16}[sb] */
|
||||
{
|
||||
M32C_INSN_ROT32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "rot32.b-dst-dst32-16-16-SB-relative-Unprefixed-SI", "rot.b", 32,
|
||||
M32C_INSN_ROT32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-16-SB-relative-Unprefixed-QI", "rot.b", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* rot.b r1h,${Dsp-16-s8}[fb] */
|
||||
{
|
||||
M32C_INSN_ROT32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "rot32.b-dst-dst32-16-8-FB-relative-Unprefixed-SI", "rot.b", 24,
|
||||
M32C_INSN_ROT32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-8-FB-relative-Unprefixed-QI", "rot.b", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* rot.b r1h,${Dsp-16-s16}[fb] */
|
||||
{
|
||||
M32C_INSN_ROT32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "rot32.b-dst-dst32-16-16-FB-relative-Unprefixed-SI", "rot.b", 32,
|
||||
M32C_INSN_ROT32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-16-FB-relative-Unprefixed-QI", "rot.b", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* rot.b r1h,${Dsp-16-u16} */
|
||||
{
|
||||
M32C_INSN_ROT32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "rot32.b-dst-dst32-16-16-absolute-Unprefixed-SI", "rot.b", 32,
|
||||
M32C_INSN_ROT32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-16-absolute-Unprefixed-QI", "rot.b", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* rot.b r1h,${Dsp-16-u24} */
|
||||
{
|
||||
M32C_INSN_ROT32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "rot32.b-dst-dst32-16-24-absolute-Unprefixed-SI", "rot.b", 40,
|
||||
M32C_INSN_ROT32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-24-absolute-Unprefixed-QI", "rot.b", 40,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* rot.w r1h,$Dst16RnHI */
|
||||
@ -15462,49 +15484,49 @@ static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] =
|
||||
M32C_INSN_ROT16_W_DST_DST16_16_16_ABSOLUTE_HI, "rot16.w-dst-dst16-16-16-absolute-HI", "rot.w", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* rot.b r1h,$Dst16RnHI */
|
||||
/* rot.b r1h,$Dst16RnQI */
|
||||
{
|
||||
M32C_INSN_ROT16_B_DST_DST16_RN_DIRECT_HI, "rot16.b-dst-dst16-Rn-direct-HI", "rot.b", 16,
|
||||
M32C_INSN_ROT16_B_DST_DST16_RN_DIRECT_QI, "rot16.b-dst-dst16-Rn-direct-QI", "rot.b", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* rot.b r1h,$Dst16AnHI */
|
||||
/* rot.b r1h,$Dst16AnQI */
|
||||
{
|
||||
M32C_INSN_ROT16_B_DST_DST16_AN_DIRECT_HI, "rot16.b-dst-dst16-An-direct-HI", "rot.b", 16,
|
||||
M32C_INSN_ROT16_B_DST_DST16_AN_DIRECT_QI, "rot16.b-dst-dst16-An-direct-QI", "rot.b", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* rot.b r1h,[$Dst16An] */
|
||||
{
|
||||
M32C_INSN_ROT16_B_DST_DST16_AN_INDIRECT_HI, "rot16.b-dst-dst16-An-indirect-HI", "rot.b", 16,
|
||||
M32C_INSN_ROT16_B_DST_DST16_AN_INDIRECT_QI, "rot16.b-dst-dst16-An-indirect-QI", "rot.b", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* rot.b r1h,${Dsp-16-u8}[$Dst16An] */
|
||||
{
|
||||
M32C_INSN_ROT16_B_DST_DST16_16_8_AN_RELATIVE_HI, "rot16.b-dst-dst16-16-8-An-relative-HI", "rot.b", 24,
|
||||
M32C_INSN_ROT16_B_DST_DST16_16_8_AN_RELATIVE_QI, "rot16.b-dst-dst16-16-8-An-relative-QI", "rot.b", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* rot.b r1h,${Dsp-16-u16}[$Dst16An] */
|
||||
{
|
||||
M32C_INSN_ROT16_B_DST_DST16_16_16_AN_RELATIVE_HI, "rot16.b-dst-dst16-16-16-An-relative-HI", "rot.b", 32,
|
||||
M32C_INSN_ROT16_B_DST_DST16_16_16_AN_RELATIVE_QI, "rot16.b-dst-dst16-16-16-An-relative-QI", "rot.b", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* rot.b r1h,${Dsp-16-u8}[sb] */
|
||||
{
|
||||
M32C_INSN_ROT16_B_DST_DST16_16_8_SB_RELATIVE_HI, "rot16.b-dst-dst16-16-8-SB-relative-HI", "rot.b", 24,
|
||||
M32C_INSN_ROT16_B_DST_DST16_16_8_SB_RELATIVE_QI, "rot16.b-dst-dst16-16-8-SB-relative-QI", "rot.b", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* rot.b r1h,${Dsp-16-u16}[sb] */
|
||||
{
|
||||
M32C_INSN_ROT16_B_DST_DST16_16_16_SB_RELATIVE_HI, "rot16.b-dst-dst16-16-16-SB-relative-HI", "rot.b", 32,
|
||||
M32C_INSN_ROT16_B_DST_DST16_16_16_SB_RELATIVE_QI, "rot16.b-dst-dst16-16-16-SB-relative-QI", "rot.b", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* rot.b r1h,${Dsp-16-s8}[fb] */
|
||||
{
|
||||
M32C_INSN_ROT16_B_DST_DST16_16_8_FB_RELATIVE_HI, "rot16.b-dst-dst16-16-8-FB-relative-HI", "rot.b", 24,
|
||||
M32C_INSN_ROT16_B_DST_DST16_16_8_FB_RELATIVE_QI, "rot16.b-dst-dst16-16-8-FB-relative-QI", "rot.b", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* rot.b r1h,${Dsp-16-u16} */
|
||||
{
|
||||
M32C_INSN_ROT16_B_DST_DST16_16_16_ABSOLUTE_HI, "rot16.b-dst-dst16-16-16-absolute-HI", "rot.b", 32,
|
||||
M32C_INSN_ROT16_B_DST_DST16_16_16_ABSOLUTE_QI, "rot16.b-dst-dst16-16-16-absolute-QI", "rot.b", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* rot.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */
|
||||
@ -33257,184 +33279,544 @@ static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] =
|
||||
M32C_INSN_MAX32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "max32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "max.b", 56,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
|
||||
},
|
||||
/* ste.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */
|
||||
/* ste.w ${Dsp-16-u16}[$Dst16An],[a1a0] */
|
||||
{
|
||||
M32C_INSN_STE16_W_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_HI, "ste16.w-dst-dspsp-16-8-dst16-16-8-An-relative-HI", "ste.w", 48,
|
||||
M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_AN_RELATIVE_HI, "ste.w-16-16-a1a0-dst16-16-16-An-relative-HI", "ste.w", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.w ${Dsp-16-u8}[sb],${Dsp-24-u20} */
|
||||
/* ste.w ${Dsp-16-u16}[sb],[a1a0] */
|
||||
{
|
||||
M32C_INSN_STE16_W_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_HI, "ste16.w-dst-dspsp-16-8-dst16-16-8-SB-relative-HI", "ste.w", 48,
|
||||
M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_SB_RELATIVE_HI, "ste.w-16-16-a1a0-dst16-16-16-SB-relative-HI", "ste.w", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.w ${Dsp-16-s8}[fb],${Dsp-24-u20} */
|
||||
/* ste.w ${Dsp-16-u16},[a1a0] */
|
||||
{
|
||||
M32C_INSN_STE16_W_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_HI, "ste16.w-dst-dspsp-16-8-dst16-16-8-FB-relative-HI", "ste.w", 48,
|
||||
M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_ABSOLUTE_HI, "ste.w-16-16-a1a0-dst16-16-16-absolute-HI", "ste.w", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.w ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20}[a0] */
|
||||
{
|
||||
M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_AN_RELATIVE_HI, "ste.w-16-16-u20a0-dst16-16-16-An-relative-HI", "ste.w", 56,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.w ${Dsp-16-u16}[sb],${Dsp-32-u20}[a0] */
|
||||
{
|
||||
M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_SB_RELATIVE_HI, "ste.w-16-16-u20a0-dst16-16-16-SB-relative-HI", "ste.w", 56,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.w ${Dsp-16-u16},${Dsp-32-u20}[a0] */
|
||||
{
|
||||
M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_ABSOLUTE_HI, "ste.w-16-16-u20a0-dst16-16-16-absolute-HI", "ste.w", 56,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.w ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20} */
|
||||
{
|
||||
M32C_INSN_STE16_W_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_HI, "ste16.w-dst-dspsp-16-16-dst16-16-16-An-relative-HI", "ste.w", 56,
|
||||
M32C_INSN_STE_W_16_16_U20_DST16_16_16_AN_RELATIVE_HI, "ste.w-16-16-u20-dst16-16-16-An-relative-HI", "ste.w", 56,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.w ${Dsp-16-u16}[sb],${Dsp-32-u20} */
|
||||
{
|
||||
M32C_INSN_STE16_W_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_HI, "ste16.w-dst-dspsp-16-16-dst16-16-16-SB-relative-HI", "ste.w", 56,
|
||||
M32C_INSN_STE_W_16_16_U20_DST16_16_16_SB_RELATIVE_HI, "ste.w-16-16-u20-dst16-16-16-SB-relative-HI", "ste.w", 56,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.w ${Dsp-16-u16},${Dsp-32-u20} */
|
||||
{
|
||||
M32C_INSN_STE16_W_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_HI, "ste16.w-dst-dspsp-16-16-dst16-16-16-absolute-HI", "ste.w", 56,
|
||||
M32C_INSN_STE_W_16_16_U20_DST16_16_16_ABSOLUTE_HI, "ste.w-16-16-u20-dst16-16-16-absolute-HI", "ste.w", 56,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.w ${Dsp-16-u8}[$Dst16An],[a1a0] */
|
||||
{
|
||||
M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_AN_RELATIVE_HI, "ste.w-16-8-a1a0-dst16-16-8-An-relative-HI", "ste.w", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.w ${Dsp-16-u8}[sb],[a1a0] */
|
||||
{
|
||||
M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_SB_RELATIVE_HI, "ste.w-16-8-a1a0-dst16-16-8-SB-relative-HI", "ste.w", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.w ${Dsp-16-s8}[fb],[a1a0] */
|
||||
{
|
||||
M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_FB_RELATIVE_HI, "ste.w-16-8-a1a0-dst16-16-8-FB-relative-HI", "ste.w", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20}[a0] */
|
||||
{
|
||||
M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_AN_RELATIVE_HI, "ste.w-16-8-u20a0-dst16-16-8-An-relative-HI", "ste.w", 48,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.w ${Dsp-16-u8}[sb],${Dsp-24-u20}[a0] */
|
||||
{
|
||||
M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_SB_RELATIVE_HI, "ste.w-16-8-u20a0-dst16-16-8-SB-relative-HI", "ste.w", 48,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.w ${Dsp-16-s8}[fb],${Dsp-24-u20}[a0] */
|
||||
{
|
||||
M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_FB_RELATIVE_HI, "ste.w-16-8-u20a0-dst16-16-8-FB-relative-HI", "ste.w", 48,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */
|
||||
{
|
||||
M32C_INSN_STE_W_16_8_U20_DST16_16_8_AN_RELATIVE_HI, "ste.w-16-8-u20-dst16-16-8-An-relative-HI", "ste.w", 48,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.w ${Dsp-16-u8}[sb],${Dsp-24-u20} */
|
||||
{
|
||||
M32C_INSN_STE_W_16_8_U20_DST16_16_8_SB_RELATIVE_HI, "ste.w-16-8-u20-dst16-16-8-SB-relative-HI", "ste.w", 48,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.w ${Dsp-16-s8}[fb],${Dsp-24-u20} */
|
||||
{
|
||||
M32C_INSN_STE_W_16_8_U20_DST16_16_8_FB_RELATIVE_HI, "ste.w-16-8-u20-dst16-16-8-FB-relative-HI", "ste.w", 48,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.w $Dst16RnHI,[a1a0] */
|
||||
{
|
||||
M32C_INSN_STE_W_BASIC_A1A0_DST16_RN_DIRECT_HI, "ste.w-basic-a1a0-dst16-Rn-direct-HI", "ste.w", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.w $Dst16AnHI,[a1a0] */
|
||||
{
|
||||
M32C_INSN_STE_W_BASIC_A1A0_DST16_AN_DIRECT_HI, "ste.w-basic-a1a0-dst16-An-direct-HI", "ste.w", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.w [$Dst16An],[a1a0] */
|
||||
{
|
||||
M32C_INSN_STE_W_BASIC_A1A0_DST16_AN_INDIRECT_HI, "ste.w-basic-a1a0-dst16-An-indirect-HI", "ste.w", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.w $Dst16RnHI,${Dsp-16-u20}[a0] */
|
||||
{
|
||||
M32C_INSN_STE_W_BASIC_U20A0_DST16_RN_DIRECT_HI, "ste.w-basic-u20a0-dst16-Rn-direct-HI", "ste.w", 40,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.w $Dst16AnHI,${Dsp-16-u20}[a0] */
|
||||
{
|
||||
M32C_INSN_STE_W_BASIC_U20A0_DST16_AN_DIRECT_HI, "ste.w-basic-u20a0-dst16-An-direct-HI", "ste.w", 40,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.w [$Dst16An],${Dsp-16-u20}[a0] */
|
||||
{
|
||||
M32C_INSN_STE_W_BASIC_U20A0_DST16_AN_INDIRECT_HI, "ste.w-basic-u20a0-dst16-An-indirect-HI", "ste.w", 40,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.w $Dst16RnHI,${Dsp-16-u20} */
|
||||
{
|
||||
M32C_INSN_STE16_W_DST_DSPSP_BASIC_DST16_RN_DIRECT_HI, "ste16.w-dst-dspsp-basic-dst16-Rn-direct-HI", "ste.w", 40,
|
||||
M32C_INSN_STE_W_BASIC_U20_DST16_RN_DIRECT_HI, "ste.w-basic-u20-dst16-Rn-direct-HI", "ste.w", 40,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.w $Dst16AnHI,${Dsp-16-u20} */
|
||||
{
|
||||
M32C_INSN_STE16_W_DST_DSPSP_BASIC_DST16_AN_DIRECT_HI, "ste16.w-dst-dspsp-basic-dst16-An-direct-HI", "ste.w", 40,
|
||||
M32C_INSN_STE_W_BASIC_U20_DST16_AN_DIRECT_HI, "ste.w-basic-u20-dst16-An-direct-HI", "ste.w", 40,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.w [$Dst16An],${Dsp-16-u20} */
|
||||
{
|
||||
M32C_INSN_STE16_W_DST_DSPSP_BASIC_DST16_AN_INDIRECT_HI, "ste16.w-dst-dspsp-basic-dst16-An-indirect-HI", "ste.w", 40,
|
||||
M32C_INSN_STE_W_BASIC_U20_DST16_AN_INDIRECT_HI, "ste.w-basic-u20-dst16-An-indirect-HI", "ste.w", 40,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */
|
||||
/* ste.b ${Dsp-16-u16}[$Dst16An],[a1a0] */
|
||||
{
|
||||
M32C_INSN_STE16_B_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_QI, "ste16.b-dst-dspsp-16-8-dst16-16-8-An-relative-QI", "ste.b", 48,
|
||||
M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_AN_RELATIVE_QI, "ste.b-16-16-a1a0-dst16-16-16-An-relative-QI", "ste.b", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.b ${Dsp-16-u8}[sb],${Dsp-24-u20} */
|
||||
/* ste.b ${Dsp-16-u16}[sb],[a1a0] */
|
||||
{
|
||||
M32C_INSN_STE16_B_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_QI, "ste16.b-dst-dspsp-16-8-dst16-16-8-SB-relative-QI", "ste.b", 48,
|
||||
M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_SB_RELATIVE_QI, "ste.b-16-16-a1a0-dst16-16-16-SB-relative-QI", "ste.b", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.b ${Dsp-16-s8}[fb],${Dsp-24-u20} */
|
||||
/* ste.b ${Dsp-16-u16},[a1a0] */
|
||||
{
|
||||
M32C_INSN_STE16_B_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_QI, "ste16.b-dst-dspsp-16-8-dst16-16-8-FB-relative-QI", "ste.b", 48,
|
||||
M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_ABSOLUTE_QI, "ste.b-16-16-a1a0-dst16-16-16-absolute-QI", "ste.b", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.b ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20}[a0] */
|
||||
{
|
||||
M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_AN_RELATIVE_QI, "ste.b-16-16-u20a0-dst16-16-16-An-relative-QI", "ste.b", 56,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.b ${Dsp-16-u16}[sb],${Dsp-32-u20}[a0] */
|
||||
{
|
||||
M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_SB_RELATIVE_QI, "ste.b-16-16-u20a0-dst16-16-16-SB-relative-QI", "ste.b", 56,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.b ${Dsp-16-u16},${Dsp-32-u20}[a0] */
|
||||
{
|
||||
M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_ABSOLUTE_QI, "ste.b-16-16-u20a0-dst16-16-16-absolute-QI", "ste.b", 56,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.b ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20} */
|
||||
{
|
||||
M32C_INSN_STE16_B_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_QI, "ste16.b-dst-dspsp-16-16-dst16-16-16-An-relative-QI", "ste.b", 56,
|
||||
M32C_INSN_STE_B_16_16_U20_DST16_16_16_AN_RELATIVE_QI, "ste.b-16-16-u20-dst16-16-16-An-relative-QI", "ste.b", 56,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.b ${Dsp-16-u16}[sb],${Dsp-32-u20} */
|
||||
{
|
||||
M32C_INSN_STE16_B_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_QI, "ste16.b-dst-dspsp-16-16-dst16-16-16-SB-relative-QI", "ste.b", 56,
|
||||
M32C_INSN_STE_B_16_16_U20_DST16_16_16_SB_RELATIVE_QI, "ste.b-16-16-u20-dst16-16-16-SB-relative-QI", "ste.b", 56,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.b ${Dsp-16-u16},${Dsp-32-u20} */
|
||||
{
|
||||
M32C_INSN_STE16_B_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_QI, "ste16.b-dst-dspsp-16-16-dst16-16-16-absolute-QI", "ste.b", 56,
|
||||
M32C_INSN_STE_B_16_16_U20_DST16_16_16_ABSOLUTE_QI, "ste.b-16-16-u20-dst16-16-16-absolute-QI", "ste.b", 56,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.b ${Dsp-16-u8}[$Dst16An],[a1a0] */
|
||||
{
|
||||
M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_AN_RELATIVE_QI, "ste.b-16-8-a1a0-dst16-16-8-An-relative-QI", "ste.b", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.b ${Dsp-16-u8}[sb],[a1a0] */
|
||||
{
|
||||
M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_SB_RELATIVE_QI, "ste.b-16-8-a1a0-dst16-16-8-SB-relative-QI", "ste.b", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.b ${Dsp-16-s8}[fb],[a1a0] */
|
||||
{
|
||||
M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_FB_RELATIVE_QI, "ste.b-16-8-a1a0-dst16-16-8-FB-relative-QI", "ste.b", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20}[a0] */
|
||||
{
|
||||
M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_AN_RELATIVE_QI, "ste.b-16-8-u20a0-dst16-16-8-An-relative-QI", "ste.b", 48,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.b ${Dsp-16-u8}[sb],${Dsp-24-u20}[a0] */
|
||||
{
|
||||
M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_SB_RELATIVE_QI, "ste.b-16-8-u20a0-dst16-16-8-SB-relative-QI", "ste.b", 48,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.b ${Dsp-16-s8}[fb],${Dsp-24-u20}[a0] */
|
||||
{
|
||||
M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_FB_RELATIVE_QI, "ste.b-16-8-u20a0-dst16-16-8-FB-relative-QI", "ste.b", 48,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */
|
||||
{
|
||||
M32C_INSN_STE_B_16_8_U20_DST16_16_8_AN_RELATIVE_QI, "ste.b-16-8-u20-dst16-16-8-An-relative-QI", "ste.b", 48,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.b ${Dsp-16-u8}[sb],${Dsp-24-u20} */
|
||||
{
|
||||
M32C_INSN_STE_B_16_8_U20_DST16_16_8_SB_RELATIVE_QI, "ste.b-16-8-u20-dst16-16-8-SB-relative-QI", "ste.b", 48,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.b ${Dsp-16-s8}[fb],${Dsp-24-u20} */
|
||||
{
|
||||
M32C_INSN_STE_B_16_8_U20_DST16_16_8_FB_RELATIVE_QI, "ste.b-16-8-u20-dst16-16-8-FB-relative-QI", "ste.b", 48,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.b $Dst16RnQI,[a1a0] */
|
||||
{
|
||||
M32C_INSN_STE_B_BASIC_A1A0_DST16_RN_DIRECT_QI, "ste.b-basic-a1a0-dst16-Rn-direct-QI", "ste.b", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.b $Dst16AnQI,[a1a0] */
|
||||
{
|
||||
M32C_INSN_STE_B_BASIC_A1A0_DST16_AN_DIRECT_QI, "ste.b-basic-a1a0-dst16-An-direct-QI", "ste.b", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.b [$Dst16An],[a1a0] */
|
||||
{
|
||||
M32C_INSN_STE_B_BASIC_A1A0_DST16_AN_INDIRECT_QI, "ste.b-basic-a1a0-dst16-An-indirect-QI", "ste.b", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.b $Dst16RnQI,${Dsp-16-u20}[a0] */
|
||||
{
|
||||
M32C_INSN_STE_B_BASIC_U20A0_DST16_RN_DIRECT_QI, "ste.b-basic-u20a0-dst16-Rn-direct-QI", "ste.b", 40,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.b $Dst16AnQI,${Dsp-16-u20}[a0] */
|
||||
{
|
||||
M32C_INSN_STE_B_BASIC_U20A0_DST16_AN_DIRECT_QI, "ste.b-basic-u20a0-dst16-An-direct-QI", "ste.b", 40,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.b [$Dst16An],${Dsp-16-u20}[a0] */
|
||||
{
|
||||
M32C_INSN_STE_B_BASIC_U20A0_DST16_AN_INDIRECT_QI, "ste.b-basic-u20a0-dst16-An-indirect-QI", "ste.b", 40,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.b $Dst16RnQI,${Dsp-16-u20} */
|
||||
{
|
||||
M32C_INSN_STE16_B_DST_DSPSP_BASIC_DST16_RN_DIRECT_QI, "ste16.b-dst-dspsp-basic-dst16-Rn-direct-QI", "ste.b", 40,
|
||||
M32C_INSN_STE_B_BASIC_U20_DST16_RN_DIRECT_QI, "ste.b-basic-u20-dst16-Rn-direct-QI", "ste.b", 40,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.b $Dst16AnQI,${Dsp-16-u20} */
|
||||
{
|
||||
M32C_INSN_STE16_B_DST_DSPSP_BASIC_DST16_AN_DIRECT_QI, "ste16.b-dst-dspsp-basic-dst16-An-direct-QI", "ste.b", 40,
|
||||
M32C_INSN_STE_B_BASIC_U20_DST16_AN_DIRECT_QI, "ste.b-basic-u20-dst16-An-direct-QI", "ste.b", 40,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* ste.b [$Dst16An],${Dsp-16-u20} */
|
||||
{
|
||||
M32C_INSN_STE16_B_DST_DSPSP_BASIC_DST16_AN_INDIRECT_QI, "ste16.b-dst-dspsp-basic-dst16-An-indirect-QI", "ste.b", 40,
|
||||
M32C_INSN_STE_B_BASIC_U20_DST16_AN_INDIRECT_QI, "ste.b-basic-u20-dst16-An-indirect-QI", "ste.b", 40,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.w ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */
|
||||
/* lde.w [a1a0],${Dsp-16-u16}[$Dst16An] */
|
||||
{
|
||||
M32C_INSN_LDE16_W_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_HI, "lde16.w-dst-dspsp-16-8-dst16-16-8-An-relative-HI", "lde.w", 48,
|
||||
M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_AN_RELATIVE_HI, "lde.w-16-16-a1a0-dst16-16-16-An-relative-HI", "lde.w", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.w ${Dsp-24-u20},${Dsp-16-u8}[sb] */
|
||||
/* lde.w [a1a0],${Dsp-16-u16}[sb] */
|
||||
{
|
||||
M32C_INSN_LDE16_W_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_HI, "lde16.w-dst-dspsp-16-8-dst16-16-8-SB-relative-HI", "lde.w", 48,
|
||||
M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_SB_RELATIVE_HI, "lde.w-16-16-a1a0-dst16-16-16-SB-relative-HI", "lde.w", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.w ${Dsp-24-u20},${Dsp-16-s8}[fb] */
|
||||
/* lde.w [a1a0],${Dsp-16-u16} */
|
||||
{
|
||||
M32C_INSN_LDE16_W_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_HI, "lde16.w-dst-dspsp-16-8-dst16-16-8-FB-relative-HI", "lde.w", 48,
|
||||
M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_ABSOLUTE_HI, "lde.w-16-16-a1a0-dst16-16-16-absolute-HI", "lde.w", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16}[$Dst16An] */
|
||||
{
|
||||
M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_AN_RELATIVE_HI, "lde.w-16-16-u20a0-dst16-16-16-An-relative-HI", "lde.w", 56,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16}[sb] */
|
||||
{
|
||||
M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_SB_RELATIVE_HI, "lde.w-16-16-u20a0-dst16-16-16-SB-relative-HI", "lde.w", 56,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16} */
|
||||
{
|
||||
M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_ABSOLUTE_HI, "lde.w-16-16-u20a0-dst16-16-16-absolute-HI", "lde.w", 56,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.w ${Dsp-32-u20},${Dsp-16-u16}[$Dst16An] */
|
||||
{
|
||||
M32C_INSN_LDE16_W_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_HI, "lde16.w-dst-dspsp-16-16-dst16-16-16-An-relative-HI", "lde.w", 56,
|
||||
M32C_INSN_LDE_W_16_16_U20_DST16_16_16_AN_RELATIVE_HI, "lde.w-16-16-u20-dst16-16-16-An-relative-HI", "lde.w", 56,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.w ${Dsp-32-u20},${Dsp-16-u16}[sb] */
|
||||
{
|
||||
M32C_INSN_LDE16_W_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_HI, "lde16.w-dst-dspsp-16-16-dst16-16-16-SB-relative-HI", "lde.w", 56,
|
||||
M32C_INSN_LDE_W_16_16_U20_DST16_16_16_SB_RELATIVE_HI, "lde.w-16-16-u20-dst16-16-16-SB-relative-HI", "lde.w", 56,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.w ${Dsp-32-u20},${Dsp-16-u16} */
|
||||
{
|
||||
M32C_INSN_LDE16_W_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_HI, "lde16.w-dst-dspsp-16-16-dst16-16-16-absolute-HI", "lde.w", 56,
|
||||
M32C_INSN_LDE_W_16_16_U20_DST16_16_16_ABSOLUTE_HI, "lde.w-16-16-u20-dst16-16-16-absolute-HI", "lde.w", 56,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.w [a1a0],${Dsp-16-u8}[$Dst16An] */
|
||||
{
|
||||
M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_AN_RELATIVE_HI, "lde.w-16-8-a1a0-dst16-16-8-An-relative-HI", "lde.w", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.w [a1a0],${Dsp-16-u8}[sb] */
|
||||
{
|
||||
M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_SB_RELATIVE_HI, "lde.w-16-8-a1a0-dst16-16-8-SB-relative-HI", "lde.w", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.w [a1a0],${Dsp-16-s8}[fb] */
|
||||
{
|
||||
M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_FB_RELATIVE_HI, "lde.w-16-8-a1a0-dst16-16-8-FB-relative-HI", "lde.w", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.w ${Dsp-24-u20}[a0],${Dsp-16-u8}[$Dst16An] */
|
||||
{
|
||||
M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_AN_RELATIVE_HI, "lde.w-16-8-u20a0-dst16-16-8-An-relative-HI", "lde.w", 48,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.w ${Dsp-24-u20}[a0],${Dsp-16-u8}[sb] */
|
||||
{
|
||||
M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_SB_RELATIVE_HI, "lde.w-16-8-u20a0-dst16-16-8-SB-relative-HI", "lde.w", 48,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.w ${Dsp-24-u20}[a0],${Dsp-16-s8}[fb] */
|
||||
{
|
||||
M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_FB_RELATIVE_HI, "lde.w-16-8-u20a0-dst16-16-8-FB-relative-HI", "lde.w", 48,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.w ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */
|
||||
{
|
||||
M32C_INSN_LDE_W_16_8_U20_DST16_16_8_AN_RELATIVE_HI, "lde.w-16-8-u20-dst16-16-8-An-relative-HI", "lde.w", 48,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.w ${Dsp-24-u20},${Dsp-16-u8}[sb] */
|
||||
{
|
||||
M32C_INSN_LDE_W_16_8_U20_DST16_16_8_SB_RELATIVE_HI, "lde.w-16-8-u20-dst16-16-8-SB-relative-HI", "lde.w", 48,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.w ${Dsp-24-u20},${Dsp-16-s8}[fb] */
|
||||
{
|
||||
M32C_INSN_LDE_W_16_8_U20_DST16_16_8_FB_RELATIVE_HI, "lde.w-16-8-u20-dst16-16-8-FB-relative-HI", "lde.w", 48,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.w [a1a0],$Dst16RnHI */
|
||||
{
|
||||
M32C_INSN_LDE_W_BASIC_A1A0_DST16_RN_DIRECT_HI, "lde.w-basic-a1a0-dst16-Rn-direct-HI", "lde.w", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.w [a1a0],$Dst16AnHI */
|
||||
{
|
||||
M32C_INSN_LDE_W_BASIC_A1A0_DST16_AN_DIRECT_HI, "lde.w-basic-a1a0-dst16-An-direct-HI", "lde.w", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.w [a1a0],[$Dst16An] */
|
||||
{
|
||||
M32C_INSN_LDE_W_BASIC_A1A0_DST16_AN_INDIRECT_HI, "lde.w-basic-a1a0-dst16-An-indirect-HI", "lde.w", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.w ${Dsp-16-u20}[a0],$Dst16RnHI */
|
||||
{
|
||||
M32C_INSN_LDE_W_BASIC_U20A0_DST16_RN_DIRECT_HI, "lde.w-basic-u20a0-dst16-Rn-direct-HI", "lde.w", 40,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.w ${Dsp-16-u20}[a0],$Dst16AnHI */
|
||||
{
|
||||
M32C_INSN_LDE_W_BASIC_U20A0_DST16_AN_DIRECT_HI, "lde.w-basic-u20a0-dst16-An-direct-HI", "lde.w", 40,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.w ${Dsp-16-u20}[a0],[$Dst16An] */
|
||||
{
|
||||
M32C_INSN_LDE_W_BASIC_U20A0_DST16_AN_INDIRECT_HI, "lde.w-basic-u20a0-dst16-An-indirect-HI", "lde.w", 40,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.w ${Dsp-16-u20},$Dst16RnHI */
|
||||
{
|
||||
M32C_INSN_LDE16_W_DST_DSPSP_BASIC_DST16_RN_DIRECT_HI, "lde16.w-dst-dspsp-basic-dst16-Rn-direct-HI", "lde.w", 40,
|
||||
M32C_INSN_LDE_W_BASIC_U20_DST16_RN_DIRECT_HI, "lde.w-basic-u20-dst16-Rn-direct-HI", "lde.w", 40,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.w ${Dsp-16-u20},$Dst16AnHI */
|
||||
{
|
||||
M32C_INSN_LDE16_W_DST_DSPSP_BASIC_DST16_AN_DIRECT_HI, "lde16.w-dst-dspsp-basic-dst16-An-direct-HI", "lde.w", 40,
|
||||
M32C_INSN_LDE_W_BASIC_U20_DST16_AN_DIRECT_HI, "lde.w-basic-u20-dst16-An-direct-HI", "lde.w", 40,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.w ${Dsp-16-u20},[$Dst16An] */
|
||||
{
|
||||
M32C_INSN_LDE16_W_DST_DSPSP_BASIC_DST16_AN_INDIRECT_HI, "lde16.w-dst-dspsp-basic-dst16-An-indirect-HI", "lde.w", 40,
|
||||
M32C_INSN_LDE_W_BASIC_U20_DST16_AN_INDIRECT_HI, "lde.w-basic-u20-dst16-An-indirect-HI", "lde.w", 40,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.b ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */
|
||||
/* lde.b [a1a0],${Dsp-16-u16}[$Dst16An] */
|
||||
{
|
||||
M32C_INSN_LDE16_B_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_QI, "lde16.b-dst-dspsp-16-8-dst16-16-8-An-relative-QI", "lde.b", 48,
|
||||
M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_AN_RELATIVE_QI, "lde.b-16-16-a1a0-dst16-16-16-An-relative-QI", "lde.b", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.b ${Dsp-24-u20},${Dsp-16-u8}[sb] */
|
||||
/* lde.b [a1a0],${Dsp-16-u16}[sb] */
|
||||
{
|
||||
M32C_INSN_LDE16_B_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_QI, "lde16.b-dst-dspsp-16-8-dst16-16-8-SB-relative-QI", "lde.b", 48,
|
||||
M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_SB_RELATIVE_QI, "lde.b-16-16-a1a0-dst16-16-16-SB-relative-QI", "lde.b", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.b ${Dsp-24-u20},${Dsp-16-s8}[fb] */
|
||||
/* lde.b [a1a0],${Dsp-16-u16} */
|
||||
{
|
||||
M32C_INSN_LDE16_B_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_QI, "lde16.b-dst-dspsp-16-8-dst16-16-8-FB-relative-QI", "lde.b", 48,
|
||||
M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_ABSOLUTE_QI, "lde.b-16-16-a1a0-dst16-16-16-absolute-QI", "lde.b", 32,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16}[$Dst16An] */
|
||||
{
|
||||
M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_AN_RELATIVE_QI, "lde.b-16-16-u20a0-dst16-16-16-An-relative-QI", "lde.b", 56,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16}[sb] */
|
||||
{
|
||||
M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_SB_RELATIVE_QI, "lde.b-16-16-u20a0-dst16-16-16-SB-relative-QI", "lde.b", 56,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16} */
|
||||
{
|
||||
M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_ABSOLUTE_QI, "lde.b-16-16-u20a0-dst16-16-16-absolute-QI", "lde.b", 56,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.b ${Dsp-32-u20},${Dsp-16-u16}[$Dst16An] */
|
||||
{
|
||||
M32C_INSN_LDE16_B_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_QI, "lde16.b-dst-dspsp-16-16-dst16-16-16-An-relative-QI", "lde.b", 56,
|
||||
M32C_INSN_LDE_B_16_16_U20_DST16_16_16_AN_RELATIVE_QI, "lde.b-16-16-u20-dst16-16-16-An-relative-QI", "lde.b", 56,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.b ${Dsp-32-u20},${Dsp-16-u16}[sb] */
|
||||
{
|
||||
M32C_INSN_LDE16_B_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_QI, "lde16.b-dst-dspsp-16-16-dst16-16-16-SB-relative-QI", "lde.b", 56,
|
||||
M32C_INSN_LDE_B_16_16_U20_DST16_16_16_SB_RELATIVE_QI, "lde.b-16-16-u20-dst16-16-16-SB-relative-QI", "lde.b", 56,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.b ${Dsp-32-u20},${Dsp-16-u16} */
|
||||
{
|
||||
M32C_INSN_LDE16_B_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_QI, "lde16.b-dst-dspsp-16-16-dst16-16-16-absolute-QI", "lde.b", 56,
|
||||
M32C_INSN_LDE_B_16_16_U20_DST16_16_16_ABSOLUTE_QI, "lde.b-16-16-u20-dst16-16-16-absolute-QI", "lde.b", 56,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.b [a1a0],${Dsp-16-u8}[$Dst16An] */
|
||||
{
|
||||
M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_AN_RELATIVE_QI, "lde.b-16-8-a1a0-dst16-16-8-An-relative-QI", "lde.b", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.b [a1a0],${Dsp-16-u8}[sb] */
|
||||
{
|
||||
M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_SB_RELATIVE_QI, "lde.b-16-8-a1a0-dst16-16-8-SB-relative-QI", "lde.b", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.b [a1a0],${Dsp-16-s8}[fb] */
|
||||
{
|
||||
M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_FB_RELATIVE_QI, "lde.b-16-8-a1a0-dst16-16-8-FB-relative-QI", "lde.b", 24,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.b ${Dsp-24-u20}[a0],${Dsp-16-u8}[$Dst16An] */
|
||||
{
|
||||
M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_AN_RELATIVE_QI, "lde.b-16-8-u20a0-dst16-16-8-An-relative-QI", "lde.b", 48,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.b ${Dsp-24-u20}[a0],${Dsp-16-u8}[sb] */
|
||||
{
|
||||
M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_SB_RELATIVE_QI, "lde.b-16-8-u20a0-dst16-16-8-SB-relative-QI", "lde.b", 48,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.b ${Dsp-24-u20}[a0],${Dsp-16-s8}[fb] */
|
||||
{
|
||||
M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_FB_RELATIVE_QI, "lde.b-16-8-u20a0-dst16-16-8-FB-relative-QI", "lde.b", 48,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.b ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */
|
||||
{
|
||||
M32C_INSN_LDE_B_16_8_U20_DST16_16_8_AN_RELATIVE_QI, "lde.b-16-8-u20-dst16-16-8-An-relative-QI", "lde.b", 48,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.b ${Dsp-24-u20},${Dsp-16-u8}[sb] */
|
||||
{
|
||||
M32C_INSN_LDE_B_16_8_U20_DST16_16_8_SB_RELATIVE_QI, "lde.b-16-8-u20-dst16-16-8-SB-relative-QI", "lde.b", 48,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.b ${Dsp-24-u20},${Dsp-16-s8}[fb] */
|
||||
{
|
||||
M32C_INSN_LDE_B_16_8_U20_DST16_16_8_FB_RELATIVE_QI, "lde.b-16-8-u20-dst16-16-8-FB-relative-QI", "lde.b", 48,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.b [a1a0],$Dst16RnQI */
|
||||
{
|
||||
M32C_INSN_LDE_B_BASIC_A1A0_DST16_RN_DIRECT_QI, "lde.b-basic-a1a0-dst16-Rn-direct-QI", "lde.b", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.b [a1a0],$Dst16AnQI */
|
||||
{
|
||||
M32C_INSN_LDE_B_BASIC_A1A0_DST16_AN_DIRECT_QI, "lde.b-basic-a1a0-dst16-An-direct-QI", "lde.b", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.b [a1a0],[$Dst16An] */
|
||||
{
|
||||
M32C_INSN_LDE_B_BASIC_A1A0_DST16_AN_INDIRECT_QI, "lde.b-basic-a1a0-dst16-An-indirect-QI", "lde.b", 16,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.b ${Dsp-16-u20}[a0],$Dst16RnQI */
|
||||
{
|
||||
M32C_INSN_LDE_B_BASIC_U20A0_DST16_RN_DIRECT_QI, "lde.b-basic-u20a0-dst16-Rn-direct-QI", "lde.b", 40,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.b ${Dsp-16-u20}[a0],$Dst16AnQI */
|
||||
{
|
||||
M32C_INSN_LDE_B_BASIC_U20A0_DST16_AN_DIRECT_QI, "lde.b-basic-u20a0-dst16-An-direct-QI", "lde.b", 40,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.b ${Dsp-16-u20}[a0],[$Dst16An] */
|
||||
{
|
||||
M32C_INSN_LDE_B_BASIC_U20A0_DST16_AN_INDIRECT_QI, "lde.b-basic-u20a0-dst16-An-indirect-QI", "lde.b", 40,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.b ${Dsp-16-u20},$Dst16RnQI */
|
||||
{
|
||||
M32C_INSN_LDE16_B_DST_DSPSP_BASIC_DST16_RN_DIRECT_QI, "lde16.b-dst-dspsp-basic-dst16-Rn-direct-QI", "lde.b", 40,
|
||||
M32C_INSN_LDE_B_BASIC_U20_DST16_RN_DIRECT_QI, "lde.b-basic-u20-dst16-Rn-direct-QI", "lde.b", 40,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.b ${Dsp-16-u20},$Dst16AnQI */
|
||||
{
|
||||
M32C_INSN_LDE16_B_DST_DSPSP_BASIC_DST16_AN_DIRECT_QI, "lde16.b-dst-dspsp-basic-dst16-An-direct-QI", "lde.b", 40,
|
||||
M32C_INSN_LDE_B_BASIC_U20_DST16_AN_DIRECT_QI, "lde.b-basic-u20-dst16-An-direct-QI", "lde.b", 40,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* lde.b ${Dsp-16-u20},[$Dst16An] */
|
||||
{
|
||||
M32C_INSN_LDE16_B_DST_DSPSP_BASIC_DST16_AN_INDIRECT_QI, "lde16.b-dst-dspsp-basic-dst16-An-indirect-QI", "lde.b", 40,
|
||||
M32C_INSN_LDE_B_BASIC_U20_DST16_AN_INDIRECT_QI, "lde.b-basic-u20-dst16-An-indirect-QI", "lde.b", 40,
|
||||
{ 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
|
||||
},
|
||||
/* stc ${cr3-Prefixed-32},$Dst32RnPrefixedSI */
|
||||
|
||||
@ -206,212 +206,217 @@ typedef enum cgen_operand_type {
|
||||
, M32C_OPERAND_DST16AN_S, M32C_OPERAND_DST32ANUNPREFIXED, M32C_OPERAND_DST32ANUNPREFIXEDQI, M32C_OPERAND_DST32ANUNPREFIXEDHI
|
||||
, M32C_OPERAND_DST32ANUNPREFIXEDSI, M32C_OPERAND_DST32ANEXTUNPREFIXED, M32C_OPERAND_DST32ANPREFIXED, M32C_OPERAND_DST32ANPREFIXEDQI
|
||||
, M32C_OPERAND_DST32ANPREFIXEDHI, M32C_OPERAND_DST32ANPREFIXEDSI, M32C_OPERAND_BIT16AN, M32C_OPERAND_BIT32ANPREFIXED
|
||||
, M32C_OPERAND_BIT32ANUNPREFIXED, M32C_OPERAND_A0, M32C_OPERAND_A1, M32C_OPERAND_SB
|
||||
, M32C_OPERAND_FB, M32C_OPERAND_SP, M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL, M32C_OPERAND_REGSETPOP
|
||||
, M32C_OPERAND_REGSETPUSH, M32C_OPERAND_RN16_PUSH_S, M32C_OPERAND_AN16_PUSH_S, M32C_OPERAND_DSP_8_U6
|
||||
, M32C_OPERAND_DSP_8_U8, M32C_OPERAND_DSP_8_U16, M32C_OPERAND_DSP_8_S8, M32C_OPERAND_DSP_8_U24
|
||||
, M32C_OPERAND_DSP_10_U6, M32C_OPERAND_DSP_16_U8, M32C_OPERAND_DSP_16_U16, M32C_OPERAND_DSP_16_U20
|
||||
, M32C_OPERAND_DSP_16_U24, M32C_OPERAND_DSP_16_S8, M32C_OPERAND_DSP_16_S16, M32C_OPERAND_DSP_24_U8
|
||||
, M32C_OPERAND_DSP_24_U16, M32C_OPERAND_DSP_24_U20, M32C_OPERAND_DSP_24_U24, M32C_OPERAND_DSP_24_S8
|
||||
, M32C_OPERAND_DSP_24_S16, M32C_OPERAND_DSP_32_U8, M32C_OPERAND_DSP_32_U16, M32C_OPERAND_DSP_32_U24
|
||||
, M32C_OPERAND_DSP_32_U20, M32C_OPERAND_DSP_32_S8, M32C_OPERAND_DSP_32_S16, M32C_OPERAND_DSP_40_U8
|
||||
, M32C_OPERAND_DSP_40_S8, M32C_OPERAND_DSP_40_U16, M32C_OPERAND_DSP_40_S16, M32C_OPERAND_DSP_40_U24
|
||||
, M32C_OPERAND_DSP_48_U8, M32C_OPERAND_DSP_48_S8, M32C_OPERAND_DSP_48_U16, M32C_OPERAND_DSP_48_S16
|
||||
, M32C_OPERAND_DSP_48_U24, M32C_OPERAND_IMM_8_S4, M32C_OPERAND_IMM_SH_8_S4, M32C_OPERAND_IMM_8_QI
|
||||
, M32C_OPERAND_IMM_8_HI, M32C_OPERAND_IMM_12_S4, M32C_OPERAND_IMM_SH_12_S4, M32C_OPERAND_IMM_13_U3
|
||||
, M32C_OPERAND_IMM_20_S4, M32C_OPERAND_IMM_SH_20_S4, M32C_OPERAND_IMM_16_QI, M32C_OPERAND_IMM_16_HI
|
||||
, M32C_OPERAND_IMM_16_SI, M32C_OPERAND_IMM_24_QI, M32C_OPERAND_IMM_24_HI, M32C_OPERAND_IMM_24_SI
|
||||
, M32C_OPERAND_IMM_32_QI, M32C_OPERAND_IMM_32_SI, M32C_OPERAND_IMM_32_HI, M32C_OPERAND_IMM_40_QI
|
||||
, M32C_OPERAND_IMM_40_HI, M32C_OPERAND_IMM_40_SI, M32C_OPERAND_IMM_48_QI, M32C_OPERAND_IMM_48_HI
|
||||
, M32C_OPERAND_IMM_48_SI, M32C_OPERAND_IMM_56_QI, M32C_OPERAND_IMM_56_HI, M32C_OPERAND_IMM_64_HI
|
||||
, M32C_OPERAND_IMM1_S, M32C_OPERAND_IMM3_S, M32C_OPERAND_BITNO16R, M32C_OPERAND_BITNO32PREFIXED
|
||||
, M32C_OPERAND_BITNO32UNPREFIXED, M32C_OPERAND_BITBASE16_16_U8, M32C_OPERAND_BITBASE16_16_S8, M32C_OPERAND_BITBASE16_16_U16
|
||||
, M32C_OPERAND_BITBASE16_8_U11_S, M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED, M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED, M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED
|
||||
, M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED, M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED, M32C_OPERAND_BITBASE32_24_U11_PREFIXED, M32C_OPERAND_BITBASE32_24_S11_PREFIXED
|
||||
, M32C_OPERAND_BITBASE32_24_U19_PREFIXED, M32C_OPERAND_BITBASE32_24_S19_PREFIXED, M32C_OPERAND_BITBASE32_24_U27_PREFIXED, M32C_OPERAND_LAB_5_3
|
||||
, M32C_OPERAND_LAB32_JMP_S, M32C_OPERAND_LAB_8_8, M32C_OPERAND_LAB_8_16, M32C_OPERAND_LAB_8_24
|
||||
, M32C_OPERAND_LAB_16_8, M32C_OPERAND_LAB_24_8, M32C_OPERAND_LAB_32_8, M32C_OPERAND_LAB_40_8
|
||||
, M32C_OPERAND_SBIT, M32C_OPERAND_OBIT, M32C_OPERAND_ZBIT, M32C_OPERAND_CBIT
|
||||
, M32C_OPERAND_UBIT, M32C_OPERAND_IBIT, M32C_OPERAND_BBIT, M32C_OPERAND_DBIT
|
||||
, M32C_OPERAND_COND16_16, M32C_OPERAND_COND16_24, M32C_OPERAND_COND16_32, M32C_OPERAND_COND32_16
|
||||
, M32C_OPERAND_COND32_24, M32C_OPERAND_COND32_32, M32C_OPERAND_COND32_40, M32C_OPERAND_COND16C
|
||||
, M32C_OPERAND_COND16J, M32C_OPERAND_COND16J5, M32C_OPERAND_COND32, M32C_OPERAND_COND32J
|
||||
, M32C_OPERAND_SCCOND32, M32C_OPERAND_FLAGS16, M32C_OPERAND_FLAGS32, M32C_OPERAND_CR16
|
||||
, M32C_OPERAND_CR1_UNPREFIXED_32, M32C_OPERAND_CR1_PREFIXED_32, M32C_OPERAND_CR2_32, M32C_OPERAND_CR3_UNPREFIXED_32
|
||||
, M32C_OPERAND_CR3_PREFIXED_32, M32C_OPERAND_Z, M32C_OPERAND_S, M32C_OPERAND_Q
|
||||
, M32C_OPERAND_G, M32C_OPERAND_X, M32C_OPERAND_SIZE, M32C_OPERAND_BITINDEX
|
||||
, M32C_OPERAND_SRCINDEX, M32C_OPERAND_DSTINDEX, M32C_OPERAND_NOREMAINDER, M32C_OPERAND_SRC16_RN_DIRECT_QI
|
||||
, M32C_OPERAND_SRC16_RN_DIRECT_HI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_HI
|
||||
, M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_HI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_AN_DIRECT_QI
|
||||
, M32C_OPERAND_SRC16_AN_DIRECT_HI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_SI
|
||||
, M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_HI, M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_AN_INDIRECT_QI
|
||||
, M32C_OPERAND_SRC16_AN_INDIRECT_HI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_QI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_SI
|
||||
, M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_HI, M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_16_8_SB_RELATIVE_QI
|
||||
, M32C_OPERAND_SRC16_16_16_SB_RELATIVE_QI, M32C_OPERAND_SRC16_16_8_FB_RELATIVE_QI, M32C_OPERAND_SRC16_16_8_AN_RELATIVE_QI, M32C_OPERAND_SRC16_16_16_AN_RELATIVE_QI
|
||||
, M32C_OPERAND_SRC16_16_8_SB_RELATIVE_HI, M32C_OPERAND_SRC16_16_16_SB_RELATIVE_HI, M32C_OPERAND_SRC16_16_8_FB_RELATIVE_HI, M32C_OPERAND_SRC16_16_8_AN_RELATIVE_HI
|
||||
, M32C_OPERAND_SRC16_16_16_AN_RELATIVE_HI, M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_QI
|
||||
, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_QI
|
||||
, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_HI
|
||||
, M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_HI
|
||||
, M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_SI
|
||||
, M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC16_16_16_ABSOLUTE_QI
|
||||
, M32C_OPERAND_SRC16_16_16_ABSOLUTE_HI, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_QI
|
||||
, M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_SI
|
||||
, M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_SRC16_2_S_8_SB_RELATIVE_QI, M32C_OPERAND_SRC16_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_SRC16_2_S_16_ABSOLUTE_QI
|
||||
, M32C_OPERAND_SRC32_2_S_8_SB_RELATIVE_QI, M32C_OPERAND_SRC32_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_SRC32_2_S_16_ABSOLUTE_QI, M32C_OPERAND_SRC32_2_S_8_SB_RELATIVE_HI
|
||||
, M32C_OPERAND_SRC32_2_S_8_FB_RELATIVE_HI, M32C_OPERAND_SRC32_2_S_16_ABSOLUTE_HI, M32C_OPERAND_DST16_RN_DIRECT_QI, M32C_OPERAND_DST16_RN_DIRECT_HI
|
||||
, M32C_OPERAND_DST16_RN_DIRECT_SI, M32C_OPERAND_DST16_RN_DIRECT_EXT_QI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_HI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_RN_DIRECT_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_RN_DIRECT_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_R3_DIRECT_UNPREFIXED_HI, M32C_OPERAND_DST16_AN_DIRECT_QI
|
||||
, M32C_OPERAND_DST16_AN_DIRECT_HI, M32C_OPERAND_DST16_AN_DIRECT_SI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_HI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_SI
|
||||
, M32C_OPERAND_DST16_AN_INDIRECT_QI, M32C_OPERAND_DST16_AN_INDIRECT_HI, M32C_OPERAND_DST16_AN_INDIRECT_SI, M32C_OPERAND_DST16_AN_INDIRECT_EXT_QI
|
||||
, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_SI, M32C_OPERAND_DST32_AN_INDIRECT_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_EXTUNPREFIXED_HI
|
||||
, M32C_OPERAND_DST16_16_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_QI
|
||||
, M32C_OPERAND_DST16_16_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_24_8_FB_RELATIVE_QI
|
||||
, M32C_OPERAND_DST16_24_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_32_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_32_16_SB_RELATIVE_QI
|
||||
, M32C_OPERAND_DST16_32_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_32_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_40_8_SB_RELATIVE_QI
|
||||
, M32C_OPERAND_DST16_40_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_40_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_40_16_AN_RELATIVE_QI
|
||||
, M32C_OPERAND_DST16_48_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_48_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_48_8_AN_RELATIVE_QI
|
||||
, M32C_OPERAND_DST16_48_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_HI
|
||||
, M32C_OPERAND_DST16_16_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_HI
|
||||
, M32C_OPERAND_DST16_24_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_24_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_32_8_SB_RELATIVE_HI
|
||||
, M32C_OPERAND_DST16_32_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_32_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_32_16_AN_RELATIVE_HI
|
||||
, M32C_OPERAND_DST16_40_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_40_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_40_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_HI
|
||||
, M32C_OPERAND_DST16_40_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_48_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_48_8_FB_RELATIVE_HI
|
||||
, M32C_OPERAND_DST16_48_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_48_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_SI
|
||||
, M32C_OPERAND_DST16_16_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_SI
|
||||
, M32C_OPERAND_DST16_24_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_24_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_24_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_SI
|
||||
, M32C_OPERAND_DST16_32_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_32_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_32_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_SI
|
||||
, M32C_OPERAND_DST16_32_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_40_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_40_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_40_8_FB_RELATIVE_SI
|
||||
, M32C_OPERAND_DST16_40_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_40_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_48_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_SI
|
||||
, M32C_OPERAND_DST16_48_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_48_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_48_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_EXT_QI
|
||||
, M32C_OPERAND_DST16_16_16_SB_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_EXT_QI
|
||||
, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST16_16_16_ABSOLUTE_QI, M32C_OPERAND_DST16_24_16_ABSOLUTE_QI
|
||||
, M32C_OPERAND_DST16_32_16_ABSOLUTE_QI, M32C_OPERAND_DST16_40_16_ABSOLUTE_QI, M32C_OPERAND_DST16_48_16_ABSOLUTE_QI, M32C_OPERAND_DST16_16_16_ABSOLUTE_HI
|
||||
, M32C_OPERAND_DST16_24_16_ABSOLUTE_HI, M32C_OPERAND_DST16_32_16_ABSOLUTE_HI, M32C_OPERAND_DST16_40_16_ABSOLUTE_HI, M32C_OPERAND_DST16_48_16_ABSOLUTE_HI
|
||||
, M32C_OPERAND_DST16_16_16_ABSOLUTE_SI, M32C_OPERAND_DST16_24_16_ABSOLUTE_SI, M32C_OPERAND_DST16_32_16_ABSOLUTE_SI, M32C_OPERAND_DST16_40_16_ABSOLUTE_SI
|
||||
, M32C_OPERAND_DST16_48_16_ABSOLUTE_SI, M32C_OPERAND_DST16_16_16_ABSOLUTE_EXT_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_HI, M32C_OPERAND_BIT16_RN_DIRECT, M32C_OPERAND_BIT32_RN_DIRECT_UNPREFIXED
|
||||
, M32C_OPERAND_BIT32_RN_DIRECT_PREFIXED, M32C_OPERAND_BIT16_AN_DIRECT, M32C_OPERAND_BIT32_AN_DIRECT_UNPREFIXED, M32C_OPERAND_BIT32_AN_DIRECT_PREFIXED
|
||||
, M32C_OPERAND_BIT16_AN_INDIRECT, M32C_OPERAND_BIT32_AN_INDIRECT_UNPREFIXED, M32C_OPERAND_BIT32_AN_INDIRECT_PREFIXED, M32C_OPERAND_BIT16_16_8_SB_RELATIVE
|
||||
, M32C_OPERAND_BIT16_16_16_SB_RELATIVE, M32C_OPERAND_BIT16_16_8_FB_RELATIVE, M32C_OPERAND_BIT16_16_8_AN_RELATIVE, M32C_OPERAND_BIT16_16_16_AN_RELATIVE
|
||||
, M32C_OPERAND_BIT32_16_11_SB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_19_SB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_19_FB_RELATIVE_UNPREFIXED
|
||||
, M32C_OPERAND_BIT32_16_11_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_27_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_24_11_SB_RELATIVE_PREFIXED
|
||||
, M32C_OPERAND_BIT32_24_19_SB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_11_FB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_19_FB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_11_AN_RELATIVE_PREFIXED
|
||||
, M32C_OPERAND_BIT32_24_19_AN_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_27_AN_RELATIVE_PREFIXED, M32C_OPERAND_BIT16_11_SB_RELATIVE_S, M32C_OPERAND_RN16_PUSH_S_DERIVED
|
||||
, M32C_OPERAND_AN16_PUSH_S_DERIVED, M32C_OPERAND_BIT16_16_16_ABSOLUTE, M32C_OPERAND_BIT32_16_19_ABSOLUTE_UNPREFIXED, M32C_OPERAND_BIT32_16_27_ABSOLUTE_UNPREFIXED
|
||||
, M32C_OPERAND_BIT32_24_19_ABSOLUTE_PREFIXED, M32C_OPERAND_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_OPERAND_DST16_3_S_R0L_DIRECT_QI, M32C_OPERAND_DST16_3_S_R0H_DIRECT_QI
|
||||
, M32C_OPERAND_DST16_3_S_8_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_8_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_8_16_ABSOLUTE_QI, M32C_OPERAND_DST16_3_S_16_8_SB_RELATIVE_QI
|
||||
, M32C_OPERAND_DST16_3_S_16_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_16_16_ABSOLUTE_QI, M32C_OPERAND_SRCDST16_R0L_R0H_S_DERIVED, M32C_OPERAND_DST32_2_S_R0L_DIRECT_QI
|
||||
, M32C_OPERAND_DST32_2_S_R0_DIRECT_HI, M32C_OPERAND_DST32_1_S_A0_DIRECT_HI, M32C_OPERAND_DST32_1_S_A1_DIRECT_HI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_QI
|
||||
, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_DST32_2_S_16_ABSOLUTE_QI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_HI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_HI
|
||||
, M32C_OPERAND_DST32_2_S_16_ABSOLUTE_HI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_SI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_SI, M32C_OPERAND_DST32_2_S_16_ABSOLUTE_SI
|
||||
, M32C_OPERAND_SRC16_BASIC_QI, M32C_OPERAND_SRC16_BASIC_HI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_QI, M32C_OPERAND_SRC32_BASIC_PREFIXED_QI
|
||||
, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_HI, M32C_OPERAND_SRC32_BASIC_PREFIXED_HI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_SI, M32C_OPERAND_SRC32_BASIC_PREFIXED_SI
|
||||
, M32C_OPERAND_SRC32_BASIC_EXTPREFIXED_QI, M32C_OPERAND_SRC16_16_8_QI, M32C_OPERAND_SRC16_16_16_QI, M32C_OPERAND_SRC16_16_8_HI
|
||||
, M32C_OPERAND_SRC16_16_16_HI, M32C_OPERAND_SRC32_16_8_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_QI
|
||||
, M32C_OPERAND_SRC32_16_8_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_UNPREFIXED_SI
|
||||
, M32C_OPERAND_SRC32_16_16_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_8_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_PREFIXED_QI
|
||||
, M32C_OPERAND_SRC32_24_24_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_PREFIXED_HI
|
||||
, M32C_OPERAND_SRC32_24_8_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_PREFIXED_SI, M32C_OPERAND_DST16_BASIC_QI
|
||||
, M32C_OPERAND_DST16_BASIC_HI, M32C_OPERAND_DST16_BASIC_SI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_QI, M32C_OPERAND_DST32_BASIC_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_BASIC_UNPREFIXED_HI, M32C_OPERAND_DST32_BASIC_PREFIXED_HI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_SI, M32C_OPERAND_DST32_BASIC_PREFIXED_SI
|
||||
, M32C_OPERAND_DST16_16_QI, M32C_OPERAND_DST16_16_8_QI, M32C_OPERAND_DST16_16_16_QI, M32C_OPERAND_DST16_16_HI
|
||||
, M32C_OPERAND_DST16_16_8_HI, M32C_OPERAND_DST16_16_16_HI, M32C_OPERAND_DST16_16_SI, M32C_OPERAND_DST16_16_8_SI
|
||||
, M32C_OPERAND_DST16_16_16_SI, M32C_OPERAND_DST16_16_EXT_QI, M32C_OPERAND_DST16_AN_INDIRECT_MOVA_HI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_MOVA_HI
|
||||
, M32C_OPERAND_DST16_16_16_AN_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_MOVA_HI
|
||||
, M32C_OPERAND_DST16_16_16_ABSOLUTE_MOVA_HI, M32C_OPERAND_DST16_16_MOVA_HI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI
|
||||
, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI
|
||||
, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI
|
||||
, M32C_OPERAND_DST32_16_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_16_24_UNPREFIXED_QI, M32C_OPERAND_DST32_16_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_16_24_UNPREFIXED_HI, M32C_OPERAND_DST32_16_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_16_24_UNPREFIXED_SI, M32C_OPERAND_DST32_16_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_UNPREFIXED_MULEX_HI
|
||||
, M32C_OPERAND_DST16_24_QI, M32C_OPERAND_DST16_24_HI, M32C_OPERAND_DST32_24_UNPREFIXED_QI, M32C_OPERAND_DST32_24_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_24_8_PREFIXED_QI, M32C_OPERAND_DST32_24_16_PREFIXED_QI, M32C_OPERAND_DST32_24_24_PREFIXED_QI, M32C_OPERAND_DST32_24_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_24_PREFIXED_HI, M32C_OPERAND_DST32_24_8_PREFIXED_HI, M32C_OPERAND_DST32_24_16_PREFIXED_HI, M32C_OPERAND_DST32_24_24_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_24_UNPREFIXED_SI, M32C_OPERAND_DST32_24_PREFIXED_SI, M32C_OPERAND_DST32_24_8_PREFIXED_SI, M32C_OPERAND_DST32_24_16_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_24_24_PREFIXED_SI, M32C_OPERAND_DST16_32_QI, M32C_OPERAND_DST16_32_HI, M32C_OPERAND_DST32_32_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_32_PREFIXED_QI, M32C_OPERAND_DST32_32_UNPREFIXED_HI, M32C_OPERAND_DST32_32_PREFIXED_HI, M32C_OPERAND_DST32_32_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_32_PREFIXED_SI, M32C_OPERAND_DST32_40_UNPREFIXED_QI, M32C_OPERAND_DST32_40_PREFIXED_QI, M32C_OPERAND_DST32_40_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_40_PREFIXED_HI, M32C_OPERAND_DST32_40_UNPREFIXED_SI, M32C_OPERAND_DST32_40_PREFIXED_SI, M32C_OPERAND_DST32_48_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_48_PREFIXED_HI, M32C_OPERAND_DST32_48_PREFIXED_SI, M32C_OPERAND_BIT16_16, M32C_OPERAND_BIT16_16_BASIC
|
||||
, M32C_OPERAND_BIT16_16_8, M32C_OPERAND_BIT16_16_16, M32C_OPERAND_BIT32_16_UNPREFIXED, M32C_OPERAND_BIT32_24_PREFIXED
|
||||
, M32C_OPERAND_BIT32_BASIC_UNPREFIXED, M32C_OPERAND_BIT32_16_8_UNPREFIXED, M32C_OPERAND_BIT32_16_16_UNPREFIXED, M32C_OPERAND_BIT32_16_24_UNPREFIXED
|
||||
, M32C_OPERAND_SRC16_2_S, M32C_OPERAND_SRC32_2_S_QI, M32C_OPERAND_SRC32_2_S_HI, M32C_OPERAND_DST16_3_S_8
|
||||
, M32C_OPERAND_DST16_3_S_16, M32C_OPERAND_SRCDST16_R0L_R0H_S, M32C_OPERAND_DST32_2_S_BASIC_QI, M32C_OPERAND_DST32_2_S_BASIC_HI
|
||||
, M32C_OPERAND_DST32_2_S_8_QI, M32C_OPERAND_DST32_2_S_16_QI, M32C_OPERAND_DST32_2_S_8_HI, M32C_OPERAND_DST32_2_S_16_HI
|
||||
, M32C_OPERAND_DST32_2_S_8_SI, M32C_OPERAND_DST32_2_S_16_SI, M32C_OPERAND_DST32_AN_S, M32C_OPERAND_BIT16_11_S
|
||||
, M32C_OPERAND_RN16_PUSH_S_ANYOF, M32C_OPERAND_AN16_PUSH_S_ANYOF, M32C_OPERAND_MAX
|
||||
, M32C_OPERAND_BIT32ANUNPREFIXED, M32C_OPERAND_A0, M32C_OPERAND_A1, M32C_OPERAND_A1A0
|
||||
, M32C_OPERAND_SB, M32C_OPERAND_FB, M32C_OPERAND_SP, M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL
|
||||
, M32C_OPERAND_REGSETPOP, M32C_OPERAND_REGSETPUSH, M32C_OPERAND_RN16_PUSH_S, M32C_OPERAND_AN16_PUSH_S
|
||||
, M32C_OPERAND_DSP_8_U6, M32C_OPERAND_DSP_8_U8, M32C_OPERAND_DSP_8_U16, M32C_OPERAND_DSP_8_S8
|
||||
, M32C_OPERAND_DSP_8_U24, M32C_OPERAND_DSP_10_U6, M32C_OPERAND_DSP_16_U8, M32C_OPERAND_DSP_16_U16
|
||||
, M32C_OPERAND_DSP_16_U20, M32C_OPERAND_DSP_16_U24, M32C_OPERAND_DSP_16_S8, M32C_OPERAND_DSP_16_S16
|
||||
, M32C_OPERAND_DSP_24_U8, M32C_OPERAND_DSP_24_U16, M32C_OPERAND_DSP_24_U20, M32C_OPERAND_DSP_24_U24
|
||||
, M32C_OPERAND_DSP_24_S8, M32C_OPERAND_DSP_24_S16, M32C_OPERAND_DSP_32_U8, M32C_OPERAND_DSP_32_U16
|
||||
, M32C_OPERAND_DSP_32_U24, M32C_OPERAND_DSP_32_U20, M32C_OPERAND_DSP_32_S8, M32C_OPERAND_DSP_32_S16
|
||||
, M32C_OPERAND_DSP_40_U8, M32C_OPERAND_DSP_40_S8, M32C_OPERAND_DSP_40_U16, M32C_OPERAND_DSP_40_S16
|
||||
, M32C_OPERAND_DSP_40_U24, M32C_OPERAND_DSP_48_U8, M32C_OPERAND_DSP_48_S8, M32C_OPERAND_DSP_48_U16
|
||||
, M32C_OPERAND_DSP_48_S16, M32C_OPERAND_DSP_48_U24, M32C_OPERAND_IMM_8_S4, M32C_OPERAND_IMM_SH_8_S4
|
||||
, M32C_OPERAND_IMM_8_QI, M32C_OPERAND_IMM_8_HI, M32C_OPERAND_IMM_12_S4, M32C_OPERAND_IMM_SH_12_S4
|
||||
, M32C_OPERAND_IMM_13_U3, M32C_OPERAND_IMM_20_S4, M32C_OPERAND_IMM_SH_20_S4, M32C_OPERAND_IMM_16_QI
|
||||
, M32C_OPERAND_IMM_16_HI, M32C_OPERAND_IMM_16_SI, M32C_OPERAND_IMM_24_QI, M32C_OPERAND_IMM_24_HI
|
||||
, M32C_OPERAND_IMM_24_SI, M32C_OPERAND_IMM_32_QI, M32C_OPERAND_IMM_32_SI, M32C_OPERAND_IMM_32_HI
|
||||
, M32C_OPERAND_IMM_40_QI, M32C_OPERAND_IMM_40_HI, M32C_OPERAND_IMM_40_SI, M32C_OPERAND_IMM_48_QI
|
||||
, M32C_OPERAND_IMM_48_HI, M32C_OPERAND_IMM_48_SI, M32C_OPERAND_IMM_56_QI, M32C_OPERAND_IMM_56_HI
|
||||
, M32C_OPERAND_IMM_64_HI, M32C_OPERAND_IMM1_S, M32C_OPERAND_IMM3_S, M32C_OPERAND_BITNO16R
|
||||
, M32C_OPERAND_BITNO32PREFIXED, M32C_OPERAND_BITNO32UNPREFIXED, M32C_OPERAND_BITBASE16_16_U8, M32C_OPERAND_BITBASE16_16_S8
|
||||
, M32C_OPERAND_BITBASE16_16_U16, M32C_OPERAND_BITBASE16_8_U11_S, M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED, M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED
|
||||
, M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED, M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED, M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED, M32C_OPERAND_BITBASE32_24_U11_PREFIXED
|
||||
, M32C_OPERAND_BITBASE32_24_S11_PREFIXED, M32C_OPERAND_BITBASE32_24_U19_PREFIXED, M32C_OPERAND_BITBASE32_24_S19_PREFIXED, M32C_OPERAND_BITBASE32_24_U27_PREFIXED
|
||||
, M32C_OPERAND_LAB_5_3, M32C_OPERAND_LAB32_JMP_S, M32C_OPERAND_LAB_8_8, M32C_OPERAND_LAB_8_16
|
||||
, M32C_OPERAND_LAB_8_24, M32C_OPERAND_LAB_16_8, M32C_OPERAND_LAB_24_8, M32C_OPERAND_LAB_32_8
|
||||
, M32C_OPERAND_LAB_40_8, M32C_OPERAND_SBIT, M32C_OPERAND_OBIT, M32C_OPERAND_ZBIT
|
||||
, M32C_OPERAND_CBIT, M32C_OPERAND_UBIT, M32C_OPERAND_IBIT, M32C_OPERAND_BBIT
|
||||
, M32C_OPERAND_DBIT, M32C_OPERAND_COND16_16, M32C_OPERAND_COND16_24, M32C_OPERAND_COND16_32
|
||||
, M32C_OPERAND_COND32_16, M32C_OPERAND_COND32_24, M32C_OPERAND_COND32_32, M32C_OPERAND_COND32_40
|
||||
, M32C_OPERAND_COND16C, M32C_OPERAND_COND16J, M32C_OPERAND_COND16J5, M32C_OPERAND_COND32
|
||||
, M32C_OPERAND_COND32J, M32C_OPERAND_SCCOND32, M32C_OPERAND_FLAGS16, M32C_OPERAND_FLAGS32
|
||||
, M32C_OPERAND_CR16, M32C_OPERAND_CR1_UNPREFIXED_32, M32C_OPERAND_CR1_PREFIXED_32, M32C_OPERAND_CR2_32
|
||||
, M32C_OPERAND_CR3_UNPREFIXED_32, M32C_OPERAND_CR3_PREFIXED_32, M32C_OPERAND_Z, M32C_OPERAND_S
|
||||
, M32C_OPERAND_Q, M32C_OPERAND_G, M32C_OPERAND_X, M32C_OPERAND_SIZE
|
||||
, M32C_OPERAND_BITINDEX, M32C_OPERAND_SRCINDEX, M32C_OPERAND_DSTINDEX, M32C_OPERAND_NOREMAINDER
|
||||
, M32C_OPERAND_SRC16_RN_DIRECT_QI, M32C_OPERAND_SRC16_RN_DIRECT_HI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_QI
|
||||
, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_HI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_SI
|
||||
, M32C_OPERAND_SRC16_AN_DIRECT_QI, M32C_OPERAND_SRC16_AN_DIRECT_HI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_HI
|
||||
, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_HI, M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_SI
|
||||
, M32C_OPERAND_SRC16_AN_INDIRECT_QI, M32C_OPERAND_SRC16_AN_INDIRECT_HI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_QI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_HI
|
||||
, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_SI, M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_HI, M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_SI
|
||||
, M32C_OPERAND_SRC16_16_8_SB_RELATIVE_QI, M32C_OPERAND_SRC16_16_16_SB_RELATIVE_QI, M32C_OPERAND_SRC16_16_8_FB_RELATIVE_QI, M32C_OPERAND_SRC16_16_8_AN_RELATIVE_QI
|
||||
, M32C_OPERAND_SRC16_16_16_AN_RELATIVE_QI, M32C_OPERAND_SRC16_16_8_SB_RELATIVE_HI, M32C_OPERAND_SRC16_16_16_SB_RELATIVE_HI, M32C_OPERAND_SRC16_16_8_FB_RELATIVE_HI
|
||||
, M32C_OPERAND_SRC16_16_8_AN_RELATIVE_HI, M32C_OPERAND_SRC16_16_16_AN_RELATIVE_HI, M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_QI
|
||||
, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_QI
|
||||
, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_HI
|
||||
, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_HI
|
||||
, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_SI
|
||||
, M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_SI
|
||||
, M32C_OPERAND_DSP20_16_U20_QI, M32C_OPERAND_DSP20_16_U20_A0_QI, M32C_OPERAND_DSP20_16_A1A0_QI, M32C_OPERAND_DSP20_24_U20_QI
|
||||
, M32C_OPERAND_DSP20_24_U20_A0_QI, M32C_OPERAND_DSP20_24_A1A0_QI, M32C_OPERAND_DSP20_32_U20_QI, M32C_OPERAND_DSP20_32_U20_A0_QI
|
||||
, M32C_OPERAND_DSP20_32_A1A0_QI, M32C_OPERAND_DSP20_16_U20_HI, M32C_OPERAND_DSP20_16_U20_A0_HI, M32C_OPERAND_DSP20_16_A1A0_HI
|
||||
, M32C_OPERAND_DSP20_24_U20_HI, M32C_OPERAND_DSP20_24_U20_A0_HI, M32C_OPERAND_DSP20_24_A1A0_HI, M32C_OPERAND_DSP20_32_U20_HI
|
||||
, M32C_OPERAND_DSP20_32_U20_A0_HI, M32C_OPERAND_DSP20_32_A1A0_HI, M32C_OPERAND_SRC16_16_16_ABSOLUTE_QI, M32C_OPERAND_SRC16_16_16_ABSOLUTE_HI
|
||||
, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_QI
|
||||
, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_SI
|
||||
, M32C_OPERAND_SRC16_2_S_8_SB_RELATIVE_QI, M32C_OPERAND_SRC16_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_SRC16_2_S_16_ABSOLUTE_QI, M32C_OPERAND_SRC32_2_S_8_SB_RELATIVE_QI
|
||||
, M32C_OPERAND_SRC32_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_SRC32_2_S_16_ABSOLUTE_QI, M32C_OPERAND_SRC32_2_S_8_SB_RELATIVE_HI, M32C_OPERAND_SRC32_2_S_8_FB_RELATIVE_HI
|
||||
, M32C_OPERAND_SRC32_2_S_16_ABSOLUTE_HI, M32C_OPERAND_DST16_RN_DIRECT_QI, M32C_OPERAND_DST16_RN_DIRECT_HI, M32C_OPERAND_DST16_RN_DIRECT_SI
|
||||
, M32C_OPERAND_DST16_RN_DIRECT_EXT_QI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_QI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_HI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_SI, M32C_OPERAND_DST32_RN_DIRECT_EXTUNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_RN_DIRECT_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_R3_DIRECT_UNPREFIXED_HI, M32C_OPERAND_DST16_AN_DIRECT_QI, M32C_OPERAND_DST16_AN_DIRECT_HI
|
||||
, M32C_OPERAND_DST16_AN_DIRECT_SI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_QI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_HI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_SI, M32C_OPERAND_DST16_AN_INDIRECT_QI
|
||||
, M32C_OPERAND_DST16_AN_INDIRECT_HI, M32C_OPERAND_DST16_AN_INDIRECT_SI, M32C_OPERAND_DST16_AN_INDIRECT_EXT_QI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_HI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_SI, M32C_OPERAND_DST32_AN_INDIRECT_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_EXTUNPREFIXED_HI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_QI
|
||||
, M32C_OPERAND_DST16_16_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_QI
|
||||
, M32C_OPERAND_DST16_24_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_24_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_24_8_AN_RELATIVE_QI
|
||||
, M32C_OPERAND_DST16_24_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_32_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_32_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_32_8_FB_RELATIVE_QI
|
||||
, M32C_OPERAND_DST16_32_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_32_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_40_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_40_16_SB_RELATIVE_QI
|
||||
, M32C_OPERAND_DST16_40_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_40_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_48_8_SB_RELATIVE_QI
|
||||
, M32C_OPERAND_DST16_48_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_48_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_48_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_48_16_AN_RELATIVE_QI
|
||||
, M32C_OPERAND_DST16_16_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_HI
|
||||
, M32C_OPERAND_DST16_16_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_24_8_FB_RELATIVE_HI
|
||||
, M32C_OPERAND_DST16_24_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_32_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_32_16_SB_RELATIVE_HI
|
||||
, M32C_OPERAND_DST16_32_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_32_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_40_8_SB_RELATIVE_HI
|
||||
, M32C_OPERAND_DST16_40_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_40_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_40_16_AN_RELATIVE_HI
|
||||
, M32C_OPERAND_DST16_48_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_48_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_48_8_AN_RELATIVE_HI
|
||||
, M32C_OPERAND_DST16_48_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_SI
|
||||
, M32C_OPERAND_DST16_16_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_SI
|
||||
, M32C_OPERAND_DST16_24_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_24_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_32_8_SB_RELATIVE_SI
|
||||
, M32C_OPERAND_DST16_32_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_32_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_32_16_AN_RELATIVE_SI
|
||||
, M32C_OPERAND_DST16_40_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_40_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_40_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_SI
|
||||
, M32C_OPERAND_DST16_40_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_48_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_48_8_FB_RELATIVE_SI
|
||||
, M32C_OPERAND_DST16_48_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_48_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_EXT_QI
|
||||
, M32C_OPERAND_DST16_16_8_FB_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_EXT_QI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST16_16_16_ABSOLUTE_QI, M32C_OPERAND_DST16_24_16_ABSOLUTE_QI, M32C_OPERAND_DST16_32_16_ABSOLUTE_QI
|
||||
, M32C_OPERAND_DST16_40_16_ABSOLUTE_QI, M32C_OPERAND_DST16_48_16_ABSOLUTE_QI, M32C_OPERAND_DST16_16_16_ABSOLUTE_HI, M32C_OPERAND_DST16_24_16_ABSOLUTE_HI
|
||||
, M32C_OPERAND_DST16_32_16_ABSOLUTE_HI, M32C_OPERAND_DST16_40_16_ABSOLUTE_HI, M32C_OPERAND_DST16_48_16_ABSOLUTE_HI, M32C_OPERAND_DST16_16_16_ABSOLUTE_SI
|
||||
, M32C_OPERAND_DST16_24_16_ABSOLUTE_SI, M32C_OPERAND_DST16_32_16_ABSOLUTE_SI, M32C_OPERAND_DST16_40_16_ABSOLUTE_SI, M32C_OPERAND_DST16_48_16_ABSOLUTE_SI
|
||||
, M32C_OPERAND_DST16_16_16_ABSOLUTE_EXT_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_HI, M32C_OPERAND_BIT16_RN_DIRECT, M32C_OPERAND_BIT32_RN_DIRECT_UNPREFIXED, M32C_OPERAND_BIT32_RN_DIRECT_PREFIXED
|
||||
, M32C_OPERAND_BIT16_AN_DIRECT, M32C_OPERAND_BIT32_AN_DIRECT_UNPREFIXED, M32C_OPERAND_BIT32_AN_DIRECT_PREFIXED, M32C_OPERAND_BIT16_AN_INDIRECT
|
||||
, M32C_OPERAND_BIT32_AN_INDIRECT_UNPREFIXED, M32C_OPERAND_BIT32_AN_INDIRECT_PREFIXED, M32C_OPERAND_BIT16_16_8_SB_RELATIVE, M32C_OPERAND_BIT16_16_16_SB_RELATIVE
|
||||
, M32C_OPERAND_BIT16_16_8_FB_RELATIVE, M32C_OPERAND_BIT16_16_8_AN_RELATIVE, M32C_OPERAND_BIT16_16_16_AN_RELATIVE, M32C_OPERAND_BIT32_16_11_SB_RELATIVE_UNPREFIXED
|
||||
, M32C_OPERAND_BIT32_16_19_SB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_19_FB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_11_AN_RELATIVE_UNPREFIXED
|
||||
, M32C_OPERAND_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_27_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_24_11_SB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_19_SB_RELATIVE_PREFIXED
|
||||
, M32C_OPERAND_BIT32_24_11_FB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_19_FB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_11_AN_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_19_AN_RELATIVE_PREFIXED
|
||||
, M32C_OPERAND_BIT32_24_27_AN_RELATIVE_PREFIXED, M32C_OPERAND_BIT16_11_SB_RELATIVE_S, M32C_OPERAND_RN16_PUSH_S_DERIVED, M32C_OPERAND_AN16_PUSH_S_DERIVED
|
||||
, M32C_OPERAND_BIT16_16_16_ABSOLUTE, M32C_OPERAND_BIT32_16_19_ABSOLUTE_UNPREFIXED, M32C_OPERAND_BIT32_16_27_ABSOLUTE_UNPREFIXED, M32C_OPERAND_BIT32_24_19_ABSOLUTE_PREFIXED
|
||||
, M32C_OPERAND_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_OPERAND_DST16_3_S_R0L_DIRECT_QI, M32C_OPERAND_DST16_3_S_R0H_DIRECT_QI, M32C_OPERAND_DST16_3_S_8_8_SB_RELATIVE_QI
|
||||
, M32C_OPERAND_DST16_3_S_8_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_8_16_ABSOLUTE_QI, M32C_OPERAND_DST16_3_S_16_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_16_8_FB_RELATIVE_QI
|
||||
, M32C_OPERAND_DST16_3_S_16_16_ABSOLUTE_QI, M32C_OPERAND_SRCDST16_R0L_R0H_S_DERIVED, M32C_OPERAND_DST32_2_S_R0L_DIRECT_QI, M32C_OPERAND_DST32_2_S_R0_DIRECT_HI
|
||||
, M32C_OPERAND_DST32_1_S_A0_DIRECT_HI, M32C_OPERAND_DST32_1_S_A1_DIRECT_HI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_QI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_QI
|
||||
, M32C_OPERAND_DST32_2_S_16_ABSOLUTE_QI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_HI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_HI, M32C_OPERAND_DST32_2_S_16_ABSOLUTE_HI
|
||||
, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_SI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_SI, M32C_OPERAND_DST32_2_S_16_ABSOLUTE_SI, M32C_OPERAND_SRC16_BASIC_QI
|
||||
, M32C_OPERAND_SRC16_BASIC_HI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_QI, M32C_OPERAND_SRC32_BASIC_PREFIXED_QI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_HI
|
||||
, M32C_OPERAND_SRC32_BASIC_PREFIXED_HI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_SI, M32C_OPERAND_SRC32_BASIC_PREFIXED_SI, M32C_OPERAND_SRC32_BASIC_EXTPREFIXED_QI
|
||||
, M32C_OPERAND_SRC16_16_8_QI, M32C_OPERAND_SRC16_16_16_QI, M32C_OPERAND_SRC16_16_8_HI, M32C_OPERAND_SRC16_16_16_HI
|
||||
, M32C_OPERAND_SRC32_16_8_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_UNPREFIXED_HI
|
||||
, M32C_OPERAND_SRC32_16_16_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_UNPREFIXED_SI
|
||||
, M32C_OPERAND_SRC32_16_24_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_8_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_PREFIXED_QI, M32C_OPERAND_SRC32_24_24_PREFIXED_QI
|
||||
, M32C_OPERAND_SRC32_24_8_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_PREFIXED_SI
|
||||
, M32C_OPERAND_SRC32_24_16_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_PREFIXED_SI, M32C_OPERAND_DST16_BASIC_QI, M32C_OPERAND_DST16_BASIC_HI
|
||||
, M32C_OPERAND_DST16_BASIC_SI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_QI, M32C_OPERAND_DST32_BASIC_PREFIXED_QI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_BASIC_PREFIXED_HI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_SI, M32C_OPERAND_DST32_BASIC_PREFIXED_SI, M32C_OPERAND_DST16_16_QI
|
||||
, M32C_OPERAND_DST16_16_8_QI, M32C_OPERAND_DST16_16_16_QI, M32C_OPERAND_DST16_16_HI, M32C_OPERAND_DST16_16_8_HI
|
||||
, M32C_OPERAND_DST16_16_16_HI, M32C_OPERAND_DST16_16_SI, M32C_OPERAND_DST16_16_8_SI, M32C_OPERAND_DST16_16_16_SI
|
||||
, M32C_OPERAND_DST16_16_EXT_QI, M32C_OPERAND_DST16_AN_INDIRECT_MOVA_HI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_MOVA_HI
|
||||
, M32C_OPERAND_DST16_16_8_SB_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_16_ABSOLUTE_MOVA_HI
|
||||
, M32C_OPERAND_DST16_16_MOVA_HI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI
|
||||
, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI
|
||||
, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_UNPREFIXED_MOVA_SI
|
||||
, M32C_OPERAND_DST32_16_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_UNPREFIXED_QI
|
||||
, M32C_OPERAND_DST32_16_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_UNPREFIXED_HI
|
||||
, M32C_OPERAND_DST32_16_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_UNPREFIXED_SI, M32C_OPERAND_DST32_16_24_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_16_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_UNPREFIXED_MULEX_HI, M32C_OPERAND_DST16_24_QI
|
||||
, M32C_OPERAND_DST16_24_HI, M32C_OPERAND_DST32_24_UNPREFIXED_QI, M32C_OPERAND_DST32_24_PREFIXED_QI, M32C_OPERAND_DST32_24_8_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_24_16_PREFIXED_QI, M32C_OPERAND_DST32_24_24_PREFIXED_QI, M32C_OPERAND_DST32_24_UNPREFIXED_HI, M32C_OPERAND_DST32_24_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_24_8_PREFIXED_HI, M32C_OPERAND_DST32_24_16_PREFIXED_HI, M32C_OPERAND_DST32_24_24_PREFIXED_HI, M32C_OPERAND_DST32_24_UNPREFIXED_SI
|
||||
, M32C_OPERAND_DST32_24_PREFIXED_SI, M32C_OPERAND_DST32_24_8_PREFIXED_SI, M32C_OPERAND_DST32_24_16_PREFIXED_SI, M32C_OPERAND_DST32_24_24_PREFIXED_SI
|
||||
, M32C_OPERAND_DST16_32_QI, M32C_OPERAND_DST16_32_HI, M32C_OPERAND_DST32_32_UNPREFIXED_QI, M32C_OPERAND_DST32_32_PREFIXED_QI
|
||||
, M32C_OPERAND_DST32_32_UNPREFIXED_HI, M32C_OPERAND_DST32_32_PREFIXED_HI, M32C_OPERAND_DST32_32_UNPREFIXED_SI, M32C_OPERAND_DST32_32_PREFIXED_SI
|
||||
, M32C_OPERAND_DST32_40_UNPREFIXED_QI, M32C_OPERAND_DST32_40_PREFIXED_QI, M32C_OPERAND_DST32_40_UNPREFIXED_HI, M32C_OPERAND_DST32_40_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_40_UNPREFIXED_SI, M32C_OPERAND_DST32_40_PREFIXED_SI, M32C_OPERAND_DST32_48_PREFIXED_QI, M32C_OPERAND_DST32_48_PREFIXED_HI
|
||||
, M32C_OPERAND_DST32_48_PREFIXED_SI, M32C_OPERAND_BIT16_16, M32C_OPERAND_BIT16_16_BASIC, M32C_OPERAND_BIT16_16_8
|
||||
, M32C_OPERAND_BIT16_16_16, M32C_OPERAND_BIT32_16_UNPREFIXED, M32C_OPERAND_BIT32_24_PREFIXED, M32C_OPERAND_BIT32_BASIC_UNPREFIXED
|
||||
, M32C_OPERAND_BIT32_16_8_UNPREFIXED, M32C_OPERAND_BIT32_16_16_UNPREFIXED, M32C_OPERAND_BIT32_16_24_UNPREFIXED, M32C_OPERAND_SRC16_2_S
|
||||
, M32C_OPERAND_SRC32_2_S_QI, M32C_OPERAND_SRC32_2_S_HI, M32C_OPERAND_DST16_3_S_8, M32C_OPERAND_DST16_3_S_16
|
||||
, M32C_OPERAND_SRCDST16_R0L_R0H_S, M32C_OPERAND_DST32_2_S_BASIC_QI, M32C_OPERAND_DST32_2_S_BASIC_HI, M32C_OPERAND_DST32_2_S_8_QI
|
||||
, M32C_OPERAND_DST32_2_S_16_QI, M32C_OPERAND_DST32_2_S_8_HI, M32C_OPERAND_DST32_2_S_16_HI, M32C_OPERAND_DST32_2_S_8_SI
|
||||
, M32C_OPERAND_DST32_2_S_16_SI, M32C_OPERAND_DST32_AN_S, M32C_OPERAND_BIT16_11_S, M32C_OPERAND_RN16_PUSH_S_ANYOF
|
||||
, M32C_OPERAND_AN16_PUSH_S_ANYOF, M32C_OPERAND_MAX
|
||||
} CGEN_OPERAND_TYPE;
|
||||
|
||||
/* Number of operands types. */
|
||||
#define MAX_OPERANDS 870
|
||||
#define MAX_OPERANDS 889
|
||||
|
||||
/* Maximum number of operands referenced by any insn. */
|
||||
#define MAX_OPERAND_INSTANCES 8
|
||||
|
||||
@ -299,6 +299,9 @@ m32c_cgen_print_operand (CGEN_CPU_DESC cd,
|
||||
case M32C_OPERAND_A1 :
|
||||
print_keyword (cd, info, & m32c_cgen_opval_h_a1, 0, 0);
|
||||
break;
|
||||
case M32C_OPERAND_A1A0 :
|
||||
print_keyword (cd, info, & m32c_cgen_opval_h_ar_SI, 0, 0);
|
||||
break;
|
||||
case M32C_OPERAND_AN16_PUSH_S :
|
||||
print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_4_1, 0);
|
||||
break;
|
||||
|
||||
@ -562,6 +562,8 @@ m32c_cgen_insert_operand (CGEN_CPU_DESC cd,
|
||||
break;
|
||||
case M32C_OPERAND_A1 :
|
||||
break;
|
||||
case M32C_OPERAND_A1A0 :
|
||||
break;
|
||||
case M32C_OPERAND_AN16_PUSH_S :
|
||||
errmsg = insert_normal (cd, fields->f_4_1, 0, 0, 4, 1, 32, total_length, buffer);
|
||||
break;
|
||||
@ -1709,6 +1711,8 @@ m32c_cgen_extract_operand (CGEN_CPU_DESC cd,
|
||||
break;
|
||||
case M32C_OPERAND_A1 :
|
||||
break;
|
||||
case M32C_OPERAND_A1A0 :
|
||||
break;
|
||||
case M32C_OPERAND_AN16_PUSH_S :
|
||||
length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 1, 32, total_length, pc, & fields->f_4_1);
|
||||
break;
|
||||
@ -2818,6 +2822,9 @@ m32c_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
case M32C_OPERAND_A1 :
|
||||
value = 0;
|
||||
break;
|
||||
case M32C_OPERAND_A1A0 :
|
||||
value = 0;
|
||||
break;
|
||||
case M32C_OPERAND_AN16_PUSH_S :
|
||||
value = fields->f_4_1;
|
||||
break;
|
||||
@ -3399,6 +3406,9 @@ m32c_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
case M32C_OPERAND_A1 :
|
||||
value = 0;
|
||||
break;
|
||||
case M32C_OPERAND_A1A0 :
|
||||
value = 0;
|
||||
break;
|
||||
case M32C_OPERAND_AN16_PUSH_S :
|
||||
value = fields->f_4_1;
|
||||
break;
|
||||
@ -3985,6 +3995,8 @@ m32c_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
break;
|
||||
case M32C_OPERAND_A1 :
|
||||
break;
|
||||
case M32C_OPERAND_A1A0 :
|
||||
break;
|
||||
case M32C_OPERAND_AN16_PUSH_S :
|
||||
fields->f_4_1 = value;
|
||||
break;
|
||||
@ -4544,6 +4556,8 @@ m32c_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
||||
break;
|
||||
case M32C_OPERAND_A1 :
|
||||
break;
|
||||
case M32C_OPERAND_A1A0 :
|
||||
break;
|
||||
case M32C_OPERAND_AN16_PUSH_S :
|
||||
fields->f_4_1 = value;
|
||||
break;
|
||||
|
||||
1064
opcodes/m32c-opc.c
1064
opcodes/m32c-opc.c
File diff suppressed because it is too large
Load Diff
@ -286,9 +286,9 @@ typedef enum cgen_insn_type {
|
||||
, M32C_INSN_XCHG16W_R2_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_XCHG16W_R2_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_XCHG16W_R2_DST16_16_16_ABSOLUTE_HI, M32C_INSN_XCHG16W_R1_DST16_RN_DIRECT_HI
|
||||
, M32C_INSN_XCHG16W_R1_DST16_AN_DIRECT_HI, M32C_INSN_XCHG16W_R1_DST16_AN_INDIRECT_HI, M32C_INSN_XCHG16W_R1_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_XCHG16W_R1_DST16_16_16_AN_RELATIVE_HI
|
||||
, M32C_INSN_XCHG16W_R1_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_XCHG16W_R1_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_XCHG16W_R1_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_XCHG16W_R1_DST16_16_16_ABSOLUTE_HI
|
||||
, M32C_INSN_XCHG16W_R0_DST16_RN_DIRECT_QI, M32C_INSN_XCHG16W_R0_DST16_AN_DIRECT_QI, M32C_INSN_XCHG16W_R0_DST16_AN_INDIRECT_QI, M32C_INSN_XCHG16W_R0_DST16_16_8_AN_RELATIVE_QI
|
||||
, M32C_INSN_XCHG16W_R0_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_XCHG16W_R0_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_XCHG16W_R0_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_XCHG16W_R0_DST16_16_8_FB_RELATIVE_QI
|
||||
, M32C_INSN_XCHG16W_R0_DST16_16_16_ABSOLUTE_QI, M32C_INSN_XCHG16B_R1H_DST16_RN_DIRECT_QI, M32C_INSN_XCHG16B_R1H_DST16_AN_DIRECT_QI, M32C_INSN_XCHG16B_R1H_DST16_AN_INDIRECT_QI
|
||||
, M32C_INSN_XCHG16W_R0_DST16_RN_DIRECT_HI, M32C_INSN_XCHG16W_R0_DST16_AN_DIRECT_HI, M32C_INSN_XCHG16W_R0_DST16_AN_INDIRECT_HI, M32C_INSN_XCHG16W_R0_DST16_16_8_AN_RELATIVE_HI
|
||||
, M32C_INSN_XCHG16W_R0_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_XCHG16W_R0_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_XCHG16W_R0_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_XCHG16W_R0_DST16_16_8_FB_RELATIVE_HI
|
||||
, M32C_INSN_XCHG16W_R0_DST16_16_16_ABSOLUTE_HI, M32C_INSN_XCHG16B_R1H_DST16_RN_DIRECT_QI, M32C_INSN_XCHG16B_R1H_DST16_AN_DIRECT_QI, M32C_INSN_XCHG16B_R1H_DST16_AN_INDIRECT_QI
|
||||
, M32C_INSN_XCHG16B_R1H_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_XCHG16B_R1H_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_XCHG16B_R1H_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_XCHG16B_R1H_DST16_16_16_SB_RELATIVE_QI
|
||||
, M32C_INSN_XCHG16B_R1H_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_XCHG16B_R1H_DST16_16_16_ABSOLUTE_QI, M32C_INSN_XCHG16B_R1L_DST16_RN_DIRECT_QI, M32C_INSN_XCHG16B_R1L_DST16_AN_DIRECT_QI
|
||||
, M32C_INSN_XCHG16B_R1L_DST16_AN_INDIRECT_QI, M32C_INSN_XCHG16B_R1L_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_XCHG16B_R1L_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_XCHG16B_R1L_DST16_16_8_SB_RELATIVE_QI
|
||||
@ -678,17 +678,17 @@ typedef enum cgen_insn_type {
|
||||
, M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI
|
||||
, M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI
|
||||
, M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI
|
||||
, M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ROT32_W_DST_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_SI
|
||||
, M32C_INSN_ROT32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI
|
||||
, M32C_INSN_ROT32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI
|
||||
, M32C_INSN_ROT32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_SI
|
||||
, M32C_INSN_ROT32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI
|
||||
, M32C_INSN_ROT32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_ROT32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI
|
||||
, M32C_INSN_ROT32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_ROT16_W_DST_DST16_RN_DIRECT_HI, M32C_INSN_ROT16_W_DST_DST16_AN_DIRECT_HI, M32C_INSN_ROT16_W_DST_DST16_AN_INDIRECT_HI
|
||||
, M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ROT32_W_DST_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_HI
|
||||
, M32C_INSN_ROT32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_INSN_ROT32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_HI
|
||||
, M32C_INSN_ROT32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ROT32_B_DST_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_QI
|
||||
, M32C_INSN_ROT32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI
|
||||
, M32C_INSN_ROT32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_ROT32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_QI
|
||||
, M32C_INSN_ROT32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_ROT16_W_DST_DST16_RN_DIRECT_HI, M32C_INSN_ROT16_W_DST_DST16_AN_DIRECT_HI, M32C_INSN_ROT16_W_DST_DST16_AN_INDIRECT_HI
|
||||
, M32C_INSN_ROT16_W_DST_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ROT16_W_DST_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ROT16_W_DST_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_ROT16_W_DST_DST16_16_16_SB_RELATIVE_HI
|
||||
, M32C_INSN_ROT16_W_DST_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ROT16_W_DST_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ROT16_B_DST_DST16_RN_DIRECT_HI, M32C_INSN_ROT16_B_DST_DST16_AN_DIRECT_HI
|
||||
, M32C_INSN_ROT16_B_DST_DST16_AN_INDIRECT_HI, M32C_INSN_ROT16_B_DST_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_ROT16_B_DST_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_ROT16_B_DST_DST16_16_8_SB_RELATIVE_HI
|
||||
, M32C_INSN_ROT16_B_DST_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_ROT16_B_DST_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ROT16_B_DST_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI
|
||||
, M32C_INSN_ROT16_W_DST_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_ROT16_W_DST_DST16_16_16_ABSOLUTE_HI, M32C_INSN_ROT16_B_DST_DST16_RN_DIRECT_QI, M32C_INSN_ROT16_B_DST_DST16_AN_DIRECT_QI
|
||||
, M32C_INSN_ROT16_B_DST_DST16_AN_INDIRECT_QI, M32C_INSN_ROT16_B_DST_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_ROT16_B_DST_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_ROT16_B_DST_DST16_16_8_SB_RELATIVE_QI
|
||||
, M32C_INSN_ROT16_B_DST_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_ROT16_B_DST_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_ROT16_B_DST_DST16_16_16_ABSOLUTE_QI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI
|
||||
, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI
|
||||
, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI
|
||||
@ -1576,16 +1576,34 @@ typedef enum cgen_insn_type {
|
||||
, M32C_INSN_MAX32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI
|
||||
, M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI
|
||||
, M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_INSN_MAX32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI
|
||||
, M32C_INSN_MAX32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_STE16_W_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_STE16_W_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_STE16_W_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_HI
|
||||
, M32C_INSN_STE16_W_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_STE16_W_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_STE16_W_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_STE16_W_DST_DSPSP_BASIC_DST16_RN_DIRECT_HI
|
||||
, M32C_INSN_STE16_W_DST_DSPSP_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_STE16_W_DST_DSPSP_BASIC_DST16_AN_INDIRECT_HI, M32C_INSN_STE16_B_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_STE16_B_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_QI
|
||||
, M32C_INSN_STE16_B_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_STE16_B_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_STE16_B_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_STE16_B_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_QI
|
||||
, M32C_INSN_STE16_B_DST_DSPSP_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_STE16_B_DST_DSPSP_BASIC_DST16_AN_DIRECT_QI, M32C_INSN_STE16_B_DST_DSPSP_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_LDE16_W_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_HI
|
||||
, M32C_INSN_LDE16_W_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_LDE16_W_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_LDE16_W_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_LDE16_W_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_HI
|
||||
, M32C_INSN_LDE16_W_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_HI, M32C_INSN_LDE16_W_DST_DSPSP_BASIC_DST16_RN_DIRECT_HI, M32C_INSN_LDE16_W_DST_DSPSP_BASIC_DST16_AN_DIRECT_HI, M32C_INSN_LDE16_W_DST_DSPSP_BASIC_DST16_AN_INDIRECT_HI
|
||||
, M32C_INSN_LDE16_B_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_LDE16_B_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_LDE16_B_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_LDE16_B_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_QI
|
||||
, M32C_INSN_LDE16_B_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_LDE16_B_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_LDE16_B_DST_DSPSP_BASIC_DST16_RN_DIRECT_QI, M32C_INSN_LDE16_B_DST_DSPSP_BASIC_DST16_AN_DIRECT_QI
|
||||
, M32C_INSN_LDE16_B_DST_DSPSP_BASIC_DST16_AN_INDIRECT_QI, M32C_INSN_STC32_SRC_CR3_DST32_RN_DIRECT_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_AN_DIRECT_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_AN_INDIRECT_PREFIXED_SI
|
||||
, M32C_INSN_MAX32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_ABSOLUTE_HI
|
||||
, M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_ABSOLUTE_HI, M32C_INSN_STE_W_16_16_U20_DST16_16_16_AN_RELATIVE_HI
|
||||
, M32C_INSN_STE_W_16_16_U20_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_STE_W_16_16_U20_DST16_16_16_ABSOLUTE_HI, M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_SB_RELATIVE_HI
|
||||
, M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_FB_RELATIVE_HI
|
||||
, M32C_INSN_STE_W_16_8_U20_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_STE_W_16_8_U20_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_STE_W_16_8_U20_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_STE_W_BASIC_A1A0_DST16_RN_DIRECT_HI
|
||||
, M32C_INSN_STE_W_BASIC_A1A0_DST16_AN_DIRECT_HI, M32C_INSN_STE_W_BASIC_A1A0_DST16_AN_INDIRECT_HI, M32C_INSN_STE_W_BASIC_U20A0_DST16_RN_DIRECT_HI, M32C_INSN_STE_W_BASIC_U20A0_DST16_AN_DIRECT_HI
|
||||
, M32C_INSN_STE_W_BASIC_U20A0_DST16_AN_INDIRECT_HI, M32C_INSN_STE_W_BASIC_U20_DST16_RN_DIRECT_HI, M32C_INSN_STE_W_BASIC_U20_DST16_AN_DIRECT_HI, M32C_INSN_STE_W_BASIC_U20_DST16_AN_INDIRECT_HI
|
||||
, M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_ABSOLUTE_QI, M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_AN_RELATIVE_QI
|
||||
, M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_ABSOLUTE_QI, M32C_INSN_STE_B_16_16_U20_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_STE_B_16_16_U20_DST16_16_16_SB_RELATIVE_QI
|
||||
, M32C_INSN_STE_B_16_16_U20_DST16_16_16_ABSOLUTE_QI, M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_FB_RELATIVE_QI
|
||||
, M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_STE_B_16_8_U20_DST16_16_8_AN_RELATIVE_QI
|
||||
, M32C_INSN_STE_B_16_8_U20_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_STE_B_16_8_U20_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_STE_B_BASIC_A1A0_DST16_RN_DIRECT_QI, M32C_INSN_STE_B_BASIC_A1A0_DST16_AN_DIRECT_QI
|
||||
, M32C_INSN_STE_B_BASIC_A1A0_DST16_AN_INDIRECT_QI, M32C_INSN_STE_B_BASIC_U20A0_DST16_RN_DIRECT_QI, M32C_INSN_STE_B_BASIC_U20A0_DST16_AN_DIRECT_QI, M32C_INSN_STE_B_BASIC_U20A0_DST16_AN_INDIRECT_QI
|
||||
, M32C_INSN_STE_B_BASIC_U20_DST16_RN_DIRECT_QI, M32C_INSN_STE_B_BASIC_U20_DST16_AN_DIRECT_QI, M32C_INSN_STE_B_BASIC_U20_DST16_AN_INDIRECT_QI, M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_AN_RELATIVE_HI
|
||||
, M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_ABSOLUTE_HI, M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_SB_RELATIVE_HI
|
||||
, M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_ABSOLUTE_HI, M32C_INSN_LDE_W_16_16_U20_DST16_16_16_AN_RELATIVE_HI, M32C_INSN_LDE_W_16_16_U20_DST16_16_16_SB_RELATIVE_HI, M32C_INSN_LDE_W_16_16_U20_DST16_16_16_ABSOLUTE_HI
|
||||
, M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_AN_RELATIVE_HI
|
||||
, M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_SB_RELATIVE_HI, M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_LDE_W_16_8_U20_DST16_16_8_AN_RELATIVE_HI, M32C_INSN_LDE_W_16_8_U20_DST16_16_8_SB_RELATIVE_HI
|
||||
, M32C_INSN_LDE_W_16_8_U20_DST16_16_8_FB_RELATIVE_HI, M32C_INSN_LDE_W_BASIC_A1A0_DST16_RN_DIRECT_HI, M32C_INSN_LDE_W_BASIC_A1A0_DST16_AN_DIRECT_HI, M32C_INSN_LDE_W_BASIC_A1A0_DST16_AN_INDIRECT_HI
|
||||
, M32C_INSN_LDE_W_BASIC_U20A0_DST16_RN_DIRECT_HI, M32C_INSN_LDE_W_BASIC_U20A0_DST16_AN_DIRECT_HI, M32C_INSN_LDE_W_BASIC_U20A0_DST16_AN_INDIRECT_HI, M32C_INSN_LDE_W_BASIC_U20_DST16_RN_DIRECT_HI
|
||||
, M32C_INSN_LDE_W_BASIC_U20_DST16_AN_DIRECT_HI, M32C_INSN_LDE_W_BASIC_U20_DST16_AN_INDIRECT_HI, M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_SB_RELATIVE_QI
|
||||
, M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_ABSOLUTE_QI, M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_ABSOLUTE_QI
|
||||
, M32C_INSN_LDE_B_16_16_U20_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_LDE_B_16_16_U20_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_LDE_B_16_16_U20_DST16_16_16_ABSOLUTE_QI, M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_AN_RELATIVE_QI
|
||||
, M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_SB_RELATIVE_QI
|
||||
, M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_LDE_B_16_8_U20_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_LDE_B_16_8_U20_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_LDE_B_16_8_U20_DST16_16_8_FB_RELATIVE_QI
|
||||
, M32C_INSN_LDE_B_BASIC_A1A0_DST16_RN_DIRECT_QI, M32C_INSN_LDE_B_BASIC_A1A0_DST16_AN_DIRECT_QI, M32C_INSN_LDE_B_BASIC_A1A0_DST16_AN_INDIRECT_QI, M32C_INSN_LDE_B_BASIC_U20A0_DST16_RN_DIRECT_QI
|
||||
, M32C_INSN_LDE_B_BASIC_U20A0_DST16_AN_DIRECT_QI, M32C_INSN_LDE_B_BASIC_U20A0_DST16_AN_INDIRECT_QI, M32C_INSN_LDE_B_BASIC_U20_DST16_RN_DIRECT_QI, M32C_INSN_LDE_B_BASIC_U20_DST16_AN_DIRECT_QI
|
||||
, M32C_INSN_LDE_B_BASIC_U20_DST16_AN_INDIRECT_QI, M32C_INSN_STC32_SRC_CR3_DST32_RN_DIRECT_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_AN_DIRECT_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_AN_INDIRECT_PREFIXED_SI
|
||||
, M32C_INSN_STC32_SRC_CR3_DST32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_8_SB_RELATIVE_PREFIXED_SI
|
||||
, M32C_INSN_STC32_SRC_CR3_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_16_FB_RELATIVE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR3_DST32_24_16_ABSOLUTE_PREFIXED_SI
|
||||
, M32C_INSN_STC32_SRC_CR3_DST32_24_24_ABSOLUTE_PREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_STC32_SRC_CR2_DST32_AN_INDIRECT_UNPREFIXED_SI
|
||||
|
||||
Loading…
Reference in New Issue
Block a user