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Tue Jun 23 11:14:04 1998 Michael Snyder <msnyder@cleaver.cygnus.com>
* config/mips/tm-irix5.h: Modify to work better on irix 6, by making FP registers 8 bytes instead of 4. REGISTER_BYTES: redefine. REGISTER_BYTE(): redefine. REGISTER_VIRTUAL_TYPE: redefine. MIPS_LAST_ARG_REGNUM: redefine. * irix5-nat.c (fetch_core_registers): read 8 bytes per FP register. * mips-tdep.c (FP_REGISTER_DOUBLE): new macro to distinguish targets with 8-byte FP registers (don't use TARGET_MIPS64). (STACK_ARGSIZE): new macro, how much space is taken up on the stack for each function argument (don't use TARGET_MIPS64). (mips_push_arguments): modify logic to work better on Irix 6 (n32 ABI).
This commit is contained in:
Michael Snyder
parent
ebb6416960
commit
a00dfa360a
@ -1,3 +1,17 @@
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Tue Jun 23 11:14:04 1998 Michael Snyder <msnyder@cleaver.cygnus.com>
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* config/mips/tm-irix5.h: Modify to work better on irix 6, by
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making FP registers 8 bytes instead of 4.
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REGISTER_BYTES: redefine. REGISTER_BYTE(): redefine.
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REGISTER_VIRTUAL_TYPE: redefine. MIPS_LAST_ARG_REGNUM: redefine.
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* irix5-nat.c (fetch_core_registers): read 8 bytes per FP register.
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* mips-tdep.c (FP_REGISTER_DOUBLE): new macro to distinguish
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targets with 8-byte FP registers (don't use TARGET_MIPS64).
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(STACK_ARGSIZE): new macro, how much space is taken up on the
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stack for each function argument (don't use TARGET_MIPS64).
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(mips_push_arguments): modify logic to work better on Irix 6
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(n32 ABI).
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Tue Jun 23 12:29:53 1998 Jillian Ye <jillian@cygnus.com>
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* configure.in: Add -lXext to mips_extra_libs
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@ -19,6 +19,37 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "mips/tm-irix3.h"
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#if defined (_MIPS_SIM_NABI32) && _MIPS_SIM == _MIPS_SIM_NABI32
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/*
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* Irix 6 (n32 ABI) has 32-bit GP regs and 64-bit FP regs
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*/
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#undef REGISTER_BYTES
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#define REGISTER_BYTES (MIPS_NUMREGS * 8 + (NUM_REGS - MIPS_NUMREGS) * MIPS_REGSIZE)
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#undef REGISTER_BYTE
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#define REGISTER_BYTE(N) \
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(((N) < FP0_REGNUM) ? (N) * MIPS_REGSIZE : \
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((N) < FP0_REGNUM + 32) ? \
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FP0_REGNUM * MIPS_REGSIZE + \
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((N) - FP0_REGNUM) * sizeof(double) : \
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32 * sizeof(double) + ((N) - 32) * MIPS_REGSIZE)
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#undef REGISTER_VIRTUAL_TYPE
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#define REGISTER_VIRTUAL_TYPE(N) \
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(((N) >= FP0_REGNUM && (N) < FP0_REGNUM+32) ? builtin_type_double \
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: ((N) == 32 /*SR*/) ? builtin_type_uint32 \
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: ((N) >= 70 && (N) <= 89) ? builtin_type_uint32 \
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: builtin_type_int)
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#undef MIPS_LAST_ARG_REGNUM
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#define MIPS_LAST_ARG_REGNUM 11 /* N32 uses R4 through R11 for args */
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#undef MIPS_NUM_ARG_REGS
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#define MIPS_NUM_ARG_REGS 8
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#endif /* N32 */
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/* When calling functions on Irix 5 (or any MIPS SVR4 ABI compliant
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platform) $25 must hold the function address. Dest_Reg is a macro
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used in CALL_DUMMY in tm-mips.h. */
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@ -192,7 +192,8 @@ fetch_core_registers (core_reg_sect, core_reg_size, which, reg_addr)
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{
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memcpy ((char *)registers, core_reg_sect, core_reg_size);
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}
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else if (core_reg_size == (2 * REGISTER_BYTES) && MIPS_REGSIZE == 4)
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else if (MIPS_REGSIZE == 4 &&
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core_reg_size == (2 * MIPS_REGSIZE) * NUM_REGS)
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{
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/* This is a core file from a N32 executable, 64 bits are saved
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for all registers. */
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@ -210,7 +211,20 @@ fetch_core_registers (core_reg_sect, core_reg_size, which, reg_addr)
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*dstp++ = *srcp++;
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*dstp++ = *srcp++;
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*dstp++ = *srcp++;
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srcp += 4;
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if (REGISTER_RAW_SIZE(regno) == 4)
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{
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/* copying 4 bytes from eight bytes?
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I don't see how this can be right... */
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srcp += 4;
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}
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else
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{
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/* copy all 8 bytes (sizeof(double)) */
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*dstp++ = *srcp++;
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*dstp++ = *srcp++;
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*dstp++ = *srcp++;
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*dstp++ = *srcp++;
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}
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}
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else
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{
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@ -1,5 +1,5 @@
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/* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
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Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996
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Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
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Free Software Foundation, Inc.
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Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
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and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
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@ -38,6 +38,9 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#define VM_MIN_ADDRESS (CORE_ADDR)0x400000
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/* Do not use "TARGET_IS_MIPS64" to test the size of floating point registers */
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#define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8)
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/* FIXME: Put this declaration in frame.h. */
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extern struct obstack frame_cache_obstack;
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@ -282,6 +285,9 @@ mips32_decode_reg_save (inst, gen_mask, float_mask)
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if ((inst & 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
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|| (inst & 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
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/* start-sanitize-r5900 */
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|| (inst & 0xffe00000) == 0x7fa00000 /* sq reg,n($sp) */
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/* end-sanitize-r5900 */
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|| (inst & 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
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{
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/* It might be possible to use the instruction to
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@ -916,6 +922,15 @@ mips_find_saved_regs (fci)
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{
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fci->saved_regs->regs[ireg] = reg_position;
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reg_position -= MIPS_REGSIZE;
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/* start-sanitize-r5900 */
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#ifdef R5900_128BIT_GPR_HACK
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/* Gross. The r5900 has 128bit wide registers, but MIPS_REGSIZE is
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still 64bits. See the comments in tm.h for a discussion of the
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various problems this causes. */
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if (ireg <= RA_REGNUM)
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reg_position -= MIPS_REGSIZE;
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#endif
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/* end-sanitize-r5900 */
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}
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/* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
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@ -1395,6 +1410,15 @@ mips32_heuristic_proc_desc(start_pc, limit_pc, next_frame, sp)
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PROC_REG_MASK(&temp_proc_desc) |= 1 << reg;
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set_reg_offset (reg, sp + low_word + 8 - MIPS_REGSIZE);
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}
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/* start-sanitize-r5900 */
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else if ((high_word & 0xFFE0) == 0x7fa0) /* sq reg,offset($sp) */
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{
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/* I don't think we have to worry about the Irix 6.2 N32 ABI
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issue noted int he sd reg, offset($sp) case above. */
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PROC_REG_MASK(&temp_proc_desc) |= 1 << reg;
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set_reg_offset (reg, sp + low_word);
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}
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/* end-sanitize-r5900 */
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else if (high_word == 0x27be) /* addiu $30,$sp,size */
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{
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/* Old gcc frame, r30 is virtual frame pointer. */
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@ -1708,6 +1732,20 @@ setup_arbitrary_frame (argc, argv)
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return create_new_frame (argv[0], argv[1]);
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}
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/*
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* STACK_ARGSIZE -- how many bytes does a pushed function arg take up on the stack?
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*
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* For n32 ABI, eight.
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* For all others, he same as the size of a general register.
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*/
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#if defined (_MIPS_SIM_NABI32) && _MIPS_SIM == _MIPS_SIM_NABI32
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#define MIPS_NABI32 1
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#define STACK_ARGSIZE 8
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#else
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#define MIPS_NABI32 0
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#define STACK_ARGSIZE MIPS_REGSIZE
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#endif
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CORE_ADDR
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mips_push_arguments(nargs, args, sp, struct_return, struct_addr)
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int nargs;
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@ -1775,7 +1813,7 @@ mips_push_arguments(nargs, args, sp, struct_return, struct_addr)
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/* 32-bit ABIs always start floating point arguments in an
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even-numbered floating point register. */
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if (!GDB_TARGET_IS_MIPS64 && typecode == TYPE_CODE_FLT
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if (!FP_REGISTER_DOUBLE && typecode == TYPE_CODE_FLT
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&& (float_argreg & 1))
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float_argreg++;
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@ -1792,7 +1830,7 @@ mips_push_arguments(nargs, args, sp, struct_return, struct_addr)
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&& float_argreg <= MIPS_LAST_FP_ARG_REGNUM
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&& mips_fpu != MIPS_FPU_NONE)
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{
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if (!GDB_TARGET_IS_MIPS64 && len == 8)
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if (!FP_REGISTER_DOUBLE && len == 8)
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{
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int low_offset = TARGET_BYTE_ORDER == BIG_ENDIAN ? 4 : 0;
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unsigned long regval;
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@ -1822,7 +1860,7 @@ mips_push_arguments(nargs, args, sp, struct_return, struct_addr)
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if (!MIPS_EABI)
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{
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write_register (argreg, regval);
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argreg += GDB_TARGET_IS_MIPS64 ? 1 : 2;
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argreg += FP_REGISTER_DOUBLE ? 1 : 2;
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}
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}
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}
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@ -1850,15 +1888,15 @@ mips_push_arguments(nargs, args, sp, struct_return, struct_addr)
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int longword_offset = 0;
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if (TARGET_BYTE_ORDER == BIG_ENDIAN)
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if (MIPS_REGSIZE == 8 &&
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if (STACK_ARGSIZE == 8 &&
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(typecode == TYPE_CODE_INT ||
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typecode == TYPE_CODE_PTR ||
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typecode == TYPE_CODE_FLT) && len <= 4)
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longword_offset = MIPS_REGSIZE - len;
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longword_offset = STACK_ARGSIZE - len;
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else if ((typecode == TYPE_CODE_STRUCT ||
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typecode == TYPE_CODE_UNION) &&
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TYPE_LENGTH (arg_type) < MIPS_REGSIZE)
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longword_offset = MIPS_REGSIZE - len;
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TYPE_LENGTH (arg_type) < STACK_ARGSIZE)
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longword_offset = STACK_ARGSIZE - len;
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write_memory (sp + stack_offset + longword_offset,
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val, partial_len);
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@ -1907,12 +1945,14 @@ mips_push_arguments(nargs, args, sp, struct_return, struct_addr)
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begins at (4 * MIPS_REGSIZE) in the old ABI. This
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leaves room for the "home" area for register parameters.
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In the new EABI, the 8 register parameters do not
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have "home" stack space reserved for them, so the
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In the new EABI (and the NABI32), the 8 register parameters
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do not have "home" stack space reserved for them, so the
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stack offset does not get incremented until after
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we have used up the 8 parameter registers. */
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if (!(MIPS_EABI && argnum < 8))
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stack_offset += ROUND_UP (partial_len, MIPS_REGSIZE);
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if (!(MIPS_EABI || MIPS_NABI32) ||
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argnum >= 8)
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stack_offset += ROUND_UP (partial_len, STACK_ARGSIZE);
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}
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}
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}
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@ -1990,7 +2030,8 @@ mips_push_dummy_frame()
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/* Save general CPU registers */
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PROC_REG_MASK(proc_desc) = GEN_REG_SAVE_MASK;
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PROC_REG_OFFSET(proc_desc) = sp - old_sp; /* offset of (Saved R31) from FP */
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/* PROC_REG_OFFSET is the offset of the first saved register from FP. */
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PROC_REG_OFFSET(proc_desc) = sp - old_sp - MIPS_REGSIZE;
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for (ireg = 32; --ireg >= 0; )
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if (PROC_REG_MASK(proc_desc) & (1 << ireg))
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mips_push_register (&sp, ireg);
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@ -1999,7 +2040,9 @@ mips_push_dummy_frame()
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PROC_FREG_MASK(proc_desc) =
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mips_fpu == MIPS_FPU_DOUBLE ? FLOAT_REG_SAVE_MASK
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: mips_fpu == MIPS_FPU_SINGLE ? FLOAT_SINGLE_REG_SAVE_MASK : 0;
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PROC_FREG_OFFSET(proc_desc) = sp - old_sp; /* offset of (Saved D18) from FP */
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/* PROC_FREG_OFFSET is the offset of the first saved *double* register
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from FP. */
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PROC_FREG_OFFSET(proc_desc) = sp - old_sp - 8;
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for (ireg = 32; --ireg >= 0; )
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if (PROC_FREG_MASK(proc_desc) & (1 << ireg))
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mips_push_register (&sp, ireg + FP0_REGNUM);
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@ -2086,7 +2129,7 @@ mips_print_register (regnum, all)
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/* If an even floating point register, also print as double. */
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if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT
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&& !((regnum-FP0_REGNUM) & 1))
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if (REGISTER_RAW_SIZE(regnum) == 4) /* this would be silly on MIPS64 */
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if (REGISTER_RAW_SIZE(regnum) == 4) /* this would be silly on MIPS64 or N32 (Irix 6) */
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{
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char dbuffer[2 * MAX_REGISTER_RAW_SIZE];
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@ -2112,7 +2155,7 @@ mips_print_register (regnum, all)
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/* If virtual format is floating, print it that way. */
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if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
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if (REGISTER_RAW_SIZE(regnum) == 8)
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if (FP_REGISTER_DOUBLE)
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{ /* show 8-byte floats as float AND double: */
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int offset = 4 * (TARGET_BYTE_ORDER == BIG_ENDIAN);
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@ -2387,6 +2430,9 @@ mips32_skip_prologue (pc, lenient)
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inst == 0x03a8e823) /* subu $sp,$sp,$t0 */
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seen_sp_adjust = 1;
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else if (((inst & 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
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/* start-sanitize-r5900 */
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|| (inst & 0xFFE00000) == 0x7FA00000 /* sq reg,n($sp) */
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/* end-sanitize-r5900 */
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|| (inst & 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
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&& (inst & 0x001F0000)) /* reg != $zero */
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continue;
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