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gas: blackfin: add missing register move insns

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The Blackfin ISA supports moving just about anything to/from EMUDAT, so
make sure the assembler accepts these insns too.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger 2010-09-22 21:30:35 +00:00
parent a2c28b80f1
commit 9d2eed0673
3 changed files with 10 additions and 2 deletions
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5
gas/ChangeLog
View File

@ -1,3 +1,8 @@
2010-09-22 Robin Getz <robin.getz@analog.com>
* config/bfin-defs.h (IS_EMUDAT): New define.
* config/bfin-parse.y: Accept EMUDAT for any register move.
2010-09-22 Robin Getz <robin.getz@analog.com>
* config/bfin-parse.y: Improve error messages.

1
gas/config/bfin-defs.h
View File

@ -203,6 +203,7 @@ enum reg_class
#define IS_BREG(r) (((r).regno & 0xf4) == T_REG_B)
#define IS_LREG(r) (((r).regno & 0xf4) == T_REG_L)
#define IS_CREG(r) ((r).regno == REG_LC0 || (r).regno == REG_LC1)
#define IS_EMUDAT(r) ((r).regno == REG_EMUDAT)
#define IS_ALLREG(r) ((r).regno < T_NOGROUP)
#define IS_GENREG(r) \

6
gas/config/bfin-parse.y
View File

@ -1728,10 +1728,12 @@ asm_1:
|| (IS_DAGREG ($1) && IS_DAGREG ($3))
|| (IS_GENREG ($1) && $3.regno == REG_USP)
|| ($1.regno == REG_USP && IS_GENREG ($3))
|| ($1.regno == REG_USP && $3.regno == REG_USP)
|| (IS_DREG ($1) && IS_SYSREG ($3))
|| (IS_PREG ($1) && IS_SYSREG ($3))
|| (IS_SYSREG ($1) && IS_DREG ($3))
|| (IS_SYSREG ($1) && IS_PREG ($3))
|| (IS_SYSREG ($1) && IS_GENREG ($3))
|| (IS_ALLREG ($1) && IS_EMUDAT ($3))
|| (IS_EMUDAT ($1) && IS_ALLREG ($3))
|| (IS_SYSREG ($1) && $3.regno == REG_USP))
{
$$ = bfin_gen_regmv (&$3, &$1);