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Add ``set debug mips'' command. Add much debugging.
This commit is contained in:
Andrew Cagney
parent
9a0149c65a
commit
9ace04976e
@ -1,3 +1,10 @@
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Sun Jun 18 01:01:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
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* mips-tdep.c (mips_debug): New variable.
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(_initialize_mips_tdep): Add command "set debug mips".
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(mips_push_arguments): Add code to dump the argument list as it is
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created.
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Sun Jun 18 00:27:15 2000 Andrew Cagney <cagney@b1.cygnus.com>
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* mips-tdep.c (mips_push_arguments): For MIPS_EABI, squeeze a
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112
gdb/mips-tdep.c
112
gdb/mips-tdep.c
@ -107,6 +107,7 @@ static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE;
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#define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8)
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#endif
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static int mips_debug = 0;
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/* MIPS specific per-architecture information */
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struct gdbarch_tdep
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@ -2095,13 +2096,23 @@ mips_push_arguments (nargs, args, sp, struct_return, struct_addr)
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len += ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args[argnum])), MIPS_SAVED_REGSIZE);
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sp -= ROUND_UP (len, 16);
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if (mips_debug)
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fprintf_unfiltered (gdb_stdlog, "mips_push_arguments: sp=0x%lx allocated %d\n",
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(long) sp, ROUND_UP (len, 16));
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/* Initialize the integer and float register pointers. */
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argreg = A0_REGNUM;
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float_argreg = FPA0_REGNUM;
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/* the struct_return pointer occupies the first parameter-passing reg */
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if (struct_return)
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write_register (argreg++, struct_addr);
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{
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if (mips_debug)
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fprintf_unfiltered (gdb_stdlog,
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"mips_push_arguments: struct_return at r%d 0x%lx\n",
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argreg, (long) struct_addr);
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write_register (argreg++, struct_addr);
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}
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/* Now load as many as possible of the first arguments into
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registers, and push the rest onto the stack. Loop thru args
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@ -2115,15 +2126,23 @@ mips_push_arguments (nargs, args, sp, struct_return, struct_addr)
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int len = TYPE_LENGTH (arg_type);
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enum type_code typecode = TYPE_CODE (arg_type);
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if (mips_debug)
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fprintf_unfiltered (gdb_stdlog,
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"mips_push_arguments: %d len=%d type=%d",
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argnum, len, (int) typecode);
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/* The EABI passes structures that do not fit in a register by
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reference. In all other cases, pass the structure by value. */
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if (MIPS_EABI && len > MIPS_SAVED_REGSIZE &&
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(typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
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if (MIPS_EABI
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&& len > MIPS_SAVED_REGSIZE
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&& (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
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{
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store_address (valbuf, MIPS_SAVED_REGSIZE, VALUE_ADDRESS (arg));
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typecode = TYPE_CODE_PTR;
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len = MIPS_SAVED_REGSIZE;
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val = valbuf;
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if (mips_debug)
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fprintf_unfiltered (gdb_stdlog, " push");
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}
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else
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val = (char *) VALUE_CONTENTS (arg);
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@ -2161,17 +2180,30 @@ mips_push_arguments (nargs, args, sp, struct_return, struct_addr)
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/* Write the low word of the double to the even register(s). */
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regval = extract_unsigned_integer (val + low_offset, 4);
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write_register (float_argreg++, regval);
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if (!MIPS_EABI)
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write_register (argreg + 1, regval);
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/* Write the high word of the double to the odd register(s). */
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regval = extract_unsigned_integer (val + 4 - low_offset, 4);
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if (mips_debug)
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fprintf_unfiltered (gdb_stdlog, " fpreg=%d val=%s",
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float_argreg, phex (regval, 4));
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write_register (float_argreg++, regval);
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if (!MIPS_EABI)
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{
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write_register (argreg, regval);
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argreg += 2;
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if (mips_debug)
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fprintf_unfiltered (gdb_stdlog, " reg=%d val=%s",
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argreg, phex (regval, 4));
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write_register (argreg++, regval);
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}
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/* Write the high word of the double to the odd register(s). */
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regval = extract_unsigned_integer (val + 4 - low_offset, 4);
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if (mips_debug)
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fprintf_unfiltered (gdb_stdlog, " fpreg=%d val=%s",
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float_argreg, phex (regval, 4));
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write_register (float_argreg++, regval);
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if (!MIPS_EABI)
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{
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if (mips_debug)
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fprintf_unfiltered (gdb_stdlog, " reg=%d val=%s",
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argreg, phex (regval, 4));
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write_register (argreg++, regval);
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}
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}
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@ -2181,7 +2213,10 @@ mips_push_arguments (nargs, args, sp, struct_return, struct_addr)
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in a single register. */
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/* On 32 bit ABI's the float_argreg is further adjusted
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above to ensure that it is even register aligned. */
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CORE_ADDR regval = extract_address (val, len);
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LONGEST regval = extract_unsigned_integer (val, len);
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if (mips_debug)
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fprintf_unfiltered (gdb_stdlog, " fpreg=%d val=%s",
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float_argreg, phex (regval, len));
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write_register (float_argreg++, regval);
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if (!MIPS_EABI)
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{
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@ -2189,6 +2224,9 @@ mips_push_arguments (nargs, args, sp, struct_return, struct_addr)
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registers for each argument. The below is (my
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guess) to ensure that the corresponding integer
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register has reserved the same space. */
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if (mips_debug)
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fprintf_unfiltered (gdb_stdlog, " reg=%d val=%s",
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argreg, phex (regval, len));
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write_register (argreg, regval);
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argreg += FP_REGISTER_DOUBLE ? 1 : 2;
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}
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@ -2217,6 +2255,7 @@ mips_push_arguments (nargs, args, sp, struct_return, struct_addr)
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promoted to int before being stored? */
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int longword_offset = 0;
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CORE_ADDR addr;
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if (TARGET_BYTE_ORDER == BIG_ENDIAN)
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{
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if (MIPS_STACK_ARGSIZE == 8 &&
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@ -2230,15 +2269,33 @@ mips_push_arguments (nargs, args, sp, struct_return, struct_addr)
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longword_offset = MIPS_STACK_ARGSIZE - len;
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}
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write_memory (sp + stack_offset + longword_offset,
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val, partial_len);
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if (mips_debug)
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{
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fprintf_unfiltered (gdb_stdlog, " stack_offset=0x%lx",
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(long) stack_offset);
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fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%lx",
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(long) longword_offset);
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}
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addr = sp + stack_offset + longword_offset;
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if (mips_debug)
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{
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int i;
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fprintf_unfiltered (gdb_stdlog, " @0x%lx ", (long) addr);
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for (i = 0; i < partial_len; i++)
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{
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fprintf_unfiltered (gdb_stdlog, "%02x", val[i] & 0xff);
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}
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}
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write_memory (addr, val, partial_len);
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}
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/* Note!!! This is NOT an else clause.
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Odd sized structs may go thru BOTH paths. */
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if (argreg <= MIPS_LAST_ARG_REGNUM)
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{
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CORE_ADDR regval = extract_address (val, partial_len);
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LONGEST regval = extract_unsigned_integer (val, partial_len);
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/* A non-floating-point argument being passed in a
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general register. If a struct or union, and if
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@ -2261,6 +2318,10 @@ mips_push_arguments (nargs, args, sp, struct_return, struct_addr)
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regval <<= ((MIPS_SAVED_REGSIZE - partial_len) *
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TARGET_CHAR_BIT);
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if (mips_debug)
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fprintf_filtered (gdb_stdlog, " reg=%d val=%s",
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argreg,
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phex (regval, MIPS_SAVED_REGSIZE));
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write_register (argreg, regval);
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argreg++;
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@ -2288,6 +2349,8 @@ mips_push_arguments (nargs, args, sp, struct_return, struct_addr)
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stack_offset += ROUND_UP (partial_len, MIPS_STACK_ARGSIZE);
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}
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}
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if (mips_debug)
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fprintf_unfiltered (gdb_stdlog, "\n");
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}
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/* Return adjusted stack pointer. */
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@ -3854,8 +3917,12 @@ mips_gdbarch_init (info, arches)
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struct gdbarch *gdbarch;
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struct gdbarch_tdep *tdep;
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int elf_flags;
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#if 0
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int ef_mips_bitptrs;
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#endif
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#if 0
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int ef_mips_arch;
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#endif
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enum mips_abi mips_abi;
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/* Extract the elf_flags if available */
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@ -3908,14 +3975,18 @@ mips_gdbarch_init (info, arches)
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if (gdbarch_debug)
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{
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fprintf_unfiltered (gdb_stdlog,
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"mips_gdbarch_init: elf_flags = %08x\n",
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"mips_gdbarch_init: elf_flags = 0x%08x\n",
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elf_flags);
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#if 0
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fprintf_unfiltered (gdb_stdlog,
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"mips_gdbarch_init: ef_mips_arch = %d\n",
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ef_mips_arch);
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#endif
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#if 0
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fprintf_unfiltered (gdb_stdlog,
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"mips_gdbarch_init: ef_mips_bitptrs = %d\n",
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ef_mips_bitptrs);
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#endif
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fprintf_unfiltered (gdb_stdlog,
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"mips_gdbarch_init: mips_abi = %d\n",
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mips_abi);
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@ -4044,6 +4115,7 @@ mips_gdbarch_init (info, arches)
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the current gcc - it would make GDB treat these 64-bit programs
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as 32-bit programs by default. */
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#if 0
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/* determine the ISA */
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switch (elf_flags & EF_MIPS_ARCH)
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{
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@ -4062,6 +4134,7 @@ mips_gdbarch_init (info, arches)
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default:
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break;
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}
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#endif
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#if 0
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/* determine the size of a pointer */
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@ -4652,4 +4725,11 @@ that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
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64 bits for others. Use \"off\" to disable compatibility mode",
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&setlist),
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&showlist);
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/* Debug this files internals. */
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add_show_from_set (add_set_cmd ("mips", class_maintenance, var_zinteger,
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&mips_debug, "Set mips debugging.\n\
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When non-zero, mips specific debugging is enabled.", &setdebuglist),
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&showdebuglist);
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}
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