* config/tc-arm.c (neon_check_type): Handle a neon_shape value of
        NS_NULL.
        * gas/arm/neon-omit.s: Add instruction that causes crash.
        * gas/arm/neon-omit.d: Add expected disassembly.
This commit is contained in:
Nick Clifton 2010-01-29 16:02:41 +00:00
parent 02961d7edf
commit 99b253c514
5 changed files with 29 additions and 5 deletions

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@ -1,3 +1,9 @@
2010-01-29 Nick Clifton <nickc@redhat.com>
PR 11136
* config/tc-arm.c (neon_check_type): Handle a neon_shape value of
NS_NULL.
2010-01-27 Dave Korn <dave.korn.cygwin@gmail.com>
* NEWS: Mention new feature.
@ -42,7 +48,7 @@
Include obj-format.h earlier.
2010-01-21 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* config/tc-s390.c (s390_elf_final_processing): New function.
* config/tc-s390.h (elf_tc_final_processing): New macro definition.
(s390_elf_final_processing): Added prototype.

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@ -12043,8 +12043,17 @@ neon_check_type (unsigned els, enum neon_shape ns, ...)
{
if ((thisarg & N_VFP) != 0)
{
enum neon_shape_el regshape = neon_shape_tab[ns].el[i];
unsigned regwidth = neon_shape_el_size[regshape], match;
enum neon_shape_el regshape;
unsigned regwidth, match;
/* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
if (ns == NS_NULL)
{
first_error (_("invalid instruction shape"));
return badtype;
}
regshape = neon_shape_tab[ns].el[i];
regwidth = neon_shape_el_size[regshape];
/* In VFP mode, operands must match register widths. If we
have a key operand, use its width, else use the width of
@ -12193,9 +12202,8 @@ try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
pfn (rs);
return SUCCESS;
}
else
inst.error = NULL;
inst.error = NULL;
return FAIL;
}

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@ -1,3 +1,9 @@
2010-01-29 Nick Clifton <nickc@redhat.com>
PR 11136
* gas/arm/neon-omit.s: Add instruction that causes crash.
* gas/arm/neon-omit.d: Add expected disassembly.
2010-01-28 Dave Korn <dave.korn.cygwin@gmail.com>
* gas/pe/section-align-1.d: Don't test section flags.

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@ -93,3 +93,4 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> f3954556 vsli\.16 q2, q3, #5
0[0-9a-f]+ <[^>]+> f3bff6b7 vqshlu\.s64 d15, d23, #63.*
0[0-9a-f]+ <[^>]+> f2b25386 vext\.8 d5, d18, d6, #3
0[0-9a-f]+ <[^>]+> f3020d54 vmul\.f32 q0, q1, q2

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@ -95,3 +95,6 @@
vsli.16 q2,q3,#5
vqshlu.s64 d15,d23,#63
vext.8 d5,d18,d6,#3
@ PR 11136 - this used to crash the assembler.
vmul.f32 q0,q1,q2