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Add clflushopt, xsaves, xsavec, xrstors
gas/ 2014-02-12 Ilya Tocar <ilya.tocar@intel.com> * config/tc-i386.c (cpu_arch): Add .clflushopt, .xsavec, .xsaves. * doc/c-i386.texi: Document .xsavec/xsavec/.xsaves/xsaves/ clflushopt/.clfushopt. gas/testsuite/ 2014-02-12 Ilya Tocar <ilya.tocar@intel.com> * gas/i386/clflushopt-intel.d: New. * gas/i386/clflushopt.d: Ditto. * gas/i386/clflushopt.s: Ditto. * gas/i386/i386.exp: Run new tests. * gas/i386/x86-64-clflushopt-intel.d: New. * gas/i386/x86-64-clflushopt.d: Ditto. * gas/i386/x86-64-clflushopt.s: Ditto. * gas/i386/x86-64-xsavec-intel.d: Ditto. * gas/i386/x86-64-xsavec.d: Ditto. * gas/i386/x86-64-xsavec.s: Ditto. * gas/i386/x86-64-xsaves-intel.d: Ditto. * gas/i386/x86-64-xsaves.d: Ditto. * gas/i386/x86-64-xsaves.s: Ditto. * gas/i386/xsavec-intel.d: Ditto. * gas/i386/xsavec.d: Ditto. * gas/i386/xsavec.s: Ditto. * gas/i386/xsaves-intel.d: Ditto. * gas/i386/xsaves.d: Ditto. * gas/i386/xsaves.s: Ditto. opcodes/ 2014-02-12 Ilya Tocar <ilya.tocar@intel.com> * i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4, MOD_0FC7_REG_5. (PREFIX enum): Add PREFIX_0FAE_REG_7. (reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5. (prefix_table): Add clflusopt. (mod_table): Add xrstors, xsavec, xsaves. * i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS, CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS. (cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC. * i386-init.h: Regenerate. * i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves, xsaves64, xsavec, xsavec64. * i386-tbl.h: Regenerate.
This commit is contained in:
Ilya Tocar
H.J. Lu
parent
0548b5db30
commit
963f35869d
@ -1,3 +1,9 @@
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2014-02-12 Ilya Tocar <ilya.tocar@intel.com>
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* config/tc-i386.c (cpu_arch): Add .clflushopt, .xsavec, .xsaves.
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* doc/c-i386.texi: Document .xsavec/xsavec/.xsaves/xsaves/
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clflushopt/.clfushopt.
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2014-02-10 Alan Modra <amodra@gmail.com>
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* po/POTFILES.in: Regenerate.
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@ -904,6 +904,12 @@ static const arch_entry cpu_arch[] =
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CPU_MPX_FLAGS, 0, 0 },
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{ STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
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CPU_SHA_FLAGS, 0, 0 },
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{ STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
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CPU_CLFLUSHOPT_FLAGS, 0, 0 },
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{ STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
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CPU_XSAVEC_FLAGS, 0, 0 },
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{ STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
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CPU_XSAVES_FLAGS, 0, 0 },
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};
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#ifdef I386COFF
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@ -1063,6 +1063,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
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@item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
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@item @samp{.smap} @tab @samp{.mpx}
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@item @samp{.smap} @tab @samp{.sha}
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@item @samp{.smap} @tab @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves}
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@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
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@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
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@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
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@ -1,3 +1,25 @@
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2014-02-12 Ilya Tocar <ilya.tocar@intel.com>
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* gas/i386/clflushopt-intel.d: New.
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* gas/i386/clflushopt.d: Ditto.
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* gas/i386/clflushopt.s: Ditto.
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* gas/i386/i386.exp: Run new tests.
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* gas/i386/x86-64-clflushopt-intel.d: New.
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* gas/i386/x86-64-clflushopt.d: Ditto.
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* gas/i386/x86-64-clflushopt.s: Ditto.
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* gas/i386/x86-64-xsavec-intel.d: Ditto.
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* gas/i386/x86-64-xsavec.d: Ditto.
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* gas/i386/x86-64-xsavec.s: Ditto.
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* gas/i386/x86-64-xsaves-intel.d: Ditto.
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* gas/i386/x86-64-xsaves.d: Ditto.
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* gas/i386/x86-64-xsaves.s: Ditto.
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* gas/i386/xsavec-intel.d: Ditto.
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* gas/i386/xsavec.d: Ditto.
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* gas/i386/xsavec.s: Ditto.
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* gas/i386/xsaves-intel.d: Ditto.
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* gas/i386/xsaves.d: Ditto.
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* gas/i386/xsaves.s: Ditto.
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2014-01-31 Michael Zolotukhin <michael.v.zolotukhin@gmail.com>
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PR gas/16488
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16
gas/testsuite/gas/i386/clflushopt-intel.d
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16
gas/testsuite/gas/i386/clflushopt-intel.d
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@ -0,0 +1,16 @@
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#as:
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#objdump: -dw -Mintel
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#name: i386 CLFLUSHOPT insns (Intel disassembly)
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#source: clflushopt.s
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.*: +file format .*
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Disassembly of section \.text:
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00000000 <_start>:
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[ ]*[a-f0-9]+:[ ]*66 0f ae 39[ ]*clflushopt BYTE PTR \[ecx\]
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[ ]*[a-f0-9]+:[ ]*66 0f ae bc f4 c0 1d fe ff[ ]*clflushopt BYTE PTR \[esp\+esi\*8-0x1e240\]
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[ ]*[a-f0-9]+:[ ]*66 0f ae 39[ ]*clflushopt BYTE PTR \[ecx\]
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[ ]*[a-f0-9]+:[ ]*66 0f ae bc f4 c0 1d fe ff[ ]*clflushopt BYTE PTR \[esp\+esi\*8-0x1e240\]
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#pass
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16
gas/testsuite/gas/i386/clflushopt.d
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16
gas/testsuite/gas/i386/clflushopt.d
Normal file
@ -0,0 +1,16 @@
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#as:
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#objdump: -dw
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#name: i386 CLFLUSHOPT insns
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#source: clflushopt.s
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.*: +file format .*
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Disassembly of section \.text:
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00000000 <_start>:
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[ ]*[a-f0-9]+:[ ]*66 0f ae 39[ ]*clflushopt \(%ecx\)
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[ ]*[a-f0-9]+:[ ]*66 0f ae bc f4 c0 1d fe ff[ ]*clflushopt -0x1e240\(%esp,%esi,8\)
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[ ]*[a-f0-9]+:[ ]*66 0f ae 39[ ]*clflushopt \(%ecx\)
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[ ]*[a-f0-9]+:[ ]*66 0f ae bc f4 c0 1d fe ff[ ]*clflushopt -0x1e240\(%esp,%esi,8\)
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#pass
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12
gas/testsuite/gas/i386/clflushopt.s
Normal file
12
gas/testsuite/gas/i386/clflushopt.s
Normal file
@ -0,0 +1,12 @@
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# Check 32bit CLFLUSHOPT instructions
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.allow_index_reg
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.text
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_start:
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clflushopt (%ecx) # CLFLUSHOPT
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clflushopt -123456(%esp,%esi,8) # CLFLUSHOPT
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.intel_syntax noprefix
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clflushopt BYTE PTR [ecx] # CLFLUSHOPT
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clflushopt BYTE PTR [esp+esi*8-123456] # CLFLUSHOPT
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@ -269,6 +269,12 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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run_list_test "mpx-inval-1" "-al"
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run_dump_test "mpx-add-bnd-prefix"
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run_dump_test "sha"
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run_dump_test "clflushopt"
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run_dump_test "clflushopt-intel"
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run_dump_test "xsavec"
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run_dump_test "xsavec-intel"
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run_dump_test "xsaves"
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run_dump_test "xsaves-intel"
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run_dump_test "disassem"
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# These tests require support for 8 and 16 bit relocs,
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@ -559,6 +565,12 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
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run_dump_test "x86-64-mpx-addr32"
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run_dump_test "x86-64-mpx-add-bnd-prefix"
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run_dump_test "x86-64-sha"
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run_dump_test "x86-64-clflushopt"
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run_dump_test "x86-64-clflushopt-intel"
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run_dump_test "x86-64-xsavec"
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run_dump_test "x86-64-xsavec-intel"
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run_dump_test "x86-64-xsaves"
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run_dump_test "x86-64-xsaves-intel"
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if { ![istarget "*-*-aix*"]
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&& ![istarget "*-*-beos*"]
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16
gas/testsuite/gas/i386/x86-64-clflushopt-intel.d
Normal file
16
gas/testsuite/gas/i386/x86-64-clflushopt-intel.d
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@ -0,0 +1,16 @@
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#as:
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#objdump: -dw -Mintel
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#name: x86_64 CLFLUSHOPT insns (Intel disassembly)
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#source: x86-64-clflushopt.s
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.*: +file format .*
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Disassembly of section \.text:
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0+ <_start>:
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[ ]*[a-f0-9]+:[ ]*66 0f ae 39[ ]*clflushopt BYTE PTR \[rcx\]
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[ ]*[a-f0-9]+:[ ]*66 42 0f ae bc f0 23 01 00 00[ ]*clflushopt BYTE PTR \[rax\+r14\*8\+0x123\]
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[ ]*[a-f0-9]+:[ ]*66 0f ae 39[ ]*clflushopt BYTE PTR \[rcx\]
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[ ]*[a-f0-9]+:[ ]*66 42 0f ae bc f0 34 12 00 00[ ]*clflushopt BYTE PTR \[rax\+r14\*8\+0x1234\]
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#pass
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16
gas/testsuite/gas/i386/x86-64-clflushopt.d
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16
gas/testsuite/gas/i386/x86-64-clflushopt.d
Normal file
@ -0,0 +1,16 @@
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#as:
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#objdump: -dw
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#name: x86_64 CLFLUSHOPT insns
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#source: x86-64-clflushopt.s
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.*: +file format .*
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Disassembly of section \.text:
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0+ <_start>:
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[ ]*[a-f0-9]+:[ ]*66 0f ae 39[ ]*clflushopt \(%rcx\)
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[ ]*[a-f0-9]+:[ ]*66 42 0f ae bc f0 23 01 00 00[ ]*clflushopt 0x123\(%rax,%r14,8\)
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[ ]*[a-f0-9]+:[ ]*66 0f ae 39[ ]*clflushopt \(%rcx\)
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[ ]*[a-f0-9]+:[ ]*66 42 0f ae bc f0 34 12 00 00[ ]*clflushopt 0x1234\(%rax,%r14,8\)
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#pass
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12
gas/testsuite/gas/i386/x86-64-clflushopt.s
Normal file
12
gas/testsuite/gas/i386/x86-64-clflushopt.s
Normal file
@ -0,0 +1,12 @@
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# Check 64bit CLFLUSHOPT instructions
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.allow_index_reg
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.text
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_start:
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clflushopt (%rcx) # CLFLUSHOPT
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clflushopt 0x123(%rax,%r14,8) # CLFLUSHOPT
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.intel_syntax noprefix
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clflushopt BYTE PTR [rcx] # CLFLUSHOPT
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clflushopt BYTE PTR [rax+r14*8+0x1234] # CLFLUSHOPT
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16
gas/testsuite/gas/i386/x86-64-xsavec-intel.d
Normal file
16
gas/testsuite/gas/i386/x86-64-xsavec-intel.d
Normal file
@ -0,0 +1,16 @@
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#as:
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#objdump: -dw -Mintel
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#name: x86_64 XSAVEC insns (Intel disassembly)
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#source: x86-64-xsavec.s
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.*: +file format .*
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Disassembly of section \.text:
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0+ <_start>:
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[ ]*[a-f0-9]+:[ ]*48 0f c7 21[ ]*xsavec64 \[rcx\]
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[ ]*[a-f0-9]+:[ ]*4a 0f c7 a4 f0 23 01 00 00[ ]*xsavec64 \[rax\+r14\*8\+0x123\]
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[ ]*[a-f0-9]+:[ ]*48 0f c7 21[ ]*xsavec64 \[rcx\]
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[ ]*[a-f0-9]+:[ ]*4a 0f c7 a4 f0 34 12 00 00[ ]*xsavec64 \[rax\+r14\*8\+0x1234\]
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#pass
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16
gas/testsuite/gas/i386/x86-64-xsavec.d
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16
gas/testsuite/gas/i386/x86-64-xsavec.d
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@ -0,0 +1,16 @@
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#as:
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#objdump: -dw
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#name: x86_64 XSAVEC insns
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#source: x86-64-xsavec.s
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.*: +file format .*
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Disassembly of section \.text:
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0+ <_start>:
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[ ]*[a-f0-9]+:[ ]*48 0f c7 21[ ]*xsavec64 \(%rcx\)
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[ ]*[a-f0-9]+:[ ]*4a 0f c7 a4 f0 23 01 00 00[ ]*xsavec64 0x123\(%rax,%r14,8\)
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[ ]*[a-f0-9]+:[ ]*48 0f c7 21[ ]*xsavec64 \(%rcx\)
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[ ]*[a-f0-9]+:[ ]*4a 0f c7 a4 f0 34 12 00 00[ ]*xsavec64 0x1234\(%rax,%r14,8\)
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#pass
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12
gas/testsuite/gas/i386/x86-64-xsavec.s
Normal file
12
gas/testsuite/gas/i386/x86-64-xsavec.s
Normal file
@ -0,0 +1,12 @@
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# Check 64bit XSAVEC instructions
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.allow_index_reg
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.text
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_start:
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xsavec64 (%rcx) # XSAVEC
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xsavec64 0x123(%rax,%r14,8) # XSAVEC
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.intel_syntax noprefix
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xsavec64 [rcx] # XSAVEC
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xsavec64 [rax+r14*8+0x1234] # XSAVEC
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20
gas/testsuite/gas/i386/x86-64-xsaves-intel.d
Normal file
20
gas/testsuite/gas/i386/x86-64-xsaves-intel.d
Normal file
@ -0,0 +1,20 @@
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#as:
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#objdump: -dw -Mintel
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#name: x86_64 XSAVES insns (Intel disassembly)
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#source: x86-64-xsaves.s
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.*: +file format .*
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Disassembly of section \.text:
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0+ <_start>:
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[ ]*[a-f0-9]+:[ ]*48 0f c7 29[ ]*xsaves64 \[rcx\]
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[ ]*[a-f0-9]+:[ ]*4a 0f c7 ac f0 23 01 00 00[ ]*xsaves64 \[rax\+r14\*8\+0x123\]
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[ ]*[a-f0-9]+:[ ]*48 0f c7 19[ ]*xrstors64 \[rcx\]
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[ ]*[a-f0-9]+:[ ]*4a 0f c7 9c f0 23 01 00 00[ ]*xrstors64 \[rax\+r14\*8\+0x123\]
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[ ]*[a-f0-9]+:[ ]*48 0f c7 29[ ]*xsaves64 \[rcx\]
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[ ]*[a-f0-9]+:[ ]*4a 0f c7 ac f0 34 12 00 00[ ]*xsaves64 \[rax\+r14\*8\+0x1234\]
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[ ]*[a-f0-9]+:[ ]*48 0f c7 19[ ]*xrstors64 \[rcx\]
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[ ]*[a-f0-9]+:[ ]*4a 0f c7 9c f0 34 12 00 00[ ]*xrstors64 \[rax\+r14\*8\+0x1234\]
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#pass
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20
gas/testsuite/gas/i386/x86-64-xsaves.d
Normal file
20
gas/testsuite/gas/i386/x86-64-xsaves.d
Normal file
@ -0,0 +1,20 @@
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#as:
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#objdump: -dw
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#name: x86_64 XSAVES insns
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#source: x86-64-xsaves.s
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.*: +file format .*
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Disassembly of section \.text:
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0+ <_start>:
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[ ]*[a-f0-9]+:[ ]*48 0f c7 29[ ]*xsaves64 \(%rcx\)
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[ ]*[a-f0-9]+:[ ]*4a 0f c7 ac f0 23 01 00 00[ ]*xsaves64 0x123\(%rax,%r14,8\)
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[ ]*[a-f0-9]+:[ ]*48 0f c7 19[ ]*xrstors64 \(%rcx\)
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[ ]*[a-f0-9]+:[ ]*4a 0f c7 9c f0 23 01 00 00[ ]*xrstors64 0x123\(%rax,%r14,8\)
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[ ]*[a-f0-9]+:[ ]*48 0f c7 29[ ]*xsaves64 \(%rcx\)
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[ ]*[a-f0-9]+:[ ]*4a 0f c7 ac f0 34 12 00 00[ ]*xsaves64 0x1234\(%rax,%r14,8\)
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[ ]*[a-f0-9]+:[ ]*48 0f c7 19[ ]*xrstors64 \(%rcx\)
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[ ]*[a-f0-9]+:[ ]*4a 0f c7 9c f0 34 12 00 00[ ]*xrstors64 0x1234\(%rax,%r14,8\)
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#pass
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16
gas/testsuite/gas/i386/x86-64-xsaves.s
Normal file
16
gas/testsuite/gas/i386/x86-64-xsaves.s
Normal file
@ -0,0 +1,16 @@
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# Check 64bit XSAVES instructions
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.allow_index_reg
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.text
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_start:
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xsaves64 (%rcx) # XSAVES
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xsaves64 0x123(%rax,%r14,8) # XSAVES
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xrstors64 (%rcx) # XSAVES
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xrstors64 0x123(%rax,%r14,8) # XSAVES
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.intel_syntax noprefix
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xsaves64 [rcx] # XSAVES
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xsaves64 [rax+r14*8+0x1234] # XSAVES
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xrstors64 [rcx] # XSAVES
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xrstors64 [rax+r14*8+0x1234] # XSAVES
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16
gas/testsuite/gas/i386/xsavec-intel.d
Normal file
16
gas/testsuite/gas/i386/xsavec-intel.d
Normal file
@ -0,0 +1,16 @@
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#as:
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#objdump: -dw -Mintel
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#name: i386 XSAVEC insns (Intel disassembly)
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#source: xsavec.s
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.*: +file format .*
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Disassembly of section \.text:
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00000000 <_start>:
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||||
[ ]*[a-f0-9]+:[ ]*0f c7 21[ ]*xsavec \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*0f c7 a4 f4 c0 1d fe ff[ ]*xsavec \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*0f c7 21[ ]*xsavec \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*0f c7 a4 f4 c0 1d fe ff[ ]*xsavec \[esp\+esi\*8-0x1e240\]
|
||||
#pass
|
||||
16
gas/testsuite/gas/i386/xsavec.d
Normal file
16
gas/testsuite/gas/i386/xsavec.d
Normal file
@ -0,0 +1,16 @@
|
||||
#as:
|
||||
#objdump: -dw
|
||||
#name: i386 XSAVEC insns
|
||||
#source: xsavec.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*0f c7 21[ ]*xsavec \(%ecx\)
|
||||
[ ]*[a-f0-9]+:[ ]*0f c7 a4 f4 c0 1d fe ff[ ]*xsavec -0x1e240\(%esp,%esi,8\)
|
||||
[ ]*[a-f0-9]+:[ ]*0f c7 21[ ]*xsavec \(%ecx\)
|
||||
[ ]*[a-f0-9]+:[ ]*0f c7 a4 f4 c0 1d fe ff[ ]*xsavec -0x1e240\(%esp,%esi,8\)
|
||||
#pass
|
||||
12
gas/testsuite/gas/i386/xsavec.s
Normal file
12
gas/testsuite/gas/i386/xsavec.s
Normal file
@ -0,0 +1,12 @@
|
||||
# Check 32bit XSAVEC instructions
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
|
||||
xsavec (%ecx) # XSAVEC
|
||||
xsavec -123456(%esp,%esi,8) # XSAVEC
|
||||
|
||||
.intel_syntax noprefix
|
||||
xsavec [ecx] # XSAVEC
|
||||
xsavec [esp+esi*8-123456] # XSAVEC
|
||||
20
gas/testsuite/gas/i386/xsaves-intel.d
Normal file
20
gas/testsuite/gas/i386/xsaves-intel.d
Normal file
@ -0,0 +1,20 @@
|
||||
#as:
|
||||
#objdump: -dw -Mintel
|
||||
#name: i386 XSAVES insns (Intel disassembly)
|
||||
#source: xsaves.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*0f c7 29[ ]*xsaves \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*0f c7 ac f4 c0 1d fe ff[ ]*xsaves \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*0f c7 19[ ]*xrstors \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*0f c7 9c f4 c0 1d fe ff[ ]*xrstors \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*0f c7 29[ ]*xsaves \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*0f c7 ac f4 c0 1d fe ff[ ]*xsaves \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*0f c7 19[ ]*xrstors \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*0f c7 9c f4 c0 1d fe ff[ ]*xrstors \[esp\+esi\*8-0x1e240\]
|
||||
#pass
|
||||
20
gas/testsuite/gas/i386/xsaves.d
Normal file
20
gas/testsuite/gas/i386/xsaves.d
Normal file
@ -0,0 +1,20 @@
|
||||
#as:
|
||||
#objdump: -dw
|
||||
#name: i386 XSAVES insns
|
||||
#source: xsaves.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*0f c7 29[ ]*xsaves \(%ecx\)
|
||||
[ ]*[a-f0-9]+:[ ]*0f c7 ac f4 c0 1d fe ff[ ]*xsaves -0x1e240\(%esp,%esi,8\)
|
||||
[ ]*[a-f0-9]+:[ ]*0f c7 19[ ]*xrstors \(%ecx\)
|
||||
[ ]*[a-f0-9]+:[ ]*0f c7 9c f4 c0 1d fe ff[ ]*xrstors -0x1e240\(%esp,%esi,8\)
|
||||
[ ]*[a-f0-9]+:[ ]*0f c7 29[ ]*xsaves \(%ecx\)
|
||||
[ ]*[a-f0-9]+:[ ]*0f c7 ac f4 c0 1d fe ff[ ]*xsaves -0x1e240\(%esp,%esi,8\)
|
||||
[ ]*[a-f0-9]+:[ ]*0f c7 19[ ]*xrstors \(%ecx\)
|
||||
[ ]*[a-f0-9]+:[ ]*0f c7 9c f4 c0 1d fe ff[ ]*xrstors -0x1e240\(%esp,%esi,8\)
|
||||
#pass
|
||||
16
gas/testsuite/gas/i386/xsaves.s
Normal file
16
gas/testsuite/gas/i386/xsaves.s
Normal file
@ -0,0 +1,16 @@
|
||||
# Check 32bit XSAVES instructions
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
|
||||
xsaves (%ecx) # XSAVES
|
||||
xsaves -123456(%esp,%esi,8) # XSAVES
|
||||
xrstors (%ecx) # XSAVES
|
||||
xrstors -123456(%esp,%esi,8) # XSAVES
|
||||
|
||||
.intel_syntax noprefix
|
||||
xsaves [ecx] # XSAVES
|
||||
xsaves [esp+esi*8-123456] # XSAVES
|
||||
xrstors [ecx] # XSAVES
|
||||
xrstors [esp+esi*8-123456] # XSAVES
|
||||
@ -1,3 +1,19 @@
|
||||
2014-02-12 Ilya Tocar <ilya.tocar@intel.com>
|
||||
|
||||
* i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
|
||||
MOD_0FC7_REG_5.
|
||||
(PREFIX enum): Add PREFIX_0FAE_REG_7.
|
||||
(reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
|
||||
(prefix_table): Add clflusopt.
|
||||
(mod_table): Add xrstors, xsavec, xsaves.
|
||||
* i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
|
||||
CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
|
||||
(cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
|
||||
* i386-init.h: Regenerate.
|
||||
* i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
|
||||
xsaves64, xsavec, xsavec64.
|
||||
* i386-tbl.h: Regenerate.
|
||||
|
||||
2014-02-10 Alan Modra <amodra@gmail.com>
|
||||
|
||||
* po/POTFILES.in: Regenerate.
|
||||
|
||||
@ -769,6 +769,9 @@ enum
|
||||
MOD_0FB2,
|
||||
MOD_0FB4,
|
||||
MOD_0FB5,
|
||||
MOD_0FC7_REG_3,
|
||||
MOD_0FC7_REG_4,
|
||||
MOD_0FC7_REG_5,
|
||||
MOD_0FC7_REG_6,
|
||||
MOD_0FC7_REG_7,
|
||||
MOD_0FD7,
|
||||
@ -884,6 +887,7 @@ enum
|
||||
PREFIX_0FAE_REG_1,
|
||||
PREFIX_0FAE_REG_2,
|
||||
PREFIX_0FAE_REG_3,
|
||||
PREFIX_0FAE_REG_7,
|
||||
PREFIX_0FB8,
|
||||
PREFIX_0FBC,
|
||||
PREFIX_0FBD,
|
||||
@ -3354,9 +3358,9 @@ static const struct dis386 reg_table[][8] = {
|
||||
{ Bad_Opcode },
|
||||
{ "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ MOD_TABLE (MOD_0FC7_REG_3) },
|
||||
{ MOD_TABLE (MOD_0FC7_REG_4) },
|
||||
{ MOD_TABLE (MOD_0FC7_REG_5) },
|
||||
{ MOD_TABLE (MOD_0FC7_REG_6) },
|
||||
{ MOD_TABLE (MOD_0FC7_REG_7) },
|
||||
},
|
||||
@ -3759,6 +3763,13 @@ static const struct dis386 prefix_table[][4] = {
|
||||
{ "wrgsbase", { Ev } },
|
||||
},
|
||||
|
||||
/* PREFIX_0FAE_REG_7 */
|
||||
{
|
||||
{ "clflush", { Mb } },
|
||||
{ Bad_Opcode },
|
||||
{ "clflushopt", { Mb } },
|
||||
},
|
||||
|
||||
/* PREFIX_0FB8 */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
@ -11286,7 +11297,7 @@ static const struct dis386 mod_table[][2] = {
|
||||
},
|
||||
{
|
||||
/* MOD_0FAE_REG_7 */
|
||||
{ "clflush", { Mb } },
|
||||
{ PREFIX_TABLE (PREFIX_0FAE_REG_7) },
|
||||
{ RM_TABLE (RM_0FAE_REG_7) },
|
||||
},
|
||||
{
|
||||
@ -11301,6 +11312,18 @@ static const struct dis386 mod_table[][2] = {
|
||||
/* MOD_0FB5 */
|
||||
{ "lgsS", { Gv, Mp } },
|
||||
},
|
||||
{
|
||||
/* MOD_0FC7_REG_3 */
|
||||
{ "xrstors", { FXSAVE } },
|
||||
},
|
||||
{
|
||||
/* MOD_0FC7_REG_4 */
|
||||
{ "xsavec", { FXSAVE } },
|
||||
},
|
||||
{
|
||||
/* MOD_0FC7_REG_5 */
|
||||
{ "xsaves", { FXSAVE } },
|
||||
},
|
||||
{
|
||||
/* MOD_0FC7_REG_6 */
|
||||
{ PREFIX_TABLE (PREFIX_0FC7_REG_6) },
|
||||
|
||||
@ -222,6 +222,12 @@ static initializer cpu_flag_init[] =
|
||||
"CpuMPX" },
|
||||
{ "CPU_SHA_FLAGS",
|
||||
"CpuSHA" },
|
||||
{ "CPU_CLFLUSHOPT_FLAGS",
|
||||
"CpuClflushOpt" },
|
||||
{ "CPU_XSAVES_FLAGS",
|
||||
"CpuXSAVES" },
|
||||
{ "CPU_XSAVEC_FLAGS",
|
||||
"CpuXSAVEC" },
|
||||
};
|
||||
|
||||
static initializer operand_type_init[] =
|
||||
@ -410,6 +416,9 @@ static bitfield cpu_flags[] =
|
||||
BITFIELD (CpuSMAP),
|
||||
BITFIELD (CpuSHA),
|
||||
BITFIELD (CpuVREX),
|
||||
BITFIELD (CpuClflushOpt),
|
||||
BITFIELD (CpuXSAVES),
|
||||
BITFIELD (CpuXSAVEC),
|
||||
BITFIELD (Cpu64),
|
||||
BITFIELD (CpuNo64),
|
||||
BITFIELD (CpuMPX),
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/* This file is automatically generated by i386-gen. Do not edit! */
|
||||
/* Copyright 2007, 2008, 2009, 2010, 2011, 2012, 2013
|
||||
/* Copyright 2007-2014
|
||||
Free Software Foundation, Inc.
|
||||
|
||||
This file is part of the GNU opcodes library.
|
||||
@ -23,541 +23,559 @@
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
|
||||
|
||||
#define CPU_GENERIC32_FLAGS \
|
||||
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_GENERIC64_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_NONE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I186_FLAGS \
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I286_FLAGS \
|
||||
{ { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I386_FLAGS \
|
||||
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I486_FLAGS \
|
||||
{ { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I586_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I686_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_PENTIUMPRO_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_P2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_P3_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 1, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_P4_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_NOCONA_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CORE_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CORE2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_COREI7_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_K6_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_K6_2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ATHLON_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_K8_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AMDFAM10_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_BDVER1_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, \
|
||||
1, 0, 1, 1, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_BDVER2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_BDVER3_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_BDVER4_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_BTVER1_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_BTVER2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
|
||||
1, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_8087_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_287_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_387_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ANY87_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CLFLUSH_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_NOP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SYSCALL_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_MMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE3_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSSE3_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4_1_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4_2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ANY_SSE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_VMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_XSAVE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_XSAVEOPT_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AES_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_PCLMUL_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_FMA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_FMA4_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_XOP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_LWP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_BMI_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_TBM_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_MOVBE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CX16_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_RDTSCP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_EPT_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_FSGSBASE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_RDRND_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_F16C_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_BMI2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_LZCNT_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_HLE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_RTM_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_INVPCID_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_VMFUNC_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_3DNOW_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_3DNOWA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_PADLOCK_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SVME_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4A_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ABM_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AVX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AVX2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AVX512F_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AVX512CD_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AVX512ER_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AVX512PF_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ANY_AVX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_L1OM_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
|
||||
|
||||
#define CPU_K1OM_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
|
||||
|
||||
#define CPU_ADX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_RDSEED_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_PRFCHW_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SMAP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_MPX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SHA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CLFLUSHOPT_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_XSAVES_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_XSAVEC_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
|
||||
|
||||
#define OPERAND_TYPE_NONE \
|
||||
|
||||
@ -169,6 +169,12 @@ enum
|
||||
CpuSHA,
|
||||
/* VREX support required */
|
||||
CpuVREX,
|
||||
/* CLFLUSHOPT instruction required */
|
||||
CpuClflushOpt,
|
||||
/* XSAVES/XRSTORS instruction required */
|
||||
CpuXSAVES,
|
||||
/* XSAVEC instruction required */
|
||||
CpuXSAVEC,
|
||||
/* 64bit support required */
|
||||
Cpu64,
|
||||
/* Not supported in the 64bit mode */
|
||||
@ -260,6 +266,9 @@ typedef union i386_cpu_flags
|
||||
unsigned int cpusmap:1;
|
||||
unsigned int cpusha:1;
|
||||
unsigned int cpuvrex:1;
|
||||
unsigned int cpuclflushopt:1;
|
||||
unsigned int cpuxsaves:1;
|
||||
unsigned int cpuxsavec:1;
|
||||
unsigned int cpu64:1;
|
||||
unsigned int cpuno64:1;
|
||||
#ifdef CpuUnused
|
||||
|
||||
@ -4291,3 +4291,25 @@ vscatterpf1qps, 1, 0x66C7, 6, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|V
|
||||
prefetchwt1, 1, 0x0F0D, 2, 2, CpuAVX512PF, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
|
||||
// AVX512PF instructions end.
|
||||
|
||||
// CLFLUSHOPT instructions.
|
||||
|
||||
clflushopt, 1, 0x660fae, 0x7, 2, CpuClflushOpt, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
|
||||
// CLFLUSHOPT instructions end.
|
||||
|
||||
// XSAVES/XRSTORS instructions.
|
||||
|
||||
xrstors, 1, 0xfc7, 0x3, 2, CpuXSAVES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
xrstors64, 1, 0xfc7, 0x3, 2, CpuXSAVES|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
xsaves, 1, 0xfc7, 0x5, 2, CpuXSAVES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
xsaves64, 1, 0xfc7, 0x5, 2, CpuXSAVES|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
|
||||
// XSAVES instructions end.
|
||||
|
||||
// XSAVEC instructions.
|
||||
|
||||
xsavec, 1, 0xfc7, 0x4, 2, CpuXSAVEC, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
xsavec64, 1, 0xfc7, 0x4, 2, CpuXSAVEC|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
|
||||
// XSAVEC instructions end.
|
||||
|
||||
7588
opcodes/i386-tbl.h
7588
opcodes/i386-tbl.h
File diff suppressed because it is too large
Load Diff
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Reference in New Issue
Block a user