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2002-12-04 Aldy Hernandez <aldyh@redhat.com>
* ppc-opc.c (PMRN): Remove. (RA): Set to NB + 1. (powerpc_opcodes): Change PMRN to SPR. Change all RD to RS. Change mftb to look like mftbl. Move mftb before mftbl. Add mfbbtar. Add mtbbtar. Change mfpmr to use PMR. Change mtpmr to use PMR. (RD): Remove. (insert_ev2): Fix mask and shift. (extract_ev2): Same. (insert_ev4): Same. (extract_ev4): Same. (PMR): Define. (extract_pmrn): Remove. (insert_pmrn): Remove.
This commit is contained in:
Aldy Hernandez
parent
45bcbdb112
commit
914749f6ed
@ -1,3 +1,24 @@
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2002-12-04 Aldy Hernandez <aldyh@redhat.com>
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* ppc-opc.c (PMRN): Remove.
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(RA): Set to NB + 1.
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(powerpc_opcodes): Change PMRN to SPR.
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Change all RD to RS.
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Change mftb to look like mftbl.
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Move mftb before mftbl.
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Add mfbbtar.
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Add mtbbtar.
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Change mfpmr to use PMR.
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Change mtpmr to use PMR.
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(RD): Remove.
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(insert_ev2): Fix mask and shift.
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(extract_ev2): Same.
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(insert_ev4): Same.
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(extract_ev4): Same.
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(PMR): Define.
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(extract_pmrn): Remove.
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(insert_pmrn): Remove.
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2002-12-03 Richard Henderson <rth@redhat.com>
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* ia64-opc-m.c: Add ld8.mov.
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@ -100,10 +100,6 @@ static unsigned long insert_nsi
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PARAMS ((unsigned long, long, int, const char **));
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static long extract_nsi
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PARAMS ((unsigned long, int, int *));
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static unsigned long insert_pmrn
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PARAMS ((unsigned long, long, int, const char **));
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static long extract_pmrn
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PARAMS ((unsigned long, int, int *));
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static unsigned long insert_ral
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PARAMS ((unsigned long, long, int, const char **));
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static unsigned long insert_ram
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@ -265,7 +261,6 @@ const struct powerpc_operand powerpc_operands[] =
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/* The CT field in an X form instruction. */
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#define CT CRFS + 1
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#define RD CT
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{ 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },
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/* The D field in a D form instruction. This is a displacement off
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@ -394,12 +389,8 @@ const struct powerpc_operand powerpc_operands[] =
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{ 16, 0, insert_nsi, extract_nsi,
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PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
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/* The PMRN field in an X form instruction. */
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#define PMRN NSI + 1
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{ 16, 0, insert_pmrn, extract_pmrn, PPC_OPERAND_GPR },
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/* The RA field in an D, DS, X, XO, M, or MDS form instruction. */
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#define RA PMRN + 1
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#define RA NSI + 1
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#define RA_MASK (0x1f << 16)
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{ 5, 16, 0, 0, PPC_OPERAND_GPR },
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@ -461,6 +452,7 @@ const struct powerpc_operand powerpc_operands[] =
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/* The SPR field in an XFX form instruction. This is flipped--the
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lower 5 bits are stored in the upper 5 and vice- versa. */
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#define SPR SISIGNOPT + 1
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#define PMR SPR
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#define SPR_MASK (0x3ff << 11)
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{ 10, 11, insert_spr, extract_spr, 0 },
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@ -889,7 +881,7 @@ insert_ev2 (insn, value, dialect, errmsg)
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*errmsg = _("offset not a multiple of 2");
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if ((value > 62) != 0 && errmsg != NULL)
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*errmsg = _("offset greater than 62");
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return insn | ((value & 0xf8) << 8);
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return insn | ((value & 0x3e) << 10);
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}
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static long
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@ -898,7 +890,7 @@ extract_ev2 (insn, dialect, invalid)
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int dialect ATTRIBUTE_UNUSED;
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int * invalid ATTRIBUTE_UNUSED;
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{
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return (insn >> 8) & 0xf8;
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return (insn >> 10) & 0x3e;
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}
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static unsigned long
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@ -912,7 +904,7 @@ insert_ev4 (insn, value, dialect, errmsg)
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*errmsg = _("offset not a multiple of 4");
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if ((value > 124) != 0 && errmsg != NULL)
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*errmsg = _("offset greater than 124");
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return insn | ((value & 0xf8) << 8);
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return insn | ((value & 0x7c) << 9);
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}
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static long
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@ -921,7 +913,7 @@ extract_ev4 (insn, dialect, invalid)
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int dialect ATTRIBUTE_UNUSED;
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int * invalid ATTRIBUTE_UNUSED;
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{
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return (insn >> 8) & 0xf8;
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return (insn >> 9) & 0x7c;
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}
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static unsigned long
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@ -1229,28 +1221,6 @@ extract_nsi (insn, dialect, invalid)
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return - (((insn & 0xffff) ^ 0x8000) - 0x8000);
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}
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/* The PMRN field in a X form instruction.
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This has 5+5 bits switched around. */
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static unsigned long
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insert_pmrn (insn, value, dialect, errmsg)
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unsigned long insn;
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long value;
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int dialect ATTRIBUTE_UNUSED;
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const char **errmsg ATTRIBUTE_UNUSED;
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{
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return insn | ((value & 0x1f) << 16) | ((value & 0x3e) << 11);
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}
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static long
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extract_pmrn (insn, dialect, invalid)
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unsigned long insn;
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int dialect ATTRIBUTE_UNUSED;
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int *invalid ATTRIBUTE_UNUSED;
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{
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return ((insn >> 16) & 0x1f) | ((insn >> 11) & 0x3e);
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}
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/* The RA field in a D or X form instruction which is an updating
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load, which means that the RA field may not be zero and may not
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equal the RT field. */
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@ -2087,43 +2057,43 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
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{ "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
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{ "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RD, RA, RB } },
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{ "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RD, RB, UIMM } },
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{ "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RD, RA, RB } },
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{ "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RD, RB, RA } },
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{ "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RD, UIMM, RB } },
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{ "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RD, RB, UIMM } },
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{ "evabs", VX(4, 520), VX_MASK, PPCSPE, { RD, RA } },
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{ "evneg", VX(4, 521), VX_MASK, PPCSPE, { RD, RA } },
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{ "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RD, RA } },
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{ "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RD, RA } },
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{ "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RD, RA } },
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{ "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RD, RA } },
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{ "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RD, RA } },
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{ "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } },
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{ "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } },
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{ "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } },
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{ "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } },
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{ "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } },
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{ "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } },
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{ "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } },
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{ "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } },
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{ "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } },
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{ "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } },
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{ "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } },
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{ "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } },
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{ "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } },
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{ "brinc", VX(4, 527), VX_MASK, PPCSPE, { RD, RA, RB } },
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{ "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } },
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{ "evand", VX(4, 529), VX_MASK, PPCSPE, { RD, RA, RB } },
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{ "evandc", VX(4, 530), VX_MASK, PPCSPE, { RD, RA, RB } },
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{ "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } },
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{ "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } },
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{ "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } },
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{ "evor", VX(4, 535), VX_MASK, PPCSPE, { RD, RA, RB } },
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{ "evorc", VX(4, 539), VX_MASK, PPCSPE, { RD, RA, RB } },
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{ "evxor", VX(4, 534), VX_MASK, PPCSPE, { RD, RA, RB } },
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{ "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RD, RA, RB } },
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{ "evnand", VX(4, 542), VX_MASK, PPCSPE, { RD, RA, RB } },
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{ "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } },
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{ "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } },
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{ "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } },
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{ "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } },
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{ "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } },
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{ "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } },
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{ "evnor", VX(4, 536), VX_MASK, PPCSPE, { RD, RA, RB } },
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{ "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } },
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{ "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RD, RA, RB } },
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{ "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RD, RA, EVUIMM } },
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{ "evslw", VX(4, 548), VX_MASK, PPCSPE, { RD, RA, RB } },
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{ "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RD, RA, EVUIMM } },
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{ "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RD, RA, RB } },
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{ "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RD, RA, RB } },
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{ "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RD, RA, EVUIMM } },
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{ "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RD, RA, EVUIMM } },
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{ "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RD, SIMM } },
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{ "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RD, SIMM } },
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{ "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } },
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{ "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
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{ "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } },
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{ "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
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{ "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } },
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{ "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } },
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{ "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
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{ "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
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{ "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } },
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{ "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } },
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{ "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } },
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{ "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } },
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{ "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } },
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@ -2134,7 +2104,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } },
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{ "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } },
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{ "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } },
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{ "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RD, RA, RB, CRFS } },
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{ "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } },
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{ "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
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{ "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } },
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@ -2174,222 +2144,222 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
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{ "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } },
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{ "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RD, RA } },
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{ "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RD, RA } },
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{ "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RD, RA } },
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{ "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RD, RA, RB } },
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{ "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RD, RA, RB } },
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{ "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RD, RA, RB } },
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{ "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RD, RA, RB } },
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{ "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } },
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{ "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } },
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{ "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } },
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{ "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } },
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{ "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } },
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{ "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } },
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{ "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } },
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{ "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } },
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{ "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } },
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{ "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } },
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{ "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } },
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{ "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } },
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{ "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } },
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{ "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RD, RB } },
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{ "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RD, RB } },
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{ "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RD, RB } },
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{ "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RD, RB } },
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{ "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RD, RB } },
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{ "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RD, RB } },
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{ "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RD, RB } },
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{ "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RD, RB } },
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{ "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RD, RB } },
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{ "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RD, RB } },
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{ "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } },
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{ "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } },
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{ "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } },
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{ "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } },
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{ "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } },
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{ "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } },
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{ "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } },
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{ "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } },
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{ "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } },
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{ "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } },
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{ "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RD, RA } },
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{ "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RD, RA } },
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{ "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RD, RA } },
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{ "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RD, RA, RB } },
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{ "efssub", VX(4, 705), VX_MASK, PPCEFS, { RD, RA, RB } },
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{ "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RD, RA, RB } },
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{ "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RD, RA, RB } },
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{ "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } },
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{ "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } },
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{ "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } },
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{ "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } },
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{ "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } },
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{ "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } },
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{ "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } },
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{ "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } },
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||||
{ "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } },
|
||||
{ "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } },
|
||||
{ "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } },
|
||||
{ "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } },
|
||||
{ "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } },
|
||||
{ "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RD, RB } },
|
||||
{ "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RD, RB } },
|
||||
{ "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RD, RB } },
|
||||
{ "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RD, RB } },
|
||||
{ "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RD, RB } },
|
||||
{ "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RD, RB } },
|
||||
{ "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RD, RB } },
|
||||
{ "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RD, RB } },
|
||||
{ "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RD, RB } },
|
||||
{ "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RD, RB } },
|
||||
{ "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } },
|
||||
{ "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } },
|
||||
{ "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } },
|
||||
{ "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } },
|
||||
{ "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } },
|
||||
{ "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } },
|
||||
{ "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } },
|
||||
{ "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } },
|
||||
{ "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } },
|
||||
{ "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } },
|
||||
|
||||
{ "evsabs", VX(4, 708), VX_MASK, PPCSPE, { RD, RA } },
|
||||
{ "evsnabs", VX(4, 709), VX_MASK, PPCSPE, { RD, RA } },
|
||||
{ "evsneg", VX(4, 710), VX_MASK, PPCSPE, { RD, RA } },
|
||||
{ "evsadd", VX(4, 704), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evssub", VX(4, 705), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evsmul", VX(4, 712), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evsdiv", VX(4, 713), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evsabs", VX(4, 708), VX_MASK, PPCSPE, { RS, RA } },
|
||||
{ "evsnabs", VX(4, 709), VX_MASK, PPCSPE, { RS, RA } },
|
||||
{ "evsneg", VX(4, 710), VX_MASK, PPCSPE, { RS, RA } },
|
||||
{ "evsadd", VX(4, 704), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evssub", VX(4, 705), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evsmul", VX(4, 712), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evsdiv", VX(4, 713), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evscmpgt", VX(4, 716), VX_MASK, PPCSPE, { CRFD, RA, RB } },
|
||||
{ "evsgmplt", VX(4, 717), VX_MASK, PPCSPE, { CRFD, RA, RB } },
|
||||
{ "evsgmpeq", VX(4, 718), VX_MASK, PPCSPE, { CRFD, RA, RB } },
|
||||
{ "evststgt", VX(4, 732), VX_MASK, PPCSPE, { CRFD, RA, RB } },
|
||||
{ "evststlt", VX(4, 733), VX_MASK, PPCSPE, { CRFD, RA, RB } },
|
||||
{ "evststeq", VX(4, 734), VX_MASK, PPCSPE, { CRFD, RA, RB } },
|
||||
{ "evscfui", VX(4, 720), VX_MASK, PPCSPE, { RD, RB } },
|
||||
{ "evscfsi", VX(4, 721), VX_MASK, PPCSPE, { RD, RB } },
|
||||
{ "evscfuf", VX(4, 722), VX_MASK, PPCSPE, { RD, RB } },
|
||||
{ "evscfsf", VX(4, 723), VX_MASK, PPCSPE, { RD, RB } },
|
||||
{ "evsctui", VX(4, 724), VX_MASK, PPCSPE, { RD, RB } },
|
||||
{ "evsctuiz", VX(4, 728), VX_MASK, PPCSPE, { RD, RB } },
|
||||
{ "evsctsi", VX(4, 725), VX_MASK, PPCSPE, { RD, RB } },
|
||||
{ "evsctsiz", VX(4, 730), VX_MASK, PPCSPE, { RD, RB } },
|
||||
{ "evsctuf", VX(4, 726), VX_MASK, PPCSPE, { RD, RB } },
|
||||
{ "evsctsf", VX(4, 727), VX_MASK, PPCSPE, { RD, RB } },
|
||||
{ "evscfui", VX(4, 720), VX_MASK, PPCSPE, { RS, RB } },
|
||||
{ "evscfsi", VX(4, 721), VX_MASK, PPCSPE, { RS, RB } },
|
||||
{ "evscfuf", VX(4, 722), VX_MASK, PPCSPE, { RS, RB } },
|
||||
{ "evscfsf", VX(4, 723), VX_MASK, PPCSPE, { RS, RB } },
|
||||
{ "evsctui", VX(4, 724), VX_MASK, PPCSPE, { RS, RB } },
|
||||
{ "evsctuiz", VX(4, 728), VX_MASK, PPCSPE, { RS, RB } },
|
||||
{ "evsctsi", VX(4, 725), VX_MASK, PPCSPE, { RS, RB } },
|
||||
{ "evsctsiz", VX(4, 730), VX_MASK, PPCSPE, { RS, RB } },
|
||||
{ "evsctuf", VX(4, 726), VX_MASK, PPCSPE, { RS, RB } },
|
||||
{ "evsctsf", VX(4, 727), VX_MASK, PPCSPE, { RS, RB } },
|
||||
|
||||
{ "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
|
||||
{ "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
|
||||
{ "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
|
||||
{ "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
|
||||
{ "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
|
||||
{ "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
|
||||
{ "evmwlssf", VX(4, 1091), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwlssfa", VX(4, 1123), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwlsmf", VX(4, 1099), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwlsmfa", VX(4, 1131), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwlssf", VX(4, 1091), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwlssfa", VX(4, 1123), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwlsmf", VX(4, 1099), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwlsmfa", VX(4, 1131), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
|
||||
{ "evmwhssfaa",VX(4, 1351), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwhssmaa",VX(4, 1349), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwhsmfaa",VX(4, 1359), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwhsmiaa",VX(4, 1357), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwhusiaa",VX(4, 1348), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwhumiaa",VX(4, 1356), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwhssfaa",VX(4, 1351), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwhssmaa",VX(4, 1349), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwhsmfaa",VX(4, 1359), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwhsmiaa",VX(4, 1357), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwhusiaa",VX(4, 1348), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwhumiaa",VX(4, 1356), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
|
||||
{ "evmwlssfaaw",VX(4, 1347), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwlsmfaaw",VX(4, 1355), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwlssfaaw",VX(4, 1347), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwlsmfaaw",VX(4, 1355), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
|
||||
{ "evmwhssfan",VX(4, 1479), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwhssian",VX(4, 1477), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwhsmfan",VX(4, 1487), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwhsmian",VX(4, 1485), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwhusian",VX(4, 1476), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwhumian",VX(4, 1484), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwhssfan",VX(4, 1479), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwhssian",VX(4, 1477), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwhsmfan",VX(4, 1487), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwhsmian",VX(4, 1485), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwhusian",VX(4, 1476), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwhumian",VX(4, 1484), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
|
||||
{ "evmwlssfanw",VX(4, 1475), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwlsmfanw",VX(4, 1483), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwlssfanw",VX(4, 1475), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwlsmfanw",VX(4, 1483), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
|
||||
{ "evmwhgssfaa",VX(4, 1383), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwhgsmfaa",VX(4, 1391), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwhgsmiaa",VX(4, 1381), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwhgumiaa",VX(4, 1380), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwhgssfaa",VX(4, 1383), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwhgsmfaa",VX(4, 1391), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwhgsmiaa",VX(4, 1381), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwhgumiaa",VX(4, 1380), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
|
||||
{ "evmwhgssfan",VX(4, 1511), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwhgsmfan",VX(4, 1519), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwhgsmian",VX(4, 1509), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwhgumian",VX(4, 1508), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwhgssfan",VX(4, 1511), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwhgsmfan",VX(4, 1519), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwhgsmian",VX(4, 1509), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwhgumian",VX(4, 1508), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
|
||||
{ "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
|
||||
{ "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
|
||||
{ "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
|
||||
{ "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RD, RA } },
|
||||
{ "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RD, RA } },
|
||||
{ "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RD, RA } },
|
||||
{ "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RD, RA } },
|
||||
{ "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } },
|
||||
{ "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } },
|
||||
{ "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } },
|
||||
{ "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } },
|
||||
|
||||
{ "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RD, RA } },
|
||||
{ "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RD, RA } },
|
||||
{ "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RD, RA } },
|
||||
{ "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RD, RA } },
|
||||
{ "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } },
|
||||
{ "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } },
|
||||
{ "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } },
|
||||
{ "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } },
|
||||
|
||||
{ "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RD, RA } },
|
||||
{ "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } },
|
||||
|
||||
{ "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RD, RA, RB } },
|
||||
{ "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
{ "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } },
|
||||
|
||||
{ "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
|
||||
{ "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
|
||||
@ -3627,7 +3597,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
||||
{ "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
|
||||
{ "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
|
||||
|
||||
{ "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMRN }},
|
||||
{ "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
|
||||
|
||||
{ "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } },
|
||||
{ "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
|
||||
@ -3672,6 +3642,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
||||
{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405, { RT } },
|
||||
{ "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
|
||||
{ "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
|
||||
{ "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } },
|
||||
{ "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } },
|
||||
@ -3715,6 +3686,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
||||
{ "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } },
|
||||
{ "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } },
|
||||
{ "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } },
|
||||
{ "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } },
|
||||
{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
|
||||
{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
|
||||
{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
|
||||
@ -3835,8 +3807,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
||||
|
||||
{ "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
|
||||
{ "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
|
||||
{ "mftb", X(31,371), X_MASK, BOOKE, { RT, TBR } },
|
||||
{ "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
|
||||
|
||||
{ "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
|
||||
|
||||
@ -4030,6 +4000,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
||||
{ "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } },
|
||||
{ "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RT } },
|
||||
{ "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } },
|
||||
{ "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } },
|
||||
{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
|
||||
{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
|
||||
{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
|
||||
@ -4103,7 +4074,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
||||
|
||||
{ "dcread", X(31,486), X_MASK, PPC403, { RT, RA, RB }},
|
||||
|
||||
{ "mtpmr", X(31,462), X_MASK, PPCPMR, { PMRN, RS }},
|
||||
{ "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
|
||||
|
||||
{ "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }},
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user