mirror/binutils-gdb
2
0
Fork 0
mirror of https://sourceware.org/git/binutils-gdb.git synced 2025-01-18 12:24:38 +08:00
Code Issues Packages Projects Releases Wiki Activity

aarch64: Add the RPRFM instruction

Browse Source 
This patch adds the RPRFM (range prefetch) instruction.
It was introduced as part of SME2, but it belongs to the
prefetch hint space and so doesn't require any specific
ISA flags.

The aarch64_rprfmop_array initialiser (deliberately) only
fills in the leading non-null elements.
This commit is contained in:
Richard Sandiford 2023-03-30 11:09:18 +01:00
parent e4cf4736e9
commit 8ff429203d
14 changed files with 1113 additions and 886 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
gas/config/tc-aarch64.c
View File

@ -7773,6 +7773,11 @@ parse_operands (char *str, const aarch64_opcode *opcode)
inst.base.operands[i].prfop = aarch64_prfops + val;
break;
case AARCH64_OPND_RPRFMOP:
po_enum_or_fail (aarch64_rprfmop_array);
info->imm.value = val;
break;
case AARCH64_OPND_BARRIER_PSB:
val = parse_barrier_psb (&str, &(info->hint_option));
if (val == PARSE_FAIL)

3
gas/testsuite/gas/aarch64/rprfm-1-invalid.d Normal file
View File

@ -0,0 +1,3 @@
#as: -march=armv8-a
#source: rprfm-1-invalid.s
#error_output: rprfm-1-invalid.l

11
gas/testsuite/gas/aarch64/rprfm-1-invalid.l Normal file
View File

@ -0,0 +1,11 @@
[^ :]+: Assembler messages:
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `rprfm pldkeep,0,\[x0\]'
[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `rprfm pldkeep,x0,0'
[^ :]+:[0-9]+: Error: operand 1 must be a range prefetch operation specifier -- `rprfm pldl1keep,x0,\[x0\]'
[^ :]+:[0-9]+: Error: operand 1 must be a range prefetch operation specifier -- `rprfm #-1,x0,\[x0\]'
[^ :]+:[0-9]+: Error: operand 1 must be a range prefetch operation specifier -- `rprfm #64,x0,\[x0\]'
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `rprfm #1,sp,\[x0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `rprfm #1,w0,\[x0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: rprfm pstkeep, x0, \[x0\]
[^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `rprfm #1,x0,\[xzr\]'

9
gas/testsuite/gas/aarch64/rprfm-1-invalid.s Normal file
View File

@ -0,0 +1,9 @@
rprfm pldkeep, 0, [x0]
rprfm pldkeep, x0, 0
rprfm pldl1keep, x0, [x0]
rprfm #-1, x0, [x0]
rprfm #64, x0, [x0]
rprfm #1, sp, [x0]
rprfm #1, w0, [x0]
rprfm #1, x0, [xzr]

83
gas/testsuite/gas/aarch64/rprfm-1.d Normal file
View File

@ -0,0 +1,83 @@
#as: -march=armv8-a
#objdump: -dr
[^:]+: file format .*
[^:]+:
[^:]+:
[^:]+: f8a04818 rprfm pldkeep, x0, \[x0\]
[^:]+: f8a0481c rprfm pldstrm, x0, \[x0\]
[^:]+: f8a04819 rprfm pstkeep, x0, \[x0\]
[^:]+: f8a0481d rprfm pststrm, x0, \[x0\]
[^:]+: f8a04818 rprfm pldkeep, x0, \[x0\]
[^:]+: f8a04819 rprfm pstkeep, x0, \[x0\]
[^:]+: f8a0481a rprfm #2, x0, \[x0\]
[^:]+: f8a0481b rprfm #3, x0, \[x0\]
[^:]+: f8a0481c rprfm pldstrm, x0, \[x0\]
[^:]+: f8a0481d rprfm pststrm, x0, \[x0\]
[^:]+: f8a0481e rprfm #6, x0, \[x0\]
[^:]+: f8a0481f rprfm #7, x0, \[x0\]
[^:]+: f8a05818 rprfm #8, x0, \[x0\]
[^:]+: f8a05819 rprfm #9, x0, \[x0\]
[^:]+: f8a0581a rprfm #10, x0, \[x0\]
[^:]+: f8a0581b rprfm #11, x0, \[x0\]
[^:]+: f8a0581c rprfm #12, x0, \[x0\]
[^:]+: f8a0581d rprfm #13, x0, \[x0\]
[^:]+: f8a0581e rprfm #14, x0, \[x0\]
[^:]+: f8a0581f rprfm #15, x0, \[x0\]
[^:]+: f8a06818 rprfm #16, x0, \[x0\]
[^:]+: f8a06819 rprfm #17, x0, \[x0\]
[^:]+: f8a0681a rprfm #18, x0, \[x0\]
[^:]+: f8a0681b rprfm #19, x0, \[x0\]
[^:]+: f8a0681c rprfm #20, x0, \[x0\]
[^:]+: f8a0681d rprfm #21, x0, \[x0\]
[^:]+: f8a0681e rprfm #22, x0, \[x0\]
[^:]+: f8a0681f rprfm #23, x0, \[x0\]
[^:]+: f8a07818 rprfm #24, x0, \[x0\]
[^:]+: f8a07819 rprfm #25, x0, \[x0\]
[^:]+: f8a0781a rprfm #26, x0, \[x0\]
[^:]+: f8a0781b rprfm #27, x0, \[x0\]
[^:]+: f8a0781c rprfm #28, x0, \[x0\]
[^:]+: f8a0781d rprfm #29, x0, \[x0\]
[^:]+: f8a0781e rprfm #30, x0, \[x0\]
[^:]+: f8a0781f rprfm #31, x0, \[x0\]
[^:]+: f8a0c818 rprfm #32, x0, \[x0\]
[^:]+: f8a0c819 rprfm #33, x0, \[x0\]
[^:]+: f8a0c81a rprfm #34, x0, \[x0\]
[^:]+: f8a0c81b rprfm #35, x0, \[x0\]
[^:]+: f8a0c81c rprfm #36, x0, \[x0\]
[^:]+: f8a0c81d rprfm #37, x0, \[x0\]
[^:]+: f8a0c81e rprfm #38, x0, \[x0\]
[^:]+: f8a0c81f rprfm #39, x0, \[x0\]
[^:]+: f8a0d818 rprfm #40, x0, \[x0\]
[^:]+: f8a0d818 rprfm #40, x0, \[x0\]
[^:]+: f8a0d819 rprfm #41, x0, \[x0\]
[^:]+: f8a0d81a rprfm #42, x0, \[x0\]
[^:]+: f8a0d81b rprfm #43, x0, \[x0\]
[^:]+: f8a0d81c rprfm #44, x0, \[x0\]
[^:]+: f8a0d81d rprfm #45, x0, \[x0\]
[^:]+: f8a0d81e rprfm #46, x0, \[x0\]
[^:]+: f8a0d81f rprfm #47, x0, \[x0\]
[^:]+: f8a0e818 rprfm #48, x0, \[x0\]
[^:]+: f8a0e819 rprfm #49, x0, \[x0\]
[^:]+: f8a0e81a rprfm #50, x0, \[x0\]
[^:]+: f8a0e81b rprfm #51, x0, \[x0\]
[^:]+: f8a0e81c rprfm #52, x0, \[x0\]
[^:]+: f8a0e81d rprfm #53, x0, \[x0\]
[^:]+: f8a0e81e rprfm #54, x0, \[x0\]
[^:]+: f8a0e81f rprfm #55, x0, \[x0\]
[^:]+: f8a0f818 rprfm #56, x0, \[x0\]
[^:]+: f8a0f819 rprfm #57, x0, \[x0\]
[^:]+: f8a0f81a rprfm #58, x0, \[x0\]
[^:]+: f8a0f81b rprfm #59, x0, \[x0\]
[^:]+: f8a0f81c rprfm #60, x0, \[x0\]
[^:]+: f8a0f81d rprfm #61, x0, \[x0\]
[^:]+: f8a0f81e rprfm #62, x0, \[x0\]
[^:]+: f8a0f81f rprfm #63, x0, \[x0\]
[^:]+: f8be4818 rprfm pldkeep, x30, \[x0\]
[^:]+: f8bf4818 rprfm pldkeep, xzr, \[x0\]
[^:]+: f8a04bd8 rprfm pldkeep, x0, \[x30\]
[^:]+: f8a04bf8 rprfm pldkeep, x0, \[sp\]
[^:]+: f8b5cb7f rprfm #39, x21, \[x27\]

74
gas/testsuite/gas/aarch64/rprfm-1.s Normal file
View File

@ -0,0 +1,74 @@
rprfm pldkeep, x0, [x0]
rprfm pldstrm, x0, [x0]
rprfm pstkeep, x0, [x0]
rprfm pststrm, x0, [x0]
rprfm #0, x0, [x0]
rprfm #1, x0, [x0]
rprfm #2, x0, [x0]
rprfm #3, x0, [x0]
rprfm #4, x0, [x0]
rprfm #5, x0, [x0]
rprfm #6, x0, [x0]
rprfm #7, x0, [x0]
rprfm #8, x0, [x0]
rprfm #9, x0, [x0]
rprfm #10, x0, [x0]
rprfm #11, x0, [x0]
rprfm #12, x0, [x0]
rprfm #13, x0, [x0]
rprfm #14, x0, [x0]
rprfm #15, x0, [x0]
rprfm #16, x0, [x0]
rprfm #17, x0, [x0]
rprfm #18, x0, [x0]
rprfm #19, x0, [x0]
rprfm #20, x0, [x0]
rprfm #21, x0, [x0]
rprfm #22, x0, [x0]
rprfm #23, x0, [x0]
rprfm #24, x0, [x0]
rprfm #25, x0, [x0]
rprfm #26, x0, [x0]
rprfm #27, x0, [x0]
rprfm #28, x0, [x0]
rprfm #29, x0, [x0]
rprfm #30, x0, [x0]
rprfm #31, x0, [x0]
rprfm #32, x0, [x0]
rprfm #33, x0, [x0]
rprfm #34, x0, [x0]
rprfm #35, x0, [x0]
rprfm #36, x0, [x0]
rprfm #37, x0, [x0]
rprfm #38, x0, [x0]
rprfm #39, x0, [x0]
rprfm #40, x0, [x0]
rprfm #40, x0, [x0]
rprfm #41, x0, [x0]
rprfm #42, x0, [x0]
rprfm #43, x0, [x0]
rprfm #44, x0, [x0]
rprfm #45, x0, [x0]
rprfm #46, x0, [x0]
rprfm #47, x0, [x0]
rprfm #48, x0, [x0]
rprfm #49, x0, [x0]
rprfm #50, x0, [x0]
rprfm #51, x0, [x0]
rprfm #52, x0, [x0]
rprfm #53, x0, [x0]
rprfm #54, x0, [x0]
rprfm #55, x0, [x0]
rprfm #56, x0, [x0]
rprfm #57, x0, [x0]
rprfm #58, x0, [x0]
rprfm #59, x0, [x0]
rprfm #60, x0, [x0]
rprfm #61, x0, [x0]
rprfm #62, x0, [x0]
rprfm #63, x0, [x0]
rprfm #0, x30, [x0]
rprfm #0, xzr, [x0]
rprfm #0, x0, [x30]
rprfm #0, x0, [sp]
rprfm #39, x21, [x27]

2
gas/testsuite/gas/aarch64/system.d
View File

@ -371,4 +371,4 @@ Disassembly of section \.text:
.*: f9800c74 prfm pstl3keep, \[x3, #24\]
.*: f9800c75 prfm pstl3strm, \[x3, #24\]
.*: f8a04817 prfm #0x17, \[x0, w0, uxtw\]
.*: f8a04818 \.inst 0xf8a04818 ; undefined
.*: f8a04818 rprfm pldkeep, x0, \[x0\]

2
include/opcode/aarch64.h
View File

@ -371,6 +371,7 @@ enum aarch64_opnd
AARCH64_OPND_BARRIER_DSB_NXS, /* Barrier operand for DSB nXS variant. */
AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
AARCH64_OPND_PRFOP, /* Prefetch operation. */
AARCH64_OPND_RPRFMOP, /* Range prefetch operation. */
AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
AARCH64_OPND_BTI_TARGET, /* BTI {<target>}. */
AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */
@ -1600,6 +1601,7 @@ aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
extern const char *const aarch64_sve_pattern_array[32];
extern const char *const aarch64_sve_prfop_array[16];
extern const char *const aarch64_rprfmop_array[64];
extern const char *const aarch64_sme_vlxn_array[2];
#ifdef __cplusplus

137
opcodes/aarch64-asm-2.c
View File

@ -642,7 +642,6 @@ aarch64_insert_operand (const aarch64_operand *self,
case 29:
case 30:
case 31:
case 167:
case 168:
case 169:
case 170:
@ -656,7 +655,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 178:
case 179:
case 180:
case 195:
case 181:
case 196:
case 197:
case 198:
@ -665,15 +664,16 @@ aarch64_insert_operand (const aarch64_operand *self,
case 201:
case 202:
case 203:
case 210:
case 213:
case 217:
case 224:
case 204:
case 211:
case 214:
case 218:
case 225:
case 232:
case 226:
case 233:
case 234:
case 235:
case 236:
return aarch64_ins_regno (self, info, code, inst, errors);
case 15:
return aarch64_ins_reg_extended (self, info, code, inst, errors);
@ -685,7 +685,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 33:
case 34:
case 35:
case 271:
case 272:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 36:
return aarch64_ins_reglist (self, info, code, inst, errors);
@ -720,9 +720,9 @@ aarch64_insert_operand (const aarch64_operand *self,
case 82:
case 83:
case 84:
case 164:
case 166:
case 187:
case 108:
case 165:
case 167:
case 188:
case 189:
case 190:
@ -730,13 +730,14 @@ aarch64_insert_operand (const aarch64_operand *self,
case 192:
case 193:
case 194:
case 238:
case 265:
case 195:
case 239:
case 266:
case 268:
case 270:
case 275:
case 267:
case 269:
case 271:
case 276:
case 277:
return aarch64_ins_imm (self, info, code, inst, errors);
case 44:
case 45:
@ -746,10 +747,10 @@ aarch64_insert_operand (const aarch64_operand *self,
case 48:
return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors);
case 52:
case 154:
case 155:
return aarch64_ins_fpimm (self, info, code, inst, errors);
case 70:
case 162:
case 163:
return aarch64_ins_limm (self, info, code, inst, errors);
case 71:
return aarch64_ins_aimm (self, info, code, inst, errors);
@ -759,11 +760,11 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_fbits (self, info, code, inst, errors);
case 75:
case 76:
case 159:
case 160:
return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
case 77:
case 158:
case 160:
case 159:
case 161:
return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
case 78:
case 79:
@ -804,30 +805,29 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_barrier_dsb_nxs (self, info, code, inst, errors);
case 107:
return aarch64_ins_prfop (self, info, code, inst, errors);
case 108:
case 267:
case 269:
return aarch64_ins_none (self, info, code, inst, errors);
case 109:
return aarch64_ins_hint (self, info, code, inst, errors);
case 268:
case 270:
return aarch64_ins_none (self, info, code, inst, errors);
case 110:
return aarch64_ins_hint (self, info, code, inst, errors);
case 111:
return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
case 112:
return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
case 113:
case 114:
case 115:
return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
case 116:
return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
case 117:
return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
case 118:
return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
case 119:
case 120:
case 121:
return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
case 122:
return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
case 123:
case 124:
case 125:
@ -842,8 +842,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 134:
case 135:
case 136:
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
case 137:
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
case 138:
case 139:
case 140:
@ -851,77 +851,77 @@ aarch64_insert_operand (const aarch64_operand *self,
case 142:
case 143:
case 144:
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
case 145:
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
case 146:
case 147:
case 148:
return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
case 149:
return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
case 150:
return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
case 151:
return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
case 152:
return aarch64_ins_sve_aimm (self, info, code, inst, errors);
return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
case 153:
return aarch64_ins_sve_aimm (self, info, code, inst, errors);
case 154:
return aarch64_ins_sve_asimm (self, info, code, inst, errors);
case 155:
return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
case 156:
return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
case 157:
return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
case 158:
return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors);
case 161:
case 162:
return aarch64_ins_inv_limm (self, info, code, inst, errors);
case 163:
case 164:
return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
case 165:
case 166:
return aarch64_ins_sve_scale (self, info, code, inst, errors);
case 181:
case 182:
case 183:
return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
case 184:
return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
case 185:
case 186:
case 251:
case 187:
case 252:
return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
case 204:
case 205:
case 206:
case 207:
case 208:
case 209:
case 210:
return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
case 211:
return aarch64_ins_sve_index (self, info, code, inst, errors);
case 212:
case 214:
case 231:
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
return aarch64_ins_sve_index (self, info, code, inst, errors);
case 213:
case 215:
case 232:
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
case 216:
case 218:
case 217:
case 219:
case 220:
case 221:
case 230:
return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
case 222:
case 231:
return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
case 223:
case 224:
return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors);
case 226:
case 228:
case 239:
return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
case 227:
case 229:
case 240:
return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
case 228:
case 230:
return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
case 236:
case 237:
case 252:
case 238:
case 253:
case 254:
case 255:
@ -934,26 +934,27 @@ aarch64_insert_operand (const aarch64_operand *self,
case 262:
case 263:
case 264:
case 265:
return aarch64_ins_simple_index (self, info, code, inst, errors);
case 240:
case 241:
case 242:
case 243:
case 244:
case 245:
case 246:
return aarch64_ins_sme_za_array (self, info, code, inst, errors);
case 247:
return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
return aarch64_ins_sme_za_array (self, info, code, inst, errors);
case 248:
return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
case 249:
return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
case 250:
return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
case 251:
return aarch64_ins_plain_shrimm (self, info, code, inst, errors);
case 272:
case 273:
case 274:
case 275:
return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
default: assert (0); abort ();
}

1637
opcodes/aarch64-dis-2.c
View File

File diff suppressed because it is too large Load Diff

1
opcodes/aarch64-opc-2.c
View File

@ -132,6 +132,7 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_SYSTEM, "BARRIER_DSB_NXS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the DSB nXS option qualifier name SY, ISH, NSH, OSH or an optional 5-bit unsigned immediate"},
{AARCH64_OPND_CLASS_SYSTEM, "BARRIER_ISB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the ISB option name SY or an optional 4-bit unsigned immediate"},
{AARCH64_OPND_CLASS_SYSTEM, "PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a prefetch operation specifier"},
{AARCH64_OPND_CLASS_SYSTEM, "RPRFMOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm1_15, FLD_imm2_12, FLD_imm3_0}, "a range prefetch operation specifier"},
{AARCH64_OPND_CLASS_SYSTEM, "BARRIER_PSB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the PSB/TSB option name CSYNC"},
{AARCH64_OPND_CLASS_SYSTEM, "BTI", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "BTI targets j/c/jc"},
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x16", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 16"},

23
opcodes/aarch64-opc.c
View File

@ -99,6 +99,17 @@ const char *const aarch64_sve_prfop_array[16] = {
0
};
/* The enumeration strings associated with each value of a 6-bit RPRFM
operation. */
const char *const aarch64_rprfmop_array[64] = {
"pldkeep",
"pstkeep",
0,
0,
"pldstrm",
"pststrm"
};
/* Vector length multiples for a predicate-as-counter operand. Used in things
like AARCH64_OPND_SME_VLxN_10. */
const char *const aarch64_sme_vlxn_array[2] = {
@ -330,6 +341,7 @@ const aarch64_field fields[] =
{ 1, 2 }, /* imm2_1: general immediate in bits [2:1]. */
{ 8, 2 }, /* imm2_8: general immediate in bits [9:8]. */
{ 10, 2 }, /* imm2_10: 2-bit immediate, bits [11:10] */
{ 12, 2 }, /* imm2_12: 2-bit immediate, bits [13:12] */
{ 15, 2 }, /* imm2_15: 2-bit immediate, bits [16:15] */
{ 16, 2 }, /* imm2_16: 2-bit immediate, bits [17:16] */
{ 19, 2 }, /* imm2_19: 2-bit immediate, bits [20:19] */
@ -4584,6 +4596,17 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
opnd->prfop->value));
break;
case AARCH64_OPND_RPRFMOP:
enum_value = opnd->imm.value;
if (enum_value < ARRAY_SIZE (aarch64_rprfmop_array)
&& aarch64_rprfmop_array[enum_value])
snprintf (buf, size, "%s",
style_reg (styler, aarch64_rprfmop_array[enum_value]));
else
snprintf (buf, size, "%s",
style_imm (styler, "#%" PRIi64, opnd->imm.value));
break;
case AARCH64_OPND_BARRIER_PSB:
snprintf (buf, size, "%s", style_sub_mnem (styler, "csync"));
break;

1
opcodes/aarch64-opc.h
View File

@ -151,6 +151,7 @@ enum aarch64_field_kind
FLD_imm2_1,
FLD_imm2_8,
FLD_imm2_10,
FLD_imm2_12,
FLD_imm2_15,
FLD_imm2_16,
FLD_imm2_19,

11
opcodes/aarch64-tbl.h
View File

@ -1779,6 +1779,10 @@
{ \
QLF2(NIL,X), \
}
#define OP_SVE_UXU \
{ \
QLF3(NIL,X,NIL), \
}
#define OP_SVE_VMR_BHSD \
{ \
QLF3(S_B,P_M,W), \
@ -5359,6 +5363,10 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME_INSN ("psel", 0x25204000, 0xff20c210, sme_psel, 0, OP3 (SVE_Pd, SVE_Pg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0),
SME_INSN ("psel", 0x25204000, 0xff20c210, sme_psel, 0, OP3 (SVE_PNd, SVE_PNg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0),
/* Added in SME2, but part of the prefetch hint space and available
without special command-line flags. */
CORE_INSN ("rprfm", 0xf8a04818, 0xffe04c18, sme_misc, 0, OP3 (RPRFMOP, Rm, SIMD_ADDR_SIMPLE), OP_SVE_UXU, 0),
/* SME2 extensions to SVE2. */
SME2_INSNC ("bfmlslb", 0x64e06000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
SME2_INSNC ("bfmlslb", 0x64e0a000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
@ -6269,6 +6277,9 @@ const struct aarch64_opcode aarch64_opcode_table[] =
"the ISB option name SY or an optional 4-bit unsigned immediate") \
Y(SYSTEM, prfop, "PRFOP", 0, F(), \
"a prefetch operation specifier") \
Y(SYSTEM, imm, "RPRFMOP", 0, \
F(FLD_imm1_15, FLD_imm2_12, FLD_imm3_0), \
"a range prefetch operation specifier") \
Y(SYSTEM, none, "BARRIER_PSB", 0, F (), \
"the PSB/TSB option name CSYNC") \
Y(SYSTEM, hint, "BTI", 0, F (), \