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https://sourceware.org/git/binutils-gdb.git
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Add MIPS32 DSPr3 support.
bfd/ * elfxx-mips.c (print_mips_ases): Add DSPR3. binutils/ * readelf.c (print_mips_ases): Add DSPR3. gas/ * config/tc-mips.c (options): Add OPTION_DSPR3 and OPTION_NO_DSPR3. (md_longopts): Likewise. (md_show_usage): Add help for -mdspr3 and -mno-dspr3. (mips_ases): Define availability for DSPr3. (mips_ase_groups): Add ASE_DSPR3 to the DSP group. (mips_convert_ase_flags): Map ASE_DSPR3 to AFL_ASE_DSPR3. * doc/as.texinfo: Document -mdspr3, -mno-dspr3. Fix -mdspr2 formatting. * doc/c-mips.texi: Document -mdspr3, -mno-dspr3, .set dspr3 and .set nodspr3. Fix -mdspr2 formatting. * testsuite/gas/mips/mips32-dspr3.d: New file. * testsuite/gas/mips/mips32-dspr3.s: Likewise. * testsuite/gas/mips/mips.exp: Run mips32-dspr3 test. include/ * elf/mips.h (AFL_ASE_DSPR3): New macro. (AFL_ASE_MASK): Update to include AFL_ASE_DSPR3. * opcode/mips.h (ASE_DSPR3): New macro. opcodes/ * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and mips64r6. * mips-opc.c (D34): New macro. (mips_builtin_opcodes): Define bposge32c for DSPr3.
This commit is contained in:
Matthew Fortune
parent
a464198b01
commit
8f4f9071ad
@ -1,3 +1,7 @@
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2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
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* elfxx-mips.c (print_mips_ases): Add DSPR3.
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2016-05-11 Alan Modra <amodra@gmail.com>
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* elf32-hppa.c (elf32_hppa_init_stub_bfd): New function.
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@ -15565,6 +15565,8 @@ print_mips_ases (FILE *file, unsigned int mask)
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fputs ("\n\tDSP ASE", file);
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if (mask & AFL_ASE_DSPR2)
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fputs ("\n\tDSP R2 ASE", file);
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if (mask & AFL_ASE_DSPR3)
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fputs ("\n\tDSP R3 ASE", file);
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if (mask & AFL_ASE_EVA)
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fputs ("\n\tEnhanced VA Scheme", file);
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if (mask & AFL_ASE_MCU)
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@ -1,3 +1,7 @@
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2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
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* readelf.c (print_mips_ases): Add DSPR3.
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2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
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* readelf.c (display_arm_attribute): Add output for Tag_DSP_extension.
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@ -14229,6 +14229,8 @@ print_mips_ases (unsigned int mask)
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fputs ("\n\tDSP ASE", stdout);
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if (mask & AFL_ASE_DSPR2)
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fputs ("\n\tDSP R2 ASE", stdout);
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if (mask & AFL_ASE_DSPR3)
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fputs ("\n\tDSP R3 ASE", stdout);
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if (mask & AFL_ASE_EVA)
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fputs ("\n\tEnhanced VA Scheme", stdout);
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if (mask & AFL_ASE_MCU)
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@ -1,3 +1,21 @@
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2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
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Matthew Fortune <matthew.fortune@imgtec.com>
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* config/tc-mips.c (options): Add OPTION_DSPR3 and
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OPTION_NO_DSPR3.
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(md_longopts): Likewise.
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(md_show_usage): Add help for -mdspr3 and -mno-dspr3.
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(mips_ases): Define availability for DSPr3.
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(mips_ase_groups): Add ASE_DSPR3 to the DSP group.
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(mips_convert_ase_flags): Map ASE_DSPR3 to AFL_ASE_DSPR3.
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* doc/as.texinfo: Document -mdspr3, -mno-dspr3. Fix -mdspr2
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formatting.
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* doc/c-mips.texi: Document -mdspr3, -mno-dspr3, .set dspr3 and
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.set nodspr3. Fix -mdspr2 formatting.
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* testsuite/gas/mips/mips32-dspr3.d: New file.
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* testsuite/gas/mips/mips32-dspr3.s: Likewise.
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* testsuite/gas/mips/mips.exp: Run mips32-dspr3 test.
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2016-05-11 Nick Clifton <nickc@redhat.com>
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PR target/20068
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@ -1410,6 +1410,8 @@ enum options
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OPTION_NO_SMARTMIPS,
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OPTION_DSPR2,
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OPTION_NO_DSPR2,
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OPTION_DSPR3,
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OPTION_NO_DSPR3,
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OPTION_EVA,
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OPTION_NO_EVA,
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OPTION_XPA,
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@ -1522,6 +1524,8 @@ struct option md_longopts[] =
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{"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
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{"mdspr2", no_argument, NULL, OPTION_DSPR2},
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{"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
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{"mdspr3", no_argument, NULL, OPTION_DSPR3},
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{"mno-dspr3", no_argument, NULL, OPTION_NO_DSPR3},
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{"meva", no_argument, NULL, OPTION_EVA},
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{"mno-eva", no_argument, NULL, OPTION_NO_EVA},
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{"mmicromips", no_argument, NULL, OPTION_MICROMIPS},
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@ -1663,6 +1667,11 @@ static const struct mips_ase mips_ases[] = {
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2, 2, 2, 2,
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-1 },
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{ "dspr3", ASE_DSP | ASE_DSPR2 | ASE_DSPR3, 0,
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OPTION_DSPR3, OPTION_NO_DSPR3,
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6, 6, -1, -1,
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-1 },
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{ "eva", ASE_EVA, 0,
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OPTION_EVA, OPTION_NO_EVA,
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2, 2, 2, 2,
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@ -1716,7 +1725,7 @@ static const struct mips_ase mips_ases[] = {
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/* Groups of ASE_* flags that represent different revisions of an ASE. */
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static const unsigned int mips_ase_groups[] = {
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ASE_DSP | ASE_DSPR2
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ASE_DSP | ASE_DSPR2 | ASE_DSPR3
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};
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/* Pseudo-op table.
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@ -17954,6 +17963,8 @@ mips_convert_ase_flags (int ase)
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ext_ases |= AFL_ASE_DSP;
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if (ase & ASE_DSPR2)
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ext_ases |= AFL_ASE_DSPR2;
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if (ase & ASE_DSPR3)
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ext_ases |= AFL_ASE_DSPR3;
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if (ase & ASE_EVA)
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ext_ases |= AFL_ASE_EVA;
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if (ase & ASE_MCU)
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@ -18963,6 +18974,9 @@ MIPS options:\n\
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-mdspr2 generate DSP R2 instructions\n\
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-mno-dspr2 do not generate DSP R2 instructions\n"));
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fprintf (stream, _("\
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-mdspr3 generate DSP R3 instructions\n\
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-mno-dspr3 do not generate DSP R3 instructions\n"));
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fprintf (stream, _("\
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-mmt generate MT instructions\n\
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-mno-mt do not generate MT instructions\n"));
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fprintf (stream, _("\
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@ -424,6 +424,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
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[@b{-mdmx}] [@b{-no-mdmx}]
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[@b{-mdsp}] [@b{-mno-dsp}]
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[@b{-mdspr2}] [@b{-mno-dspr2}]
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[@b{-mdspr3}] [@b{-mno-dspr3}]
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[@b{-mmsa}] [@b{-mno-msa}]
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[@b{-mxpa}] [@b{-mno-xpa}]
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[@b{-mmt}] [@b{-mno-mt}]
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@ -1438,10 +1439,17 @@ This tells the assembler to accept DSP Release 1 instructions.
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@item -mdspr2
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@itemx -mno-dspr2
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Generate code for the DSP Release 2 Application Specific Extension.
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This option implies -mdsp.
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This option implies @samp{-mdsp}.
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This tells the assembler to accept DSP Release 2 instructions.
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@samp{-mno-dspr2} turns off this option.
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@item -mdspr3
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@itemx -mno-dspr3
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Generate code for the DSP Release 3 Application Specific Extension.
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This option implies @samp{-mdsp} and @samp{-mdspr2}.
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This tells the assembler to accept DSP Release 3 instructions.
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@samp{-mno-dspr3} turns off this option.
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@item -mmsa
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@itemx -mno-msa
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Generate code for the MIPS SIMD Architecture Extension.
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@ -187,10 +187,17 @@ This tells the assembler to accept DSP Release 1 instructions.
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@item -mdspr2
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@itemx -mno-dspr2
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Generate code for the DSP Release 2 Application Specific Extension.
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This option implies -mdsp.
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This option implies @samp{-mdsp}.
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This tells the assembler to accept DSP Release 2 instructions.
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@samp{-mno-dspr2} turns off this option.
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@item -mdspr3
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@itemx -mno-dspr3
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Generate code for the DSP Release 3 Application Specific Extension.
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This option implies @samp{-mdsp} and @samp{-mdspr2}.
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This tells the assembler to accept DSP Release 3 instructions.
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@samp{-mno-dspr3} turns off this option.
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@item -mmt
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@itemx -mno-mt
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Generate code for the MT Application Specific Extension.
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@ -1007,6 +1014,15 @@ on in the assembly. This directive implies @code{.set dsp}. The
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@code{.set nodspr2} directive prevents DSP Release 2 instructions from
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being accepted.
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@cindex MIPS DSP Release 3 instruction generation override
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@kindex @code{.set dspr3}
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@kindex @code{.set nodspr3}
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The directive @code{.set dspr3} makes the assembler accept instructions
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from the DSP Release 3 Application Specific Extension from that point
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on in the assembly. This directive implies @code{.set dsp} and
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@code{.set dspr2}. The @code{.set nodspr3} directive prevents DSP
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Release 3 instructions from being accepted.
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@cindex MIPS MT instruction generation override
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@kindex @code{.set mt}
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@kindex @code{.set nomt}
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@ -1153,6 +1153,7 @@ if { [istarget mips*-*-vxworks*] } {
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!octeon]
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run_dump_test_arches "mips32-dspr2" [mips_arch_list_matching mips32r2 \
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!octeon]
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run_dump_test_arches "mips32-dspr3" [mips_arch_list_matching mips32r6]
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run_dump_test "mips64-dsp"
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run_dump_test "mips32-mt"
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22
gas/testsuite/gas/mips/mips32-dspr3.d
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22
gas/testsuite/gas/mips/mips32-dspr3.d
Normal file
@ -0,0 +1,22 @@
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#objdump: -pdr --prefix-addresses --show-raw-insn
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#name: MIPS DSP ASE Rev3 for MIPS32
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#as: -mdspr3 -32
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# Check MIPS DSP ASE Rev3 for MIPS32 Instruction Assembly
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.*: +file format .*mips.*
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#...
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ASEs:
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#...
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DSP ASE
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DSP R2 ASE
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DSP R3 ASE
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#...
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FLAGS 1: .*
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FLAGS 2: .*
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Disassembly of section .text:
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0+0000 <[^>]*> 0418ffff bposge32c 00000000 <text_label>
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.*0: R_MIPS_PC16 text_label
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\.\.\.
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12
gas/testsuite/gas/mips/mips32-dspr3.s
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12
gas/testsuite/gas/mips/mips32-dspr3.s
Normal file
@ -0,0 +1,12 @@
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# source file to test assembly of MIPS DSP ASE Rev3 for MIPS32 instructions
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.set noreorder
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.set noat
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.text
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text_label:
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bposge32c text_label
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# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
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.align 2
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.space 8
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@ -1,3 +1,9 @@
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2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
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* elf/mips.h (AFL_ASE_DSPR3): New macro.
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(AFL_ASE_MASK): Update to include AFL_ASE_DSPR3.
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* opcode/mips.h (ASE_DSPR3): New macro.
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2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
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Nick Clifton <nickc@redhat.com>
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@ -1227,7 +1227,8 @@ extern void bfd_mips_elf_swap_abiflags_v0_out
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#define AFL_ASE_MIPS16 0x00000400 /* MIPS16 ASE. */
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#define AFL_ASE_MICROMIPS 0x00000800 /* MICROMIPS ASE. */
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#define AFL_ASE_XPA 0x00001000 /* XPA ASE. */
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#define AFL_ASE_MASK 0x00001fff /* All ASEs. */
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#define AFL_ASE_DSPR3 0x00002000 /* DSP R3 ASE. */
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#define AFL_ASE_MASK 0x00003fff /* All ASEs. */
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/* Values for the isa_ext word of an ABI flags structure. */
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@ -1256,6 +1256,7 @@ static const unsigned int mips_isa_table[] = {
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#define ASE_MSA64 0x00001000
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/* eXtended Physical Address (XPA) Extension. */
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#define ASE_XPA 0x00002000
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#define ASE_DSPR3 0x00004000
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/* MIPS ISA defines, use instead of hardcoding ISA level. */
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@ -1,3 +1,10 @@
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2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
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* mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
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mips64r6.
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* mips-opc.c (D34): New macro.
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(mips_builtin_opcodes): Define bposge32c for DSPr3.
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2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
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* i386-dis.c (prefix_table): Add RDPID instruction.
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@ -563,7 +563,7 @@ const struct mips_arch_choice mips_arch_choices[] =
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{ "mips32r6", 1, bfd_mach_mipsisa32r6, CPU_MIPS32R6,
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ISA_MIPS32R6,
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(ASE_EVA | ASE_MSA | ASE_VIRT | ASE_XPA | ASE_MCU | ASE_MT | ASE_DSP
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| ASE_DSPR2),
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| ASE_DSPR2 | ASE_DSPR3),
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mips_cp0_names_mips3264r2,
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mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
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mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
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@ -602,7 +602,7 @@ const struct mips_arch_choice mips_arch_choices[] =
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{ "mips64r6", 1, bfd_mach_mipsisa64r6, CPU_MIPS64R6,
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ISA_MIPS64R6,
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(ASE_EVA | ASE_MSA | ASE_MSA64 | ASE_XPA | ASE_VIRT | ASE_VIRT64
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| ASE_MCU | ASE_MT | ASE_DSP | ASE_DSPR2),
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| ASE_MCU | ASE_MT | ASE_DSP | ASE_DSPR2 | ASE_DSPR3),
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mips_cp0_names_mips3264r2,
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mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
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mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
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@ -374,6 +374,7 @@ decode_mips_operand (const char *p)
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#define DSP_VOLA INSN_NO_DELAY_SLOT
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#define D32 ASE_DSP
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#define D33 ASE_DSPR2
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#define D34 ASE_DSPR3
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#define D64 ASE_DSP64
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/* MIPS MT ASE support. */
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@ -2149,6 +2150,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"addwc", "d,s,t", 0x7c000450, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 },
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{"bitrev", "d,t", 0x7c0006d2, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 },
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{"bposge32", "p", 0x041c0000, 0xffff0000, CBD, 0, 0, D32, 0 },
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{"bposge32c", "p", 0x04180000, 0xffff0000, NODS, FS, 0, D34, 0 },
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{"bposge64", "p", 0x041d0000, 0xffff0000, CBD, 0, 0, D64, 0 },
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{"cmp.eq.ph", "s,t", 0x7c000211, 0xfc00ffff, RD_1|RD_2, 0, 0, D32, 0 },
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{"cmp.eq.pw", "s,t", 0x7c000415, 0xfc00ffff, RD_1|RD_2, 0, 0, D64, 0 },
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