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* config/tc-m68k.c (m68k_ip): The coldfire does not support 8x
scale factor.
This commit is contained in:
J.T. Conklin
parent
0d65f03d6e
commit
8d20a0a883
@ -1,3 +1,8 @@
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Fri Jul 5 10:32:58 1996 J.T. Conklin <jtc@rtl.cygnus.com>
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* config/tc-m68k.c (m68k_ip): The coldfire does not support 8x
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scale factor.
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Fri Jul 5 11:07:24 1996 Ian Lance Taylor <ian@cygnus.com>
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* symbols.c (S_SET_EXTERNAL): Change as_warn to as_bad.
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@ -26,12 +26,14 @@
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#include "opcode/m68k.h"
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#include "m68k-parse.h"
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/* This array holds the chars that always start a comment. If the
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pre-processor is disabled, these aren't very useful */
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/* This string holds the chars that always start a comment. If the
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pre-processor is disabled, these aren't very useful. The macro
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tc_comment_chars points to this. We use this, rather than the
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usual comment_chars, so that the --bitwise-or option will work. */
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#if (defined (OBJ_ELF) && ! defined (TE_PSOS) && ! defined (TE_LINUX)) || defined (TE_DELTA)
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const char comment_chars[] = "|#";
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const char *m68k_comment_chars = "|#";
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#else
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const char comment_chars[] = "|";
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const char *m68k_comment_chars = "|";
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#endif
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/* This array holds the chars that only start a comment at the beginning of
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@ -158,6 +160,11 @@ static const enum m68k_register m68060_control_regs[] = {
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USP, VBR, URP, SRP, PCR,
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0
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};
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static const enum m68k_register mcf5200_control_regs[] = {
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CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
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RAMBAR0, RAMBAR1, MBAR,
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0
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};
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#define cpu32_control_regs m68010_control_regs
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static const enum m68k_register *control_regs;
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@ -211,7 +218,7 @@ struct m68k_it
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reloc[5]; /* Five is enough??? */
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};
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#define cpu_of_arch(x) ((x) & m68000up)
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#define cpu_of_arch(x) ((x) & (m68000up|mcf5200))
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#define float_of_arch(x) ((x) & mfloat)
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#define mmu_of_arch(x) ((x) & mmmu)
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@ -339,6 +346,7 @@ static const struct m68k_cpu archs[] = {
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{ cpu32, "cpu32", 0 },
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{ m68881, "68881", 0 },
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{ m68851, "68851", 0 },
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{ mcf5200, "5200", 0 },
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/* Aliases (effectively, so far as gas is concerned) for the above
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cpus. */
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{ m68020, "68k", 1 },
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@ -350,6 +358,7 @@ static const struct m68k_cpu archs[] = {
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{ m68020, "68ec020", 1 },
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{ m68030, "68ec030", 1 },
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{ m68040, "68ec040", 1 },
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{ m68060, "68ec060", 1 },
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{ cpu32, "68330", 1 },
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{ cpu32, "68331", 1 },
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{ cpu32, "68332", 1 },
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@ -1331,7 +1340,9 @@ m68k_ip (instring)
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break;
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case 'O':
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if (opP->mode != DREG && opP->mode != IMMED)
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if (opP->mode != DREG
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&& opP->mode != IMMED
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&& opP->mode != ABSL)
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losing++;
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break;
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@ -1848,13 +1859,13 @@ m68k_ip (instring)
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|| opP->index.size == SIZE_LONG)
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nextword |= 0x800;
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if (cpu_of_arch (current_architecture) < m68020)
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if ((opP->index.scale != 1
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&& cpu_of_arch (current_architecture) < m68020)
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|| (opP->index.scale == 8
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&& current_architecture == mcf5200))
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{
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if (opP->index.scale != 1)
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{
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opP->error =
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"scale factor invalid on this architecture; needs 68020 or higher";
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}
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opP->error =
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"scale factor invalid on this architecture; needs cpu32 or 68020 or higher";
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}
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switch (opP->index.scale)
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@ -1986,6 +1997,8 @@ m68k_ip (instring)
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/* Figure out innner displacement stuff */
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if (opP->mode == POST || opP->mode == PRE)
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{
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if (cpu_of_arch (current_architecture) & cpu32)
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opP->error = "invalid operand mode for this architecture; needs 68020 or higher";
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switch (siz2)
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{
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case SIZE_UNSPEC:
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@ -2359,6 +2372,18 @@ m68k_ip (instring)
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case PCR:
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tmpreg = 0x808;
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break;
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case ROMBAR:
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tmpreg = 0xC00;
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break;
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case RAMBAR0:
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tmpreg = 0xC04;
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break;
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case RAMBAR1:
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tmpreg = 0xC05;
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break;
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case MBAR:
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tmpreg = 0xC0F;
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break;
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default:
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abort ();
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}
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@ -2940,29 +2965,52 @@ static const struct init_entry init_table[] =
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{ "ccr", CCR },
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{ "cc", CCR },
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{ "usp", USP },
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{ "isp", ISP },
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{ "sfc", SFC },
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/* control registers */
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{ "sfc", SFC }, /* Source Function Code */
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{ "sfcr", SFC },
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{ "dfc", DFC },
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{ "dfc", DFC }, /* Destination Function Code */
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{ "dfcr", DFC },
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{ "cacr", CACR },
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{ "caar", CAAR },
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{ "cacr", CACR }, /* Cache Control Register */
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{ "caar", CAAR }, /* Cache Address Register */
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{ "vbr", VBR },
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{ "usp", USP }, /* User Stack Pointer */
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{ "vbr", VBR }, /* Vector Base Register */
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{ "msp", MSP }, /* Master Stack Pointer */
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{ "isp", ISP }, /* Interrupt Stack Pointer */
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{ "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
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{ "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
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{ "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
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{ "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
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/* 68ec040 versions of same */
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{ "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
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{ "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
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{ "dacr0", DTT0 }, /* Data Access Control Register 0 */
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{ "dacr1", DTT1 }, /* Data Access Control Register 0 */
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/* mcf5200 versions of same */
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{ "acr2", ITT0 }, /* Access Control Unit 2 */
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{ "acr3", ITT1 }, /* Access Control Unit 3 */
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{ "acr0", DTT0 }, /* Access Control Unit 0 */
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{ "acr1", DTT1 }, /* Access Control Unit 1 */
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{ "tc", TC }, /* MMU Translation Control Register */
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{ "tcr", TC },
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{ "mmusr", MMUSR }, /* MMU Status Register */
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{ "srp", SRP }, /* User Root Pointer */
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{ "urp", URP }, /* Supervisor Root Pointer */
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{ "msp", MSP },
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{ "itt0", ITT0 },
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{ "itt1", ITT1 },
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{ "dtt0", DTT0 },
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{ "dtt1", DTT1 },
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{ "mmusr", MMUSR },
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{ "tc", TC },
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{ "srp", SRP },
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{ "urp", URP },
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{ "buscr", BUSCR },
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{ "pcr", PCR },
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{ "rombar", ROMBAR }, /* ROM Base Address Register */
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{ "rambar0", RAMBAR0 }, /* ROM Base Address Register */
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{ "rambar1", RAMBAR1 }, /* ROM Base Address Register */
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{ "mbar", MBAR }, /* Module Base Address Register */
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/* end of control registers */
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{ "ac", AC },
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{ "bc", BC },
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{ "cal", CAL },
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@ -3375,6 +3423,20 @@ md_begin ()
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*/
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alt_notend_table['@'] = 1;
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/* We need to put digits in alt_notend_table to handle
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bfextu %d0{24:1},%d0
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*/
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alt_notend_table['0'] = 1;
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alt_notend_table['1'] = 1;
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alt_notend_table['2'] = 1;
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alt_notend_table['3'] = 1;
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alt_notend_table['4'] = 1;
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alt_notend_table['5'] = 1;
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alt_notend_table['6'] = 1;
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alt_notend_table['7'] = 1;
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alt_notend_table['8'] = 1;
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alt_notend_table['9'] = 1;
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#ifndef MIT_SYNTAX_ONLY
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/* Insert pseudo ops, these have to go into the opcode table since
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gas expects pseudo ops to start with a dot */
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@ -3487,6 +3549,9 @@ m68k_init_after_args ()
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case cpu32:
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control_regs = cpu32_control_regs;
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break;
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case mcf5200:
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control_regs = mcf5200_control_regs;
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break;
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default:
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abort ();
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}
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@ -6129,6 +6194,9 @@ s_mri_endw (ignore)
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* -pic Indicates PIC.
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* -k Indicates PIC. (Sun 3 only.)
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*
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* --bitwise-or
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* Permit `|' to be used in expressions.
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*
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*/
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#ifdef OBJ_ELF
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@ -6143,6 +6211,8 @@ struct option md_longopts[] = {
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#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
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{"register-prefix-optional", no_argument, NULL,
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OPTION_REGISTER_PREFIX_OPTIONAL},
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#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
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{"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
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{NULL, no_argument, NULL, 0}
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};
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size_t md_longopts_size = sizeof(md_longopts);
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@ -6260,6 +6330,21 @@ md_parse_option (c, arg)
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case 'Q':
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break;
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case OPTION_BITWISE_OR:
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{
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char *n, *t;
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const char *s;
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n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
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t = n;
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for (s = m68k_comment_chars; *s != '\0'; s++)
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if (*s != '|')
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*t++ = *s;
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*t = '\0';
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m68k_comment_chars = n;
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}
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break;
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default:
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return 0;
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}
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@ -6276,7 +6361,7 @@ md_show_usage (stream)
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-l use 1 word for refs to undefined symbols [default 2]\n\
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-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
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| -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
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| -mcpu32\n\
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| -mcpu32 | -mcf5200\n\
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specify variant of 680X0 architecture [default 68020]\n\
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-m68881 | -m68882 | -mno-68881 | -mno-68882\n\
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target has/lacks floating-point coprocessor\n\
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@ -6288,7 +6373,8 @@ md_show_usage (stream)
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-pic, -k generate position independent code\n\
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-S turn jbsr into jsr\n\
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--register-prefix-optional\n\
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recognize register names without prefix character\n");
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recognize register names without prefix character\n\
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--bitwise-or do not treat `|' as a comment character\n");
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}
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#ifdef TEST2
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