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gas/
2003-03-21 H.J. Lu <hongjiu.lu@intel.com> PR binutils/4218 * config/tc-i386.c (match_template): Properly handle 64bit mode "xchg %eax, %eax". gas/testsuite/ 2003-03-21 H.J. Lu <hongjiu.lu@intel.com> PR binutils/4218 * gas/i386/nops.s: Add testcases for nop r/m. * gas/i386/x86-64-nops.s: Likewise. * gas/i386/x86-64-opcode.s: Add testcases for xchg with %ax, %eax and %rax. * gas/i386/nops.d: Updated. * gas/i386/x86-64-nops.d: Likewise. * gas/i386/x86-64-opcode.d: Likewise. opcodes/ 2003-03-21 H.J. Lu <hongjiu.lu@intel.com> PR binutils/4218 * i386-dis.c (PREGRP38): New. (dis386): Use PREGRP38 for 0x90. (prefix_user_table): Add PREGRP38. (print_insn): Set uses_REPZ_prefix to 1 for pause. (NOP_Fixup1): Properly handle REX bits. (NOP_Fixup2): Likewise. * i386-opc.c (i386_optab): Allow %eax with xchg in 64bit. Allow register with nop.
This commit is contained in:
H.J. Lu
parent
ffa8bd48e3
commit
8b38ad713b
@ -1,3 +1,9 @@
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2003-03-21 H.J. Lu <hongjiu.lu@intel.com>
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PR binutils/4218
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* config/tc-i386.c (match_template): Properly handle 64bit mode
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"xchg %eax, %eax".
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2007-03-21 Anton Ertl <anton@mips.complang.tuw>
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PR gas/4124
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@ -2621,6 +2621,15 @@ match_template (void)
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continue;
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break;
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case 2:
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/* xchg %eax, %eax is a special case. It is an aliase for nop
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only in 32bit mode and we can use opcode 0x90. In 64bit
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mode, we can't use 0x90 for xchg %eax, %eax since it should
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zero-extend %eax to %rax. */
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if (flag_code == CODE_64BIT
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&& t->base_opcode == 0x90
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&& i.types [0] == (Acc | Reg32)
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&& i.types [1] == (Acc | Reg32))
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continue;
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case 3:
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case 4:
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overlap1 = i.types[1] & operand_types[1];
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@ -1,3 +1,16 @@
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2003-03-21 H.J. Lu <hongjiu.lu@intel.com>
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PR binutils/4218
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* gas/i386/nops.s: Add testcases for nop r/m.
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* gas/i386/x86-64-nops.s: Likewise.
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* gas/i386/x86-64-opcode.s: Add testcases for xchg with %ax,
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%eax and %rax.
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* gas/i386/nops.d: Updated.
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* gas/i386/x86-64-nops.d: Likewise.
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* gas/i386/x86-64-opcode.d: Likewise.
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2003-03-21 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/i386.exp: Run nops-3.
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@ -14,4 +14,11 @@ Disassembly of section .text:
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[ ]*19:[ ]+0f 1f 84 00 00 00 00 00[ ]+nopl[ ]+0x0\(%eax,%eax,1\)
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[ ]*21:[ ]+66 0f 1f 84 00 00 00 00 00[ ]+nopw[ ]+0x0\(%eax,%eax,1\)
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[ ]*2a:[ ]+66 2e 0f 1f 84 00 00 00 00 00[ ]+nopw[ ]+%cs:0x0\(%eax,%eax,1\)
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[ ]*34:[ ]+0f 1f 00[ ]+nopl[ ]+\(%eax\)
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[ ]*37:[ ]+0f 1f c0[ ]+nop[ ]+%eax
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[ ]*3a:[ ]+66 0f 1f c0[ ]+nop[ ]+%ax
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[ ]*3e:[ ]+0f 1f 00[ ]+nopl[ ]+\(%eax\)
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[ ]*41:[ ]+66 0f 1f 00[ ]+nopw[ ]+\(%eax\)
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[ ]*45:[ ]+0f 1f c0[ ]+nop[ ]+%eax
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[ ]*48:[ ]+66 0f 1f c0[ ]+nop[ ]+%ax
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#pass
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@ -9,4 +9,12 @@
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.byte 0x66, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0
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.byte 0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0
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nop (%eax)
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nop %eax
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nop %ax
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nopl (%eax)
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nopw (%eax)
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nopl %eax
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nopw %ax
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.p2align 4
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@ -14,4 +14,24 @@ Disassembly of section .text:
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[ ]*19:[ ]+0f 1f 84 00 00 00 00 00[ ]+nopl[ ]+0x0\(%rax,%rax,1\)
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[ ]*21:[ ]+66 0f 1f 84 00 00 00 00 00[ ]+nopw[ ]+0x0\(%rax,%rax,1\)
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[ ]*2a:[ ]+66 2e 0f 1f 84 00 00 00 00 00[ ]+nopw[ ]+%cs:0x0\(%rax,%rax,1\)
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[ ]*34:[ ]+0f 1f 00[ ]+nopl[ ]+\(%rax\)
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[ ]*37:[ ]+48 0f 1f c0[ ]+nop[ ]+%rax
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[ ]*3b:[ ]+0f 1f c0[ ]+nop[ ]+%eax
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[ ]*3e:[ ]+66 0f 1f c0[ ]+nop[ ]+%ax
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[ ]*42:[ ]+48 0f 1f 00[ ]+nopq[ ]+\(%rax\)
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[ ]*46:[ ]+0f 1f 00[ ]+nopl[ ]+\(%rax\)
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[ ]*49:[ ]+66 0f 1f 00[ ]+nopw[ ]+\(%rax\)
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[ ]*4d:[ ]+48 0f 1f c0[ ]+nop[ ]+%rax
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[ ]*51:[ ]+0f 1f c0[ ]+nop[ ]+%eax
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[ ]*54:[ ]+66 0f 1f c0[ ]+nop[ ]+%ax
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[ ]*58:[ ]+41 0f 1f 02[ ]+nopl[ ]+\(%r10\)
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[ ]*5c:[ ]+49 0f 1f c2[ ]+nop[ ]+%r10
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[ ]*60:[ ]+41 0f 1f c2[ ]+nop[ ]+%r10d
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[ ]*64:[ ]+66 41 0f 1f c2[ ]+nop[ ]+%r10w
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[ ]*69:[ ]+49 0f 1f 02[ ]+nopq[ ]+\(%r10\)
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[ ]*6d:[ ]+41 0f 1f 02[ ]+nopl[ ]+\(%r10\)
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[ ]*71:[ ]+66 41 0f 1f 02[ ]+nopw[ ]+\(%r10\)
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[ ]*76:[ ]+49 0f 1f c2[ ]+nop[ ]+%r10
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[ ]*7a:[ ]+41 0f 1f c2[ ]+nop[ ]+%r10d
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[ ]*7e:[ ]+66 41 0f 1f c2[ ]+nop[ ]+%r10w
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#pass
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@ -9,4 +9,25 @@
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.byte 0x66, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0
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.byte 0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x0, 0x0, 0x0, 0x0, 0x0
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nop (%rax)
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nop %rax
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nop %eax
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nop %ax
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nopq (%rax)
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nopl (%rax)
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nopw (%rax)
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nopq %rax
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nopl %eax
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nopw %ax
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nop (%r10)
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nop %r10
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nop %r10d
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nop %r10w
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nopq (%r10)
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nopl (%r10)
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nopw (%r10)
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nopq %r10
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nopl %r10d
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nopw %r10w
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.p2align 4
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@ -274,6 +274,16 @@ Disassembly of section .text:
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[ ]*[0-9a-f]+:[ ]+90[ ]+nop[ ]*(#.*)*
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[ ]*[0-9a-f]+:[ ]+48 90[ ]+rex64 nop[ ]*(#.*)*
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[ ]*[0-9a-f]+:[ ]+49 90[ ]+xchg[ ]+%rax,%r8[ ]*(#.*)*
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[ ]*[0-9a-f]+:[ ]+41 90[ ]+xchg[ ]+%eax,%r8d[ ]*(#.*)*
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[ ]*[0-9a-f]+:[ ]+41 90[ ]+xchg[ ]+%eax,%r8d[ ]*(#.*)*
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[ ]*[0-9a-f]+:[ ]+41 91[ ]+xchg[ ]+%eax,%r9d[ ]*(#.*)*
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[ ]*[0-9a-f]+:[ ]+41 91[ ]+xchg[ ]+%eax,%r9d[ ]*(#.*)*
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[ ]*[0-9a-f]+:[ ]+93[ ]+xchg[ ]+%eax,%ebx[ ]*(#.*)*
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[ ]*[0-9a-f]+:[ ]+93[ ]+xchg[ ]+%eax,%ebx[ ]*(#.*)*
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[ ]*[0-9a-f]+:[ ]+66 41 90[ ]+xchg[ ]+%ax,%r8w[ ]*(#.*)*
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[ ]*[0-9a-f]+:[ ]+66 41 90[ ]+xchg[ ]+%ax,%r8w[ ]*(#.*)*
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[ ]*[0-9a-f]+:[ ]+66 41 91[ ]+xchg[ ]+%ax,%r9w[ ]*(#.*)*
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[ ]*[0-9a-f]+:[ ]+66 41 91[ ]+xchg[ ]+%ax,%r9w[ ]*(#.*)*
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[ ]*[0-9a-f]+:[ ]+48 0f 01 e0[ ]+smsw[ ]+%rax[ ]*(#.*)*
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[ ]*[0-9a-f]+:[ ]+0f 01 e0[ ]+smsw[ ]+%eax[ ]*(#.*)*
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[ ]*[0-9a-f]+:[ ]+66 0f 01 e0[ ]+smsw[ ]+%ax[ ]*(#.*)*
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@ -397,6 +397,16 @@
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xchg %rax,%rax # -- -- -- -- 90
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rex64 xchg %rax,%rax # -- -- -- 48 90
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xchg %rax,%r8 # -- -- -- 49 90
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xchg %eax,%r8d # -- -- -- 41 90
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xchg %r8d,%eax # -- -- -- 41 90
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xchg %eax,%r9d # -- -- -- 41 91
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xchg %r9d,%eax # -- -- -- 41 91
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xchg %ebx,%eax # -- -- -- 93
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xchg %eax,%ebx # -- -- -- 93
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xchg %ax,%r8w # -- -- -- 66 41 90
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xchg %r8w,%ax # -- -- -- 66 41 90
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xchg %ax,%r9w # -- -- -- 66 41 91
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xchg %r9w,%ax # -- -- -- 66 41 91
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smsw %rax # -- -- -- 48 0F 01 e0
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smsw %eax # -- -- -- -- 0F 01 e0
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@ -1,3 +1,16 @@
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2003-03-21 H.J. Lu <hongjiu.lu@intel.com>
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PR binutils/4218
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* i386-dis.c (PREGRP38): New.
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(dis386): Use PREGRP38 for 0x90.
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(prefix_user_table): Add PREGRP38.
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(print_insn): Set uses_REPZ_prefix to 1 for pause.
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(NOP_Fixup1): Properly handle REX bits.
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(NOP_Fixup2): Likewise.
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* i386-opc.c (i386_optab): Allow %eax with xchg in 64bit.
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Allow register with nop.
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2007-03-20 DJ Delorie <dj@redhat.com>
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* m32c-asm.c: Regenerate.
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@ -467,6 +467,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
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#define PREGRP35 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 35 } }
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#define PREGRP36 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 36 } }
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#define PREGRP37 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 37 } }
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#define PREGRP38 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 38 } }
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#define X86_64_0 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 0 } }
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@ -692,7 +693,7 @@ static const struct dis386 dis386[] = {
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{ "movD", { Sw, Sv } },
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{ "popU", { stackEv } },
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/* 90 */
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{ "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
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{ PREGRP38 },
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{ "xchgS", { RMeCX, eAX } },
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{ "xchgS", { RMeDX, eAX } },
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{ "xchgS", { RMeBX, eAX } },
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@ -2017,6 +2018,14 @@ static const struct dis386 prefix_user_table[][4] = {
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{ "(bad)", { XX } },
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{ "(bad)", { XX } },
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},
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/* PREGRP38 */
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{
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{ "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
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{ "pause", { XX } },
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{ "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
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{ "(bad)", { XX } },
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},
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};
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static const struct dis386 x86_64_table[][2] = {
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@ -3091,7 +3100,8 @@ print_insn (bfd_vma pc, disassemble_info *info)
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need_modrm = onebyte_has_modrm[*codep];
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uses_DATA_prefix = 0;
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uses_REPNZ_prefix = 0;
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uses_REPZ_prefix = 0;
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/* pause is 0xf3 0x90. */
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uses_REPZ_prefix = *codep == 0x90;
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uses_LOCK_prefix = 0;
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codep++;
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}
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@ -5284,17 +5294,15 @@ OP_0fae (int bytemode, int sizeflag)
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}
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/* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
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32bit mode and "xchg %rax,%rax" in 64bit mode. NOP with REPZ prefix
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is called PAUSE. We display "xchg %ax,%ax" instead of "data16 nop".
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*/
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32bit mode and "xchg %rax,%rax" in 64bit mode. */
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static void
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NOP_Fixup1 (int bytemode, int sizeflag)
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{
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if (prefixes == PREFIX_REPZ)
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strcpy (obuf, "pause");
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else if (prefixes == PREFIX_DATA
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|| ((rex & REX_MODE64) && rex != 0x48))
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if ((prefixes & PREFIX_DATA) != 0
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|| (rex != 0
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&& rex != 0x48
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&& address_mode == mode_64bit))
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OP_REG (bytemode, sizeflag);
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else
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strcpy (obuf, "nop");
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@ -5303,8 +5311,10 @@ NOP_Fixup1 (int bytemode, int sizeflag)
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static void
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NOP_Fixup2 (int bytemode, int sizeflag)
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{
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if (prefixes == PREFIX_DATA
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|| ((rex & REX_MODE64) && rex != 0x48))
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if ((prefixes & PREFIX_DATA) != 0
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|| (rex != 0
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&& rex != 0x48
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&& address_mode == mode_64bit))
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OP_IMREG (bytemode, sizeflag);
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}
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@ -144,12 +144,10 @@ const template i386_optab[] =
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xchg commutes: we allow both operand orders.
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In the 64bit code, xchg rax, rax is reused for new nop instruction. */
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{"xchg", 2, 0x90, X, CpuNo64, wl_Suf|ShortForm, { WordReg, Acc, 0 } },
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{"xchg", 2, 0x90, X, CpuNo64, wl_Suf|ShortForm, { Acc, WordReg, 0 } },
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{"xchg", 2, 0x90, X, Cpu64, wq_Suf|ShortForm, { Reg16|Reg64, Acc, 0 } },
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{"xchg", 2, 0x90, X, Cpu64, wq_Suf|ShortForm, { Acc, Reg16|Reg64, 0 } },
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{"xchg", 2, 0x86, X, 0, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } },
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{"xchg", 2, 0x86, X, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Reg, 0 } },
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{"xchg", 2, 0x90, X, 0, wlq_Suf|ShortForm, { WordReg, Acc, 0 } },
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{"xchg", 2, 0x90, X, 0, wlq_Suf|ShortForm, { Acc, WordReg, 0 } },
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{"xchg", 2, 0x86, X, 0, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } },
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{"xchg", 2, 0x86, X, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Reg, 0 } },
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/* In/out from ports. */
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/* XXX should reject %rax */
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@ -517,7 +515,7 @@ const template i386_optab[] =
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{"hlt", 0, 0xf4, X, 0, NoSuf, { 0, 0, 0} },
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{"nop", 1, 0x0f1f, X, Cpu686, wl_Suf|Modrm, { WordMem, 0, 0} },
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{"nop", 1, 0x0f1f, 0, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, 0, 0} },
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/* nop is actually "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
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32bit mode and "xchg %rax,%rax" in 64bit mode. */
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