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Implement missing powerpc extended mnemonics

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gas/
	* testsuite/gas/ppc/power8.d,
	* testsuite/gas/ppc/power8.s: Add miso.
	* testsuite/gas/ppc/power9.d,
	* testsuite/gas/ppc/power8.s: Add exser, msgsndu, msgclru.
opcodes/
	* ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
	Enable icbt for power5, miso for power8.
This commit is contained in:
Alan Modra 2020-08-10 15:08:27 +09:30
parent 5fbec329ec
commit 8b2742a156
7 changed files with 35 additions and 7 deletions
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7
gas/ChangeLog
View File

@ -1,3 +1,10 @@
2020-08-10 Alan Modra <amodra@gmail.com>
* testsuite/gas/ppc/power8.d,
* testsuite/gas/ppc/power8.s: Add miso.
* testsuite/gas/ppc/power9.d,
* testsuite/gas/ppc/power8.s: Add exser, msgsndu, msgclru.
2020-08-10 Alan Modra <amodra@gmail.com>
* testsuite/gas/ppc/power8.d: Update.

2
gas/testsuite/gas/ppc/power8.d
View File

@ -310,4 +310,6 @@ Disassembly of section \.text:
.*: (4d 89 04 61|61 04 89 4d) bgttarl cr2
.*: (4d 89 04 61|61 04 89 4d) bgttarl cr2
.*: (4d 89 1c 61|61 1c 89 4d) bctarl 12,4\*cr2\+gt,3
.*: (7f 5a d3 78|78 d3 5a 7f) miso
.*: (7f 5a d3 78|78 d3 5a 7f) miso
#pass

2
gas/testsuite/gas/ppc/power8.s
View File

@ -302,3 +302,5 @@ power8:
bctarl 0b01100,4*cr2+gt
bctarl 0b01100,4*cr2+gt,0
bctarl 0b01100,4*cr2+gt,3
or 26,26,26
miso

4
gas/testsuite/gas/ppc/power9.d
View File

@ -399,4 +399,8 @@ Disassembly of section \.text:
.*: (7c 20 20 ac|ac 20 20 7c) dcbfl 0,r4
.*: (7c 60 28 ac|ac 28 60 7c) dcbflp 0,r5
.*: (7c 60 28 ac|ac 28 60 7c) dcbflp 0,r5
.*: (63 ff 00 00|00 00 ff 63) exser
.*: (63 ff 00 00|00 00 ff 63) exser
.*: (7c 00 18 9c|9c 18 00 7c) msgsndu r3
.*: (7c 00 d8 dc|dc d8 00 7c) msgclru r27
#pass

4
gas/testsuite/gas/ppc/power9.s
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@ -390,3 +390,7 @@ power9:
dcbf 0,4,1
dcbflp 0,5
dcbf 0,5,3
ori 31,31,0
exser
msgsndu 3
msgclru 27

5
opcodes/ChangeLog
View File

@ -1,3 +1,8 @@
2020-08-10 Alan Modra <amodra@gmail.com>
* ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
Enable icbt for power5, miso for power8.
2020-08-10 Alan Modra <amodra@gmail.com>
* ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over

18
opcodes/ppc-opc.c
View File

@ -6114,6 +6114,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"rlnm.", M(23,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}},
{"nop", OP(24), 0xffffffff, PPCCOM, PPCVLE, {0}},
{"exser", 0x63ff0000, 0xffffffff, POWER9, PPCVLE, {0}},
{"ori", OP(24), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}},
{"oril", OP(24), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}},
@ -6236,7 +6237,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"ldx", X(31,21), X_MASK, PPC64, 0, {RT, RA0, RB}},
{"icbt", X(31,22), X_MASK, BOOKE|PPCE300|PPCA2|PPC476, 0, {CT, RA0, RB}},
{"icbt", X(31,22), X_MASK, POWER5|BOOKE|PPCE300, 0, {CT, RA0, RB}},
{"lwzx", X(31,23), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
{"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}},
@ -6354,6 +6355,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"mulhw", XO(31,75,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
{"mulhw.", XO(31,75,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
{"msgsndu", XRTRA(31,78,0,0), XRTRA_MASK, POWER9, 0, {RB}},
{"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA, RS, RB}},
{"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA, RS, RB}},
@ -6387,6 +6389,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"lxvrdx", X(31,109), XX1_MASK, POWER10, 0, {XT6, RA0, RB}},
{"msgclru", XRTRA(31,110,0,0), XRTRA_MASK, POWER9, 0, {RB}},
{"mvidsplt", X(31,110), X_MASK, E6500, 0, {VD, RA, RB}},
{"mtsrdin", X(31,114), XRA_MASK, PPC64, 0, {RS, RB}},
@ -7051,14 +7054,15 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"sthux", X(31,439), X_MASK, COM, 0, {RS, RAS, RB}},
{"mdors", 0x7f9ce378, 0xffffffff, E500MC, 0, {0}},
{"miso", 0x7f5ad378, 0xffffffff, E6500, 0, {0}},
/* The "yield", "mdoio" and "mdoom" instructions are extended mnemonics for
"or rX,rX,rX", with rX being r27, r29 and r30 respectively. */
/* or 26,26,26 */
{"miso", 0x7f5ad378, 0xffffffff, POWER8|E6500, 0, {0}},
/* or 27,27,27 */
{"yield", 0x7f7bdb78, 0xffffffff, POWER7, 0, {0}},
/* or 28,28,28 */
{"mdors", 0x7f9ce378, 0xffffffff, E500MC, 0, {0}},
/* or 29,29,29 */
{"mdoio", 0x7fbdeb78, 0xffffffff, POWER7, 0, {0}},
/* or 30,30,30 */
{"mdoom", 0x7fdef378, 0xffffffff, POWER7, 0, {0}},
{"mr", XRC(31,444,0), X_MASK, COM, 0, {RA, RSB}},
{"or", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RB}},